AD800-45BQ

AD800 AD | Alldatasheet

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FILTERØ DET fDET å COMPENSATING ZERO RECOVERED CLOCK OUTPUT RETIMING DEVICE REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Clock Recovery and Data Retiming Phase-Locked Loop AD800/AD802* Tel: 617/329-4700 Fax: 617/326-8703 PRODUCT DESCRIPTION The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and

52 Mbps STS-1 are supported by the AD800-45 and

AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155. Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. The loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 × 10 5 bit periods when using a damping factor of 5.

FEATURES

44.736 Mbps—DS-3

51.84 Mbps—STS-1

155.52 Mbps—STS-3 or STM-1

Accepts NRZ Data, No Preamble Required Recovered Clock and Retimed Data Outputs Phase-Locked Loop Type Clock Recovery—No Crystal Required Random Jitter: 20 8 Peak-to-Peak Pattern Jitter: Virtually Eliminated 10KH ECL Compatible Single Supply Operation: –5.2 V or +5 V Wide Operating Temperature Range: –40 8C to +85 8C During the process of acquisition the frequency detector provides a Frequency Acquisition (FRAC) signal which indicates that the device has not yet locked onto the input data. This signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. Once the circuit has acquired frequency lock no pulses occur at the FRAC output. The inclusion of a precisely trimmed VCO in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components. The VCO provides a clock output within ± 20% of the device center frequency in the absence of input data. The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. Total loop jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask programmable fractional loop bandwidth. The AD800, used for data rates < 90 Mbps, has been designed with a nominal loop bandwidth of 0.1% of the center frequency. The AD802, used for data rates in excess of 90 Mbps, has a loop bandwidth of 0.08% of center frequency. All of the devices operate with a single +5 V or –5.2 V supply. *Protected by U.S. Patent No. 5,027,085.

REV. B–2– AD800/AD802–SPECIFICATIONS (VEE = VMIN to VMAX, VCC = GND, TA = TMIN to TMAX, Loop Damping Factor = 5, unless otherwise noted) AD800-45BQ AD800-52BR AD802-155KR/BR Parameter1 Condition Min Typ Max Min Typ Max Min Typ Max Units NOMINAL CENTER FREQUENCY 44.736 51.84 155.52 MHz OPERATING TEMPERATURE K Grade 0 70 °C RANGE (TMIN to TMAX) B Grade –40 85 –40 85 –40 85 °C TRACKING RANGE 43 45.5 49 53 155 156 Mbps CAPTURE RANGE 43 45.5 49 53 155 156 Mbps STATIC PHASE ERROR ρ = 1, TA = +25°C, VEE = –5.2 V 2 10 2 10 14 30 Degrees ρ = 1 3 11.5 3 11.5 18 37 Degrees SETUP TIME t SU (Figure 1) 2.06 2.37 ns TRANSITIONLESS DATA RUN 240 240 240 Bit Periods OUTPUT JITTER ρ = 1 2 2 3.5 Degrees rms JITTER TOLERANCE f = 10 Hz 2,500 2,500 3,000 Unit Intervals f = 2.3 kHz 6.5 Unit Intervals f = 30 kHz 0.47 Unit Intervals f = 1 MHz 0.47 Unit Intervals f = 30 Hz 830 Unit Intervals f = 300 Hz 83 Unit Intervals f = 2 kHz 7.4 Unit Intervals f = 20 kHz 0.47 Unit Intervals f = 6.5 kHz 2.0 7.6 Unit Intervals f = 65 kHz 0.26 0.9 Unit Intervals JITTER TRANSFER Damping Factor Capacitor, C D ζ = 1, Nominal 8.2 6.8 2.2 nF ζ = 5, Nominal 0.22 0.15 0.047 µF ζ = 10, Nominal 0.82 0.68 0.22 µF Peaking ζ = 1, Nominal T A = +25°C, VEE = –5.2 V 2 2 2 dB ζ = 5, Nominal T A = +25°C, VEE = –5.2 V 0.08 0.08 0.08 dB ζ = 10, Nominal T A = +25°C, VEE = –5.2 V 0.02 0.02 0.02 dB Bandwidth 45 52 130 kHz ACQUISITION TIME ρ = 1/2 ζ = 1 1 × 104 1 × 104 1.5 × 104 Bit Periods TA = +25°C ζ = 5 3 × 105 8 × 105 3 × 105 8 × 105 4 × 105 8 × 105 Bit Periods VEE = –5.2 V ζ = 10 8 × 105 8 × 105 1.4 × 106 Bit Periods POWER SUPPLY Current T A = +25°C, VEE = –5.2 V 125 170 125 170 140 180 mA 180 180 205 mA INPUT VOLTAGE LEVELS T A = +25°C OUTPUT VOLTAGE LEVELS T A = +25°C INPUT CURRENT LEVELS T A = +25°C Input Logic High, I IH 125 125 125 µA Input Logic Low, I IL 80 80 80 µA OUTPUT SLEW TIMES T A = +25°C SYMMETRY ρ = 1/2, TA = +25°C Recovered Clock Output V EE = –5.2 V 45 55 45 55 45 55 % NOTES 1Refer to Glossary for parameter definition. Specifications subject to change without notice.

Figure 1. Recovered Clock Skew and Setup

1 DATAOUT Differential Retimed Data Output

2 DATAOUT Differential Retimed Data Output

4 CLKOUT Differential Recovered Clock Output

5 CLKOUT Differential Recovered Clock Output

10 ASUBST Analog Substrate

11 CF 2 Loop Damping Capacitor Input

12 CF 1 Loop Damping Capacitor Input

13 AV CC Analog Ground

14 V CC1 Digital Ground

15 V EE Digital VEE

16 DATAIN Differential Data Input

17 DATAIN Differential Data Input

18 SUBST Digital Substrate

19 FRAC Differential Frequency Acquisition

20 FRAC Differential Frequency Acquisition

systems. Typical specifications indicate mean measurements. system-to-test system variation contribute to each guardband. prohibit direct measurement of static phase error. (0 ≤ ρ ≤ 1) of data transitions to clock periods. recovered clock causes jitter on the retimed data. phase modulation, and is usually specified in unit intervals.

Figure 15. AD802-155 Center Frequency vs. Temperature Figure 17. AD802-155 Capture Range, Tracking Range vs. Figure 19. AD802-155 Minimum Acquisition Range vs. Figure 16. AD802-155 Output Jitter vs. Temperature

1 UI – Pk-Pk

Figure 18. AD802-155 Jitter Tolerance Figure 20. AD802-155 Bit Error Rate vs. Input Jitter

10 TURNS

Figure 25. Power Supply Noise Sensitivity Test Circuit, PECL Configuration Figure 26. Evaluation Board Schematic, Negative Supply

REV. B–12– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Small Outline IC Package (R-20) 11 0 1120 0.50 (1.27) BSC 0.015 (0.38) 0.007 (0.18) 0.019 (0.48) 0.014 (0.36) 0.011 (0.28) 0.004 (0.10) 0.050 (1.27) 0.016 (0.40) 0.104 (2.64) 0.093 (2.36) 0.419 (10.65) 0.394 (10.00) 0.300 (7.60) 0.292 (7.40) 0.512 (13.00) 0.496 (12.60) 20-Pin Cerdip Package (Q-20) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15° 0.005 (0.13) MIN PIN 1 0.098 (2.49) MAX 0.310 (7.87) 0.220 (5.59) 1.060 (26.92) MAX 0.200 (5.08) MAX 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE C1725a–7.5–12/93PRINTED IN U.S.A.