AD7922

AD7912/AD7922 2-Channel, 2.35 V to 5.2 V, 1 MSPS, 10-/12-Bit ADCs Data Sheet (REV. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 32

Technical content

2-Channel, 2.35 V to 5.25 V,

1 MSPS, 10-/12-Bit ADCs

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power: 4.8 mW typ at 1 MSPS with 3 V supplies 15.5mW typ at 1 MSPS with 5 V supplies Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 1 µA maximum Daisy-chain mode 8-lead TSOT package 8-lead MSOP package

APPLICATIONS

Battery-powered systems: Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION The AD7912/AD79221 are 10-bit and 12-bit, high speed, low power, 2-channel successive approximation ADCs, respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates of up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 6 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The conversion rate is determined by the SCLK signal. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. The channel to be converted is selected through the DIN pin, and the mode of operation is controlled by CS . The serial data stream from the DOUT pin has a channel identifier bit and mode identifier bit, which provide information about the converted channel and the current mode of operation. FUNCTIONAL BLOCK DIAGRAM 04351-0-001 T/H CONTROL LOGIC 10-/12-BIT SUCCESSIVE APPROXIMATION ADC GND VDD AD7912/AD7922 VIN0 VIN1 SCLK DOUT CS DIN MUX Figure 1. Several AD7912/AD7922 can be connected together in a daisy chain. The AD7912/AD7922 feature a daisy-chain mode that allows the user to read the conversion results from the ADCs contained in the chain. The AD7912/AD7922 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from V DD, thereby allowing the widest dynamic input range to the ADC. PRODUCT HIGHLIGHTS 1. 2-channel, 1 MSPS, 10-/12-bit ADCs in TSOT package. 2. High throughput with low power consumption. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Average power consumption is reduced when the power-down mode is used while not converting. Current consumption is 1 µA maximum and 50 nA typically when in power-down mode. 4. Daisy-chain mode. 5. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. 1 Protected by U.S. Patent Number 6,681,332.

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS AD7912 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V , fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter A Grade 1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 100 kHz sine wave Signal-to- Noise + Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD)2 −71 dB max Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max Intermodulation Distortion (IMD)2 Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −83 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity2 ±0.5 LSB max Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error2 ±0.5 LSB max Offset Error Match2, 3 ±0.3 LSB max Gain Error2 ±0.5 LSB max Gain Error Match2, 3 ±0.3 LSB max Total Unadjusted Error (TUE)2 ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V DD V DC Leakage Current ±0.3 µA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 (V DD) V min 2.35 V ≤ V DD ≤ 2.7 V 2 V min 2.7 V < V DD ≤ 5.25 V Input Low Voltage, VINL 0.3 V max V DD = 2.35 V 0.2 (V DD) V max 2.35 V < V DD ≤ 2.7 V 0.8 V max 2.7 V < V DD ≤ 5.25 V Input Current, IIN, SCLK Pin ±0.3 µA max Typically 8 nA, V IN = 0 V or VDD Input Current, IIN, CS Pin ±0.3 µA max Input Current, IIN, DIN Pin ±0.3 µA max Input Capacitance, CIN3 5 pF max LOGIC OUTPUTS Output High Voltage, VOH V DD − 0.2 V min I SOURCE = 200 µA, VDD = 2.35 V to 5.25 V Output Low Voltage, VOL 0.2 V max I SINK = 200 µA Floating-State Leakage Current ±0.3 µA max Floating-State Output Capacitance3 5 pF max Output Coding Straig ht (natural) binary

Rev. 0 | Page 4 of 32 Parameter A Grade 1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 777 ns max 14 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or V DD Normal Mode (Static) 3 mA typ V DD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ V DD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max V DD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 2 mA max V DD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 µA ma x SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.48 mA typ V DD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS 0.26 mA typ V DD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max V DD = 5 V, fSAMPLE = 1 MSPS 6 mW max V DD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 µW max V DD = 5 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.

Rev. 0 | Page 5 of 32 AD7922 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V , fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter A Grade 1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 100 kHz sine wave Signal-to-Noise + Distortion (SINAD)2 70 dB min 72 dB typ Signal-to-Noise Ratio (SNR)2 71 dB min 72.5 dB typ Total Harmonic Distortion (THD)2 −81 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −84 dB typ Intermodulation Distortion (IMD)2 Second-Order Terms −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Terms −86 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±1.5 LSB max V DD = 2.35 V to 3.6V ±0.7 LSB typ V DD = 4.75 V to 5.25V Differential Nonlinearity2 Guaranteed no missed codes to 12 bits −0.9/+1.5 LSB max V DD = 2.35 V to 3.6V −0.7/+1.2 LSB typ V DD = 4.75 V to 5.25V Offset Error2 ±1 LSB max V DD = 2.35 V to 3.6V ±0.1 LSB typ V DD = 4.75 V to 5.25V Offset Error Match2, 3 ±0.5 LSB max V DD = 2.35 V to 3.6V ±0.02 LSB typ V DD = 4.75 V to 5.25V Gain Error2 ±2 LSB max V DD = 2.35 V to 3.6V ±0.5 LSB typ V DD = 4.75 V to 5.25V Gain Error Match2, 3 ±1 LSB max V DD = 2.35 V to 3.6V ±0.2 LSB typ V DD = 4.75 V to 5.25V Total Unadjusted Error (TUE)2 ±1.5 LSB max V DD = 2.35 V to 3.6V ±0.5 LSB typ V DD = 4.75 V to 5.25V ANALOG INPUT Input Voltage Ranges 0 to V DD V DC Leakage Current ±0.3 µA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 (V DD) V min 2.35 V ≤ V DD ≤ 2.7 V 2 V min 2.7 V < V DD ≤ 5.25 V Input Low Voltage, VINL 0.3 V max V DD = 2.35 V 0.2 (V DD) V max 2.35 V < V DD ≤ 2.7 V 0.8 V max 2.7 V < V DD ≤ 5.25 V Input Current, IIN, SCLK Pin ±0.3 µA max Typically 8 nA, V IN = 0 V or VDD Input Current, IIN, CS Pin ±0.3 µA max Input Current, IIN, DIN Pin ±0.3 µA max Input Capacitance, CIN3 5 pF max

Rev. 0 | Page 6 of 32 Parameter A Grade 1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH V DD − 0.2 V min I SOURCE = 200 µA; VDD = 2.35 V to 5.25 V Output Low Voltage, VOL 0.2 V max I SINK = 200 µA Floating-State Leakage Current ±0.3 µA max Floating-State Output Capacitance3 5 pF max Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 888 ns max 16 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max S ee the Serial Interface section POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or V DD Normal Mode (Static) 3 mA typ V DD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ V DD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max V DD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 2 mA max V DD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 µA ma x SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.5 mA typ V DD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS 0.28 mA typ V DD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max V DD = 5 V, fSAMPLE = 1 MSPS 6 mW max V DD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 µW max V DD = 5 V 3 µW max V DD = 3 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V . VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.

18 MHz max

1 Mark/space ratio for SCLK input is 40/60 to 60/40. 2 Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. time of the part and is independent of the bus loading. 6 See the Power-Up Time section. Figure 2. Load Circuit for Digital Output Timing Specifications Figure 3. Access Time after SCLK Falling Edge Figure 4. Hold Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State

Rev. 0 | Page 9 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to GND −0.3 V to +7 V Analog Input Voltage to GND −0.3 V to V DD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V DD + 0.3 V Input Current to Any Pin except Supplies1 ±10 mA Operating Temperature Range Commercial (A Grade) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 207°C/W θJA Thermal Impedance 205.9°C/W θJC Thermal Impedance 43.74°C/W Lead Temperature Soldering Reflow (10 s to 30 s) 235 (0/+5)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 11 of 32 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7912/ AD7922, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00…000) to (00… 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match The difference in offset error between any two channels. Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal, that is, V DD − 1 LSB after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Tot a l Una dju ste d E r ror A comprehensive specification that includes gain error, linearity error, and offset error. Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal of 20 kHz to 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a 10 kHz signal. The figure is given worst case across both channels for the AD7912/AD7922. Track-and-Hold Acquisition Time The time required for the output of the track-and-hold amplifier to reach its final value within ±1 LSB after the end of conversion. The track-and-hold amplifier returns to track mode at the end of conversion. See the Serial Interface section for more details. Signal-to-Noise + Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by √2, and the rms value for the quantization noise is q/√12. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as dB761026 .N.SNR += Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit converter, SNR is 62 dB. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental, which is defined as V VVVVV THD ++++ log20)dB( where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fs /2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specifica- tion is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Rev. 0 | Page 12 of 32 Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7912/AD7922 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third- order terms are specified separately. The calculation of the intermodulation distortion is as in the THD specification, where it is defined as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.

with a SCLK frequency of 18 MHz for the AD7922. with an SCLK frequency of 18 MHz for the AD7922. with an SCLK frequency of 18 MHz. for different operating temperatures.

8192 POINT FFT

Figure 10. AD7922 Dynamic Performance at 1 MSPS Figure 11. AD7912 Dynamic Performance at 1 MSPS Figure 12. AD7922 SINAD vs. Input Frequency at 1 MSPS Figure 13. AD7922 SNR vs. Input Frequency at 1 MSPS

Rev. 0 | Page 18 of 32 MODES OF OPERATION The three modes of operation of the AD7912/AD7922 are normal mode, power-down mode, and daisy-chain mode. The mode of operation is selected by controlling the logic state of the CS signal. The point at which CS is pulled high after the conversion has been initiated determines whether the AD7912/AD7922 enter power-down mode or change to daisy- chain mode. Similarly, if already in daisy-chain mode, CS can control whether the device returns to normal operation or enters power-down mode. The user can also change from daisy- chain mode to normal mode by writing to the DIN pin, as outlined in the DIN Input section. Power-down mode is designed to provide flexible power management options and to optimize the ratio of power dissipation to throughput rate for different application requirements. Daisy-chain mode is intended for applications where fast throughput rate is not required and more than one AD7912/AD7922 have been connected in a daisy chain, as shown in Figure 33. NORMAL MODE Normal mode is intended for the fastest throughput rate performance. The user does not have to worry about any power-up time, because the AD7912/AD7922 remain fully powered all the time. Figure 26 shows the operation of the AD7912/AD7922 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS . If CS is brought high after the 10th SCLK falling edge and before the 12th SCLK falling edge, then the device enters daisy-chain mode, as shown in Figure 27. The conversion is terminated and DOUT goes back into three-state. If CS is brought high after the 13th SCLK falling edge, but before the end of tCONVERT, the conversion is terminated and DOUT goes back into three-state, but the part remains in normal mode. For the AD7922, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7912, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. CS can idle high until the next conversion or can idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (DOUT has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. POWER-DOWN MODE Power-down mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions can be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7912/ AD7922 are in power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 28. Once CS has been brought high in this window of SCLKs, then the part enters power-down mode, the conversion that was initiated by the falling edge of CS is termi- nated, and DOUT goes back into three-state. If CS is brought high before the second SCLK falling edge, then the part remains in normal mode and does not power down. This helps to avoid accidental power-down due to glitches on the CS line. To exit this mode of operation and power the AD7912/AD7922 up again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs have elapsed and valid data results from the next conversion, as shown in Figure 29. If CS is brought high before the 10th falling edge of SCLK, then the AD7912/AD7922 go back into power- down mode. This helps to avoid accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. Therefore, although the device might begin to power up on the falling edge of CS, it powers down again on the rising edge of CS, as long as this occurs before the 10th SCLK falling edge.

equidistant sampling is implemented by the DSP . out two trailing zeros to fill the 16-bit word. outputs, and the MSB is shifted first. Figure 41. Interfacing to the DSP563xx

Rev. 0 | Page 28 of 32 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7912/AD7922 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7912/ AD7922 are in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7912/AD7922. Avoid running digital lines under the device, because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7912/AD7922 to avoid noise coupling. The power supply lines to the AD7912/AD7922 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A micro- strip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also very important. The analog supply should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. T o achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the V DD and GND pins to a minimum with short track lengths connecting the respective pins.

Rev. 0 | Page 29 of 32 EVALUATING AD7912/AD7922 PERFORMANCE The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2. The EV AL-CONTROL BRD2 can be used in conjunction with the AD7912CB/AD7922CB evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator to demonstrate and evaluate the ac and dc performance of the AD7912/AD7922. The software allows the user to perform ac (Fast Fourier Transform) and dc (histograms of codes) tests on the AD7912/AD7922. See the AD7912/AD7922 Technical Note for more information. The technical note is included in the software, and it can also be found on the www.analog.com website under the Design Tools link on the AD7912/AD7922 product page.

Rev. 0 | Page 30 of 32 OUTLINE DIMENSIONS 0.80 0.60 0.40 4.90 BSC PIN 1

0.65 BSC

3.00 BSC SEATING PLANE 0.15 0.00 0.38 0.22

1.10 MAX

3.00 BSC COPLANARITY 0.10 0.23 0.08 COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 42. 8-Lead Mini Small Outline Package [MSOP]

2.90 BSC

1.60 BSC

0.10 MAX

0.84 SEATING

2.80 BSC

Figure 43. 8-Lead Thin Small Outline Transistor Package [TSOT]

Description

AD7912ARM −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 1 AD7912ARM-REEL −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 3000 AD7912ARM-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 1000 AD7912AUJ-R2 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 C1A 250 AD7912AUJ-REEL7 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 C1A 3000 AD7922ARM −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 1 AD7922ARM-REEL −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 3000 AD7922ARM-REEL7 −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 1000 AD7922AUJ-R2 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 C1B 250 AD7922AUJ-REEL7 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 C1B 3000 EVAL-AD7912CB2 Evaluation Board EVAL-AD7922CB2 Evaluation Board EVAL-CONTROL BRD23 Evaluation Control Board 1 Linearity error here refers to integral nonlinearity. 2 This evaluation board can be used standalone or in conjunction with the EVAL-CONTROL BRD2 for evaluation or demonstration purposes. 3 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, order a particular ADC evaluation board (EVAL-AD7922 CB, for example), the EVAL-CONTROL BRD2, and a 12 ac transformer. See the relevant evaluation board technical note for more information.

Rev. 0 | Page 31 of 32 NOTES

Rev. 0 | Page 32 of 32 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04351–0–4/04(0)