AD7920

AD7910 AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD7910/AD7920* 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70

FEATURES

Throughput Rate: 250 kSPS Specified for V DD of 2.35 V to 5.25 V Low Power: 3.6 mW Typ at 250 kSPS with 3 V Supplies 12.5 mW Typ at 250 kSPS with 5 V Supplies Wide Input Bandwidth: 71 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI ® /QSPI™/MICROWIRE™/DSP Compatible Standby Mode: 1 /H9262A Max 6-Lead SC70 Package 8-Lead MSOP Package

APPLICATIONS

Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical Sensors FUNCTIONAL BLOCK DIAGRAM 10-/12-BIT SUCCESSIVE- APPROXIMA TION ADC CONTROL LOGIC AD7910/AD7920 GND VDD VIN SCLK SDA T A CS T/H GENERAL DESCRIPTION The AD7910/AD7920 are, respectively, 10-bit and 12-bit, high speed, low power, successive-approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 250 kSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7910/AD7920 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from V DD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to V DD. The conversion rate is determined by the SCLK. PRODUCT HIGHLIGHTS 1. 10-/12-Bit ADCs in SC70 and MSOP Packages. 2. Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when power-down mode is used while not convert- ing. The part also features a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 /H9262A max and 50 nA typically when in power-down mode. 4. Reference Derived from the Power Supply. 5. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. *Protected by U.S.Patent No. 6,681,332.

REV. B–2– AD7910–SPECIFICATIONS1 (VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.) Parameter A Grade 1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 100 kHz Sine Wave Signal-to-Noise + Distortion (SINAD) 3 61 dB min Total Harmonic Distortion (THD) 3 –72 dB max Peak Harmonic or Spurious Noise (SFDR) 3 –73 dB max Intermodulation Distortion (IMD) 3 Second-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth 13.5 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity ± 0.5 LSB max Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 10 Bits Offset Error 3, 4 ± 1L S B m a x Gain Error3, 4 ± 1L S B m a x Total Unadjusted Error (TUE) 3, 4 ± 1.2 LSB max ANALOG INPUT Input Voltage Ranges 0 to V DD V DC Leakage Current ± 0.5 mA max Input Capacitance 20 pF typ Track-and-Hold in Track, 6 pF Typ when in Hold LOGIC INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max V DD = 5 V

0.4 V max V DD = 3 V

Input Current, IIN, SCLK Pin ± 0.5 mA max Typically 10 nA, V IN = 0 V or VDD Input Current, IIN, CS Pin ± 10 nA typ Input Capacitance, C IN 5 5 pF max LOGIC OUTPUTS Output High Voltage, V OH VDD – 0.2 V min I SOURCE = 200 mA, VDD = 2.35 V to 5.25 V Output Low Voltage, V OL 0.4 V max I SINK = 200 mA Floating-State Leakage Current ± 1 mA max Floating-State Output Capacitance 5 5 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 2.8 ms max 14 SCLK Cycles with SCLK at 5 MHz Track-and-Hold Acquisition Time 3 250 ns max Throughput Rate 250 kSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or V DD Normal Mode(Static) 2.5 mA typ V DD = 4.75 V to 5.25 V, SCLK On or Off 1.2 mA typ V DD = 2.35 V to 3.6 V, SCLK On or Off Normal Mode (Operational) 3 mA max V DD = 4.75 V to 5.25 V, f SAMPLE = 250 kSPS 1.4 mA max V DD = 2.35 V to 3.6 V, f SAMPLE = 250 kSPS Full Power-Down Mode 1 mA max Typically 50 nA Power Dissipation6 Normal Mode (Operational) 15 mW max V DD = 5 V, fSAMPLE = 250 kSPS 4.2 mW max V DD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 mW max V DD = 5 V 3 mW max V DD = 3 V NOTES 1Temperature range from –40 ∞C to +85∞C. 2Operational from V DD = 2.0 V, with input high voltage (V INH) 1.8 V min. 3See Terminology section. 4SC70 values guaranteed by characterization. 5Guaranteed by characterization. 6See Power Vs. Throughput Rate section. Specifications subject to change without notice.

REV. B AD7910/AD7920 –3– AD7920–SPECIFICATIONS1 (VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.) Parameter A Grade 1, 2 B Grade1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 100 kHz Sine Wave Signal-to-Noise + Distortion (SINAD) 3 70 70 dB min V DD = 2.35 V to 3.6 V, TA = 25∞C 69 69 dB min V DD = 2.4 V to 3.6 V 71.5 71.5 dB typ V DD = 2.35 V to 3.6 V 69 69 dB min V DD = 4.75 V to 5.25 V, T A = 25∞C 68 68 dB min V DD = 4.75 V to 5.25 V Signal-to-Noise Ratio (SNR) 3 71 71 dB min V DD = 2.35 V to 3.6 V, TA = 25∞C 70 70 dB min V DD = 2.4 V to 3.6 V 70 70 dB min V DD = 4.75 V to 5.25 V, T A = 25∞C 69 69 dB min V DD = 4.75 V to 5.25 V Total Harmonic Distortion (THD) 3 –80 –80 dB typ Peak Harmonic or Spurious Noise (SFDR)3 –82 –82 dB typ Intermodulation Distortion (IMD) 3 Second-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 13.5 13.5 MHz typ @ 3 dB 22 MHz typ @ 0.1 dB DC ACCURACY B Grade 4 Resolution 12 12 Bits Integral Nonlinearity 3 ± 1.5 LSB max ± 0.75 LSB typ Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits ± 0.75 LSB typ Offset Error3, 5 ± 1.5 LSB max ± 1.5 ± 0.2 LSB typ Gain Error3, 5 ± 1.5 LSB max ± 1.5 ± 0.5 LSB typ Total Unadjusted Error (TUE) 3,5 ± 2 LSB max ANALOG INPUT Input Voltage Ranges 0 to V DD 0 to VDD V DC Leakage Current ± 0.5 ± 0.5 mA max Input Capacitance 20 20 pF typ Track-and-Hold in Track, 6 pF Typ when in Hold LOGIC INPUTS Input High Voltage, V INH 2.4 2.4 V min 1.8 1.8 V min V DD = 2.35 V Input Low Voltage, V INL 0.8 0.8 V max V DD = 3.6 V to 5.25 V 0.4 0.4 V max V DD = 2.35 V to 3.6 V Input Current, IIN, SCLK Pin ± 0.5 ± 0.5 mA max Typically 10 nA, V IN = 0 V or VDD Input Current, IIN, CS Pin ± 10 ± 10 nA typ Input Capacitance, C IN 6 5 5 p F max LOGIC OUTPUTS Output High Voltage, V OH VDD – 0.2 V DD – 0.2 V min I SOURCE = 200 mA, VDD = 2.35 V to 5.25 V Output Low Voltage, V OL 0.4 0.4 V max I SINK = 200 mA Floating-State Leakage Current ± 1 ± 1 mA max Floating-State Output Capacitance 6 55p F max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 3.2 3.2 ms max 16 SCLK Cycles with SCLK at 5 MHz Track-and-Hold Acquisition Time 3 250 250 ns max Throughput Rate 250 250 kSPS max See Serial Interface Section

REV. B–4– AD7910/AD7920 AD7910/AD7920 Parameter Limit at T MIN, TMAX Unit Description fSCLK 2 10 kHz min 3

5 MHz max

tCONVERT 14 /H11003 tSCLK AD7910 16 /H11003 tSCLK AD7920 tQUIET 50 ns minM inimum Quiet Time Required between Bus Relinquish and Start of Next Conversion t1 10 ns min Minimum CS Pulse Width t2 10 ns min CS to SCLK Setup Time 4 22 ns max Delay from CS until SDATA Three-State Disabled 4 40 ns max Data Access Time after SCLK Falling Edge t5 0.4 /H11003 tSCLK ns min SCLK Low Pulse Width t6 0.4 /H11003 tSCLK ns min SCLK High Pulse Width

5 SCLK to Data Valid Hold Time

10 ns min V DD £ 3.3 V 9.5 ns min 3.3 V < V DD £ 3.6 V 7 ns min V DD > 3.6 V 6 36 ns max SCLK Falling Edge to SDATA Three-State See Note 7 ns min SCLK Falling Edge to SDATA Three-State tPOWER-UP 8 1 ms max Power-Up Time from Full Power-Down NOTES 1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3Minimum fSCLK at which specifications are guaranteed. 5Measured with a 50 pF load capacitor. 6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the Timing Characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7t7 values apply to t 8 minimum values also. 8See Power-Up Time section. Specifications subject to change without notice. AD7920–SPECIFICATIONS1 (continued) Parameter A Grade 1, 2 B Grade1, 2 Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.35/5.25 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or V DD Normal Mode (Static) 2.5 2.5 mA typ V DD = 4.75 V to 5.25 V, SCLK On or Off 1.2 1.2 mA typ V DD = 2.35 V to 3.6 V, SCLK On or Off Normal Mode (Operational) 3 3 mA max V DD = 4.75 V to 5.25 V, f SAMPLE = 250 kSPS 1.4 1.4 mA max V DD = 2.35 V to 3.6 V, f SAMPLE = 250 kSPS Full Power-Down Mode 1 1 mA max Typically 50 nA Power Dissipation7 Normal Mode (Operational) 15 15 mW max V DD = 5 V, fSAMPLE = 250 kSPS 4.2 4.2 mW max V DD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 5 mW max V DD = 5 V 33 mW max V DD = 3 V NOTES 1Temperature range from –40 ∞C to +85∞C. 2Operational from V DD = 2.0 V, with input low voltage (V INL) 0.35 V max. 3See Terminology section. 4B Grade, maximum specs apply as typical figures when V DD = 4.75 V to 5.25 V. 5SC70 values guaranteed by characterization. 6Guaranteed by characterization. 7See Power vs. Throughput Rate section. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)

4 LEADING ZEROS

Figure 2. AD7920 Serial Interface Timing Diagram Figure 3. Serial Interface Timing Example Figure 1. Load Circuit for Digital Output Timing Timing Specifications table. 250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 ms. The AD7920 can also operate with slower clock frequencies.

REV. B–6– AD7910/AD7920 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7910/AD7920 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS 1 (TA = 25∞C, unless otherwise noted.) Operating Temperature Range Lead Temperature, Soldering NOTES

1 Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Temperature Linearity Package Model Range Error (LSB) 1 Option2 Branding AD7910AKS-500RL7 –40 ∞C to +85∞C ± 0.5 max KS-6 CVA AD7910AKS-REEL –40 ∞C to +85∞C ± 0.5 max KS-6 CVA AD7910AKS-REEL7 –40 ∞C to +85∞C ± 0.5 max KS-6 CVA AD7910ARM –40 ∞C to +85∞C ± 0.5 max RM-8 CVA AD7910ARM-REEL –40 ∞C to +85∞C ± 0.5 max RM-8 CVA AD7910ARM-REEL7 –40 ∞C to +85∞C ± 0.5 max RM-8 CVA AD7920AKS-500RL7 –40 ∞C to +85∞C ± 0.75 typ KS-6 CUA AD7920AKS-REEL –40 ∞C to +85∞C ± 0.75 typ KS-6 CUA AD7920AKS-REEL7 –40 ∞C to +85∞C ± 0.75 typ KS-6 CUA AD7920BKS –40 ∞C to +85∞C ± 1.5 max KS-6 CUB AD7920BKS-REEL –40 ∞C to +85∞C ± 1.5 max KS-6 CUB AD7920BKS-REEL7 –40 ∞C to +85∞C ± 1.5 max KS-6 CUB AD7920BRM –40 ∞C to +85∞C ± 1.5 max RM-8 CUB AD7920BRM-REEL –40 ∞C to +85∞C ± 1.5 max RM-8 CUB AD7920BRM-REEL7 –40 ∞C to +85∞C ± 1.5 max RM-8 CUB EVAL-AD7910CB3 Evaluation Board EVAL-AD7920CB3 Evaluation Board EVAL-CONTROL BRD24 NOTES 1Linearity error refers to integral nonlinearity. 2KS = SC70, RM = MSOP. 3This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration pu rposes. 4This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in t he CB designator. To order a complete evaluation kit, a particular ADC evaluation board must be ordered, e.g., EVAL-AD7920CB, the EVAL-CONTROL BRD2, and a 1 2 V ac transformer. See relevant evaluation board technical note for more information.

REV. B AD7910/AD7920 –7– PIN FUNCTION DESCRIPTIONS Mnemonic Function CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7910/ AD7920 and framing the serial data transfer. VDD Power Supply Input. The V DD range for the AD7910/AD7920 is from 2.35 V to 5.25 V. GND Analog Ground. Ground reference point for all circuitry on the AD7910/AD7920. All analog input signals should be referred to this GND voltage. VIN Analog Input. Single-ended analog input channel. The input range is 0 to V DD. SDATA Data Out. Logic output. The conversion result from the AD7910/AD7920 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7920 consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. The data stream from the AD7910 consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided MSB first. SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7910/AD7920 conversion process. NC No Connect PIN CONFIGURATIONS 6-Lead SC70 TOP VIEW (Not to Scale) VDD GND VIN CS SDA T A SCLK AD7910/ AD7920 8-Lead MSOP VDD SDA T A CS VIN GND SCLK NCNC TOP VIEW (Not to Scale) AD7910/ AD7920 NC = NO CONNECT

REV. B–8– AD7910/AD7920 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7920 and AD7910, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error from the ideal, i.e., GND + 1 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier r eturns to track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ± 0.5 LSB, after the end of conversion. See the Serial Interface section for more details. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to- Noise Distortion N () ( . . )+= + 60 2 1 76 dB Thus, for a 12-bit converter this is 74 dB, and for a 10-bit converter this is 62 dB. Total Unadjusted Error A comprehensive specification that includes gain error, linearity error, and offset error. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of har- monics to the fundamental. It is defined as: THD VVVVV V () l o gdB = + +++20 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spec- trum (up to fS/2 and excluding dc) to the rms value of the funda- mental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs whose har- monics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). The AD7910/AD7920 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the specification page). In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the funda- mentals, expressed in dB.

REV. B Typical Performance Characteristics–AD7910/AD7920 –9– TPC 1 and TPC 2 show a typical FFT plot for the AD7920 and AD7910, respectively, at a 250 kSPS sampling rate and a 100 kHz input frequency. TPC 3 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 250 kSPS with a SCLK frequency of 5 MHz for the AD7920. TPC 4 and TPC 5 show typical INL and DNL performance for the AD7920. FREQUENCY (kHz) –55 –115 0 12525 SNR (dB) 50 75 100 –15 –35 –75 –95

8192 POINT FFT

VDD = 2.7V fSAMPLE = 250kSPS fIN = 100kHz SINAD = 72.05dB THD = –82.87dB SFDR = –87.24dB TPC 1. AD7920 Dynamic Performance at 250 kSPS FREQUENCY (kHz) –45 –105 SNR (dB) –25 –65 –85 VDD = 2.35V fSAMPLE = 250kSPS fIN = 100kHz SINAD = 61.67dB THD = –79.59dB SFDR = –82.93dB 0 12525 50 75 100 TPC 2. AD7910 Dynamic Performance at 250 kSPS FREQUENCY (kHz) –72.0 10 1000 SINAD (dB) 100 –73.0 –73.5 VDD = 5.25V VDD = 2.35V VDD = 2.7VVDD = 4.75V VDD = 3.6V –72.5 –71.0 –71.5 TPC 3. AD7920 SINAD vs. Input Frequency at 250 kSPS CODE 1.0 0.4 –0.2 0 1024 INL ERROR (LSB) 512 0.8 0.6 0.2 –0.4 –0.6 –0.8 –1.0 1536 2048 2560 3072 3584 4096 VDD = 2.35V TEMP = 25/H11543C fSAMPLE = 250kSPS TPC 4. AD7920 INL Performance TPC 6 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of 3.6 V and sampling at a rate of 250 kSPS. See the Analog Input section. TPC 7 shows a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 250 kSPS with an SCLK frequency of 5 MHz.

is complete. The control logic generates the ADC output code. Figure 6 shows the ADC transfer function. Figure 5. ADC Conversion Phase The output coding of the AD7910/AD7920 is straight binary. Figure 6. Transfer Characteristic

0 V to V

it needs to supply to the AD7910/AD7920 is typically 1.2 mA. needs to supply a maximum of 1.4 mA to the AD7910/AD7920. Figure 7. REF193 as Power Supply ature under the same setup conditions.

frequency is applied to the ADC, the cycle time will be 3.2 /H9262s. QUIET, to initiate the conversion. dummy cycle required to place the track-and-hold into track. The power dissipation during normal mode is 15 mW (VDD = 5 V). and powering up), and the power dissipated during conversion. Finally, the conversion time is 16 /H11003 (1/fSCLK) = 3.2 /H9262s. it does not have any effect on the overall power dissipation value. between conversions with both 5 V and 3 V supplies. rates there is no power saving made by using the power-down mode. Figure 12. Power vs. Throughput Rate

of information from the AD7910/AD7920 during conversion. The CS signal initiates the data transfer and conversion process. at that point. The conversion is also initiated at this point. three-state on the 16th SCLK falling edge, as shown in Figure 14. out the last bit and it could be read in the 15th rising SCLK edge. leading zero and it could be read on the following rising edge. Figure 13. AD7920 Serial Interface Timing Diagram

4 LEADING ZEROSTHREE-ST A TE

2 TRAILING ZEROS

Figure 14. AD7910 Serial Interface Timing Diagram

trailing zeros to fill the 16-bit word. configured as outputs and the MSB will be shifted first. DSP563xx provides equidistant sampling. Figure 17. Interfacing to the DSP563xx facili tates the use of ground planes that can be easily separated. cated to ground planes while signals are placed on the solder side. capacitor for the MSOP and SC70 packages respectively.

REV. B AD7910/AD7920 –19– OUTLINE DIMENSIONS 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 0.22 0.08 0.46 0.36 0.26 8/H11543 4/H11543 0/H11543 0.30 0.15 1.00 0.90 0.70 SEATING PLANE

1.10 MAX

2.00 BSC

2.10 BSC

0.65 BSC

1.25 BSC

1.30 BSC

0.10 MAX

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203AB 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 0.80 0.60 0.40 8/H11543 0/H11543 4.90 BSC PIN 1 3.00 BSC SEATING PLANE 0.15 0.00 0.38 0.22 3.00 BSC COPLANARITY 0.10 0.23 0.08 COMPLIANT TO JEDEC STANDARDS MO-187AA

–20– REV. B C02976–0–3/04(B) AD7910/AD7920

Revision History

3/04 – Data Sheet changed from REV. A to REV. B 8/03 – Data Sheet changed from REV. 0 to REV. A