AD7911ARM-REEL7

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2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs AD7911/AD7921 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 ©2004–2011 Analog Devices, Inc. All rights reserved.

FEATURES

Fast throughput rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V Low power: 4 mW typ at 250 kSPS with 3 V supplies 13.5 mW typ at 250 kSPS with 5 V supplies Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 1 μA maximum 8-lead TSOT package 8-lead MSOP package

APPLICATIONS

Battery-powered systems: Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION The AD7911/AD79211 are 10-bit and 12-bit, high speed, low power, 2-channel successive approximation ADCs, respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates of up to 250 kSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 6 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The channel to be converted is selected through the DIN pin, and the mode of operation is controlled by CS. The serial data stream from the DOUT pin has a channel identifier bit, which provides information about the converted channel. 1 Protected by U.S. Patent Number 6,681,332. FUNCTIONAL BLOCK DIAGRAM 04350-0-001 T/H CONTROL LOGIC 10-/12-BIT SUCCESSIVE APPROXIMATION ADC GND VDD AD7911/AD7921 VIN0 VIN1 SCLK DOUT CS DIN MUX Figure 1. The AD7911/AD7921 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD, thereby allowing the widest dynamic input range to the ADC. The analog input range for the part, therefore, is 0 to VDD. The conversion rate is determined by the SCLK signal. PRODUCT HIGHLIGHTS 1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. 2. Low power consumption. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock; conversion time is reduced when the serial clock speed is increased. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Average power consumption is reduced when the power- down mode is used while not converting. Current consumption is 1 μA maximum and 50 nA typically when in power-down mode. 4. Reference derived from the power supply. 5. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.

Rev. A | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

5/11—Rev. 0 to Rev. A 4/04—Revision 0: Initial Version

Rev. A | Page 3 of 28 SPECIFICATIONS AD7911 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V , fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter A Grade1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave Signal-to- Noise and Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD)2 −71 dB max Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max Intermodulation Distortion (IMD)2 Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −83 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 −90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity2 ±0.5 LSB max Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error2 ±0.5 LSB max Offset Error Match2, 3 ±0.3 LSB max Gain Error2 ±0.5 LSB max Gain Error Match2, 3 ±0.3 LSB max Total Unadjusted Error (TUE)2 ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±0.3 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 (VDD) V min 2.35 V ≤ VDD ≤ 2.7 V 2 V min 2.7 V < VDD ≤ 5.25 V Input Low Voltage, VINL 0.3 V max VDD = 2.35 V 0.2 (VDD) V max 2.35 V < VDD ≤ 2.7 V 0.8 V max 2.7 V < VDD ≤ 5.25 V Input Current, IIN, SCLK Pin ±0.3 μA max VIN = 0 V or VDD Input Current, IIN, CS Pin ±0.3 μA max Input Current, IIN, DIN Pin ±0.3 μA max Input Capacitance, CIN 5 pF max LOGIC OUTPUTS Output High Voltage, VOH V DD − 0.2 V min ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V Output Low Voltage, VOL 0.2 V max ISINK = 200 μA Floating-State Leakage Current ±0.3 μA max Floating-State Output Capacitance3 5 pF max Output Coding Straight (natural) binary See notes at end of table.

Rev. A | Page 4 of 28 Parameter A Grade1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 2.8 μs max 14 SCLK cycles with SCLK at 5 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 250 kSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Full Power-Down Mode (Static) 1 μA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.38 mA typ VDD = 5 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS 0.2 mA typ VDD = 3 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 250 kSPS 6 mW max VDD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 μW max VDD = 5 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.

Rev. A | Page 5 of 28 AD7921 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V , fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter A Grade1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 100 kHz sine wave Signal-to-Noise and Distortion (SINAD)2 70 dB min 72 dB typ Signal-to-Noise Ratio (SNR)2 71 dB min 72.5 dB typ Total Harmonic Distortion (THD)2 −81 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −84 dB typ Intermodulation Distortion (IMD)2 Second-Order Terms −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Term −86 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 −90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±1.5 LSB max Differential Nonlinearity2 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits Offset Error2 ±1.5 LSB max ±0.5 LSB typ Offset Error Match2, 3 ±0.5 LSB max Gain Error2 ± 2 LSB max ±0.3 LSB typ Gain Error Match2, 3 ±1 LSB max Total Unadjusted Error (TUE)2 ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±0.3 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 (VDD) V min 2.35 V ≤ VDD ≤ 2.7 V 2 V min 2.7 V < VDD ≤ 5.25 V Input Low Voltage, VINL 0.3 V max VDD = 2.35 V 0.2 (VDD) V max 2.35 V < VDD ≤ 2.7 V 0.8 V max 2.7 V < VDD ≤ 5.25 V Input Current, IIN, SCLK Pin ±0.3 μA max VIN = 0 V or VDD Input Current, IIN, CS Pin ±0.3 μA max Input Current, IIN, DIN Pin ±0.3 μA max Input Capacitance, CIN3 5 pF max LOGIC OUTPUTS Output High Voltage, VOH V DD − 0.2 V min ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V Output Low Voltage, VOL 0.2 V max ISINK = 200 μA Floating-State Leakage Current ±0.3 μA max Floating-State Output Capacitance3 5 pF max Output Coding Straight (natural) binary See notes at end of table.

Rev. A | Page 6 of 28 Parameter A Grade1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 3.2 μs max 16 SCLK cycles with SCLK at 5 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 250 kSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Full Power-Down Mode (Static) 1 μA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.4 mA typ VDD = 5 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS 0.22 mA typ VDD = 3 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 250 kSPS 6 mW max VDD = 3 V, fSAMPLE = 250 kSPS Full Power-Down 5 μW max VDD = 5 V 3 μW max VDD = 3 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V . VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.

5 MHz max

1 Mark/space ratio for SCLK input is 40/60 to 60/40. 2 Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. time of the part and is independent of the bus loading. 6 See the Power-Up Time section. Figure 2. Load Circuit for Digital Output Timing Specifications Figure 3. Access Time after SCLK Falling Edge Figure 4. Hold Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State

Rev. A | Page 9 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to GND −0.3 V to +7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin except Supplies1 ±10 mA Operating Temperature Range Commercial (A Grade) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 207°C/W θJA Thermal Impedance 205.9°C/W θJC Thermal Impedance 43.74°C/W Lead Temperature Soldering Reflow (10 s to 30 s) 235 (0/+5)°C ESD 2 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 11 of 28 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7911/ AD7921, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00…000) to (00…001) from the ideal, that is, AGND + 1 LSB. Offset Error Match The difference in offset error between any two channels. Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal, that is, V REF − 1 LSB after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Tot a l Una dju ste d E r ror A comprehensive specification that includes gain error, linearity error, and offset error. Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal of 20 kHz to 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a 10 kHz signal. The figure is given worst case across both channels for the AD7911/AD7921. Track-and-Hold Acquisition Time The time required for the output of the track-and-hold amplifier to reach its final value within ±1 LSB after the end of conversion. The track-and-hold amplifier returns to track mode at the end of conversion. See the Serial Interface section for more details. Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by √2, and the rms value for the quantization noise is q/√12. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as dB 76 1 02 6. N . SNR+= Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit converter, SNR is 62 dB. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental, which is defined as 2 2 V V V V V V THD + + + + log 20 ) dB( where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specifica- tion is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Rev. A | Page 12 of 28 Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7911/AD7921 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third- order terms are specified separately. The calculation of the intermodulation distortion is as in the THD specification, where it is defined as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.

250 kSPS with a SCLK frequency of 5 MHz for the AD7921. 250 kSPS with an SCLK frequency of 5 MHz for the AD7921. 250 kSPS. See the Analog Input section. sampling at 250 kSPS with an SCLK frequency of 5 MHz. for different operating temperatures.

8192 POINT FFT

Figure 10. AD7921 Dynamic Performance at 250 kSPS Figure 11. AD7911 Dynamic Performance at 250 kSPS Figure 12. AD7921 SINAD vs. Input Frequency at 250 kSPS Figure 13. AD7921 SNR vs. Input Frequency at 250 kSPS

conversion and access the complete conversion result. to avoid accidental power-down due to glitches on the CS line. Figure 26. Normal Mode Operation

rates do not have a power saving in power-down mode. Figure 29. Power Consumption vs. Throughput Rate

equidistant sampling is implemented by the DSP . clocking out two trailing zeros to fill the 16-bit word. outputs, and the MSB is shifted first. Figure 34. Interfacing to the DSP563xx

Rev. A | Page 24 of 28 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7911/AD7921 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7911/ AD7921 is in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7911/AD7921. Avoid running digital lines under the device, because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7911/AD7921 to avoid noise coupling. The power supply lines to the AD7911/AD7921 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also very important. The analog supply should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the V DD and GND pins to a minimum with short track lengths connecting the respective pins.

Rev. A | Page 25 of 28 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40

0.65 BSC

0.40 0.25

1.10 MAX

3.20 3.00 2.80 COPLANARITY 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 PIN 1 IDENTIFIER 15° MAX0.95 0.85 0.75 0.15 0.05 10-07-2009-B Figure 35. 8-Lead Mini Small Outline Package [MSOP]

2.90 BSC

1.60 BSC

0.10 MAX

2.80 BSC

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 36. 8-Lead Thin Small Outline Transistor Package [TSOT]

Description

AD7911ARMZ −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARMZ-REEL −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARM-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911ARMZ-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 #C1J AD7911AUJZ-R2 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 #C1J AD7911AUJZ-REEL7 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 #C1J AD7921ARMZ −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921ARMZ-REEL −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921ARMZ-REEL7 −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 #C1K AD7921AUJZ-R2 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 #C1K AD7921AUJZ-REEL7 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 #C1K 1 Z = RoHS Compliant Part. 2 Linearity error here refers to integral nonlinearity.

Rev. A | Page 26 of 28 NOTES

Rev. A | Page 27 of 28 NOTES

Rev. A | Page 28 of 28 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04350–0–5/11(A)