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4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP Data Sheet AD7904/AD7914/AD7924 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2002–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Fast throughput rate: 1 MSPS Specified for AVDD of 2.7 V to 5.25 V Low power: 6 mW maximum at 1 MSPS with 3 V supplies 13.5 mW maximum at 1 MSPS with 5 V supplies 4 single-ended inputs with sequencer Wide input bandwidth AD7924, 70 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI/QSPI™/ MICROWIRE™/DSP compatible Shutdown mode: 0.5 µA maximum 16-lead TSSOP package Qualified for automotive applications FUNCTIONAL BLOCK DIAGRAM AGND SCLK DOUT DIN CS VDRIVE AVDD CONTROL LOGIC 8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC T/H REFIN VIN0 VIN3 VIN2 VIN1 I/P MUX AD7904/AD7914/AD7924 SEQUENCER 03087-001 Figure 1. GENERAL DESCRIPTION The AD7904/AD7914/AD7924 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 4-channel successive approxi- mation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily inter- face with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is initiated at this point. There are no pipeline delays associated with the part. The AD7904/AD7914/AD7924 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7904/AD7914/ AD7924 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum. Through the configuration of the control register, the analog input range for the part can be selected as 0 V to REF IN or 0 V to 2 × REFIN, with either straight binary or twos complement output coding. The AD7904/AD7914/AD7924 each feature four single- ended analog inputs with a channel sequencer to allow a pre- programmed selection of channels to be converted sequentially. The conversion time for the AD7904/AD7914/AD7924 is determined by the SCLK frequency, which is also used as the master clock to control the conversion. PRODUCT HIGHLIGHTS 1. High Throughput with Low Power Consumption. The AD7904/AD7914/AD7924 offer throughput rates up to 1 MSPS. At the maximum throughput rate with 3 V supplies, the AD7904/AD7914/AD7924 dissipate only 6 mW of power maximum. 2. Four Single-Ended Inputs with Channel Sequencer. A consecutive sequence of channels can be selected, through which the ADC will cycle and convert on. 3. Single-Supply Operation with VDRIVE Function. The AD7904/AD7914/AD7924 operate from a single 2.7 V to 5.25 V supply. The V DRIVE function allows the serial inter- face to connect directly to 3 V or 5 V processor systems, independent of VDD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced by increasing the serial clock speed. The parts also feature two shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 µA maximum when in full shutdown. 5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via the CS input and once-off conversion control.
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 2 of 32 TABLE OF CONTENTS
REVISION HISTORY
6/13—Rev. B to Rev. C Deleted Evaluating AD7904/AD7914/AD7924 Performance 7/11—Rev. A to Rev. B Changes to Signal to (Noise + Distortion) (SINAD) Parameter Changes to Signal to (Noise + Distortion) (SINAD) Parameter Changes to Signal to (Noise + Distortion) (SINAD) Parameter 2/09—Rev. 0 to Rev. A 11/02—Revision 0: Initial Version
Data Sheet AD7904/AD7914/AD7924 Rev. C | Page 3 of 32 SPECIFICATIONS AD7904 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V , REFIN = 2.5 V , fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal to (Noise + Distortion) (SINAD)2 49 dB min B models 48.5 dB min W models Signal-to-Noise Ratio (SNR) 49 dB min B models 48.5 dB min W models Total Harmonic Distortion (THD)2 −66 dB max Peak Harmonic or Spurious Noise (SFDR) −64 dB max Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 8 Bits Integral Nonlinearity (INL)2 ±0.2 LSB max Differential Nonlinearity (DNL)2 ±0.2 LSB max Guaranteed no missed codes to 8 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error2 ±0.5 LSB max Offset Error Match2 ±0.05 LSB max Gain Error2 ±0.2 LSB max Gain Error Match2 ±0.05 LSB max
0 V to 2 × REFIN Input Range
−REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error2 ±0.2 LSB max Positive Gain Error Match2 ±0.05 LSB max Zero Code Error2 ±0.5 LSB max Zero Code Error Match2 ±0.1 LSB max Negative Gain Error2 ±0.2 LSB max Negative Gain Error Match2 ±0.05 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF max
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 4 of 32 Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time2 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max VDRIVE 2.7/5.25 V min/V max IDD4 Digital inputs = 0 V or VDRIVE Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section.
Data Sheet AD7904/AD7914/AD7924 Rev. C | Page 5 of 32 AD7914 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V , REFIN = 2.5 V , fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal to (Noise + Distortion) (SINAD)2 61 dB min B models 60.5 dB min W models Signal-to-Noise Ratio (SNR) 61 dB min B models 60.5 dB min W models Total Harmonic Distortion (THD)2 −72 dB max Peak Harmonic or Spurious Noise (SFDR) −74 dB max Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity (INL)2 ±0.5 LSB max Differential Nonlinearity (DNL)2 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error2 ±2 LSB max Offset Error Match2 ±0.2 LSB max Gain Error2 ±0.5 LSB max Gain Error Match2 ±0.2 LSB max
0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos
Positive Gain Error2 ±0.5 LSB max Positive Gain Error Match2 ±0.2 LSB max Zero Code Error2 ±2 LSB max Zero Code Error Match2 ±0.2 LSB max Negative Gain Error2 ±0.5 LSB max Negative Gain Error Match2 ±0.2 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF max
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 6 of 32 Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time2 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max VDRIVE 2.7/5.25 V min/V max IDD4 Digital inputs = 0 V or VDRIVE Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section.
Data Sheet AD7904/AD7914/AD7924 Rev. C | Page 7 of 32 AD7924 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V , REFIN = 2.5 V , fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal to (Noise + Distortion) (SINAD)2 70 dB min @ 5 V, B models 69.5 dB min @ 5 V, W models 69 dB min @ 3 V, typically 69.5 dB Signal-to-Noise Ratio (SNR) 70 dB min B models 69.5 dB min W models Total Harmonic Distortion (THD)2 −77 dB max @ 5 V, typically −84 dB −73 dB max @ 3 V, typically −77 dB Peak Harmonic or Spurious Noise (SFDR) −78 dB max @ 5 V, typically −86 dB Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity (INL)2 ±1 LSB max Differential Nonlinearity (DNL)2 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits Offset Error2 ±8 LSB max Typically ±0.5 LSB Offset Error Match2 ±0.5 LSB max Gain Error2 ±1.5 LSB max Gain Error Match2 ±0.5 LSB max −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error2 ±1.5 LSB max Positive Gain Error Match2 ±0.5 LSB max Zero Code Error2 ±8 LSB max Typically ±0.8 LSB Zero Code Error Match2 ±0.5 LSB max Negative Gain Error2 ±1 LSB max Negative Gain Error Match2 ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V min Input Low Voltage, VINL 0.3 × VDRIVE V max Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF max
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 8 of 32 Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary CODING bit set to 1 Twos complement CODING bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time2 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS VDD 2.7/5.25 V min/V max VDRIVE 2.7/5.25 V min/V max IDD4 Digital inputs = 0 V or VDRIVE Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown Mode 960 μA typ fSAMPLE = 250 kSPS 0.5 μA max Static Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AVDD = 5 V, fSCLK = 20 MHz 6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V 1 Temperature range for B versions: −40°C to +85°C. 2 See the Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See the Power vs. Throughput Rate section.
AVDD = 2.7 V to 5.25 V , VDRIVE ≤ AVDD, REFIN = 2.5 V , TA = TMIN to TMAX, unless otherwise noted. 1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2). 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. time of the part and is independent of the bus loading. Figure 2. Load Circuit for Digital Output Timing Specifications
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 10 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating AVDD to AGND −0.3 V to +7 V VDRIVE to AGND −0.3 V to AVDD + 0.3 V Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to AGND −0.3 V to +7 V Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V REFIN to AGND −0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Automotive (W Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 150.4°C/W (TSSOP) θJC Thermal Impedance 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) 215°C Infrared (15 secs) 220°C ESD 1.5 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
Figure 3. Pin Configuration Table 6. Pin Function Descriptions used as the clock source for the AD7904/AD7914/AD7924 conversion process. this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). AD7904/AD7914/AD7924 and frames the serial data transfer. to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. voltage range for the external reference is 2.5 V ± 1% for specified performance. corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first. of the AD7904/AD7914/AD7924 operates.
4096 POINT FFT
Figure 4. AD7924 Dynamic Performance at 1 MSPS Figure 5. AD7924 SINAD vs. Analog Input Frequency for Various Supply Figure 6. AD7924 PSRR vs. Supply Ripple Frequency (No Decoupling) Figure 7. AD7924 THD vs. Analog Input Frequency for Various Supply Figure 8. AD7924 THD vs. Analog Input Frequency for Various Source Figure 9. AD7924 Typical INL
Figure 10. AD7924 Typical DNL
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 14 of 32 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error Offset error is the deviation of the first code transition (00 … 000 to 00 … 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match Offset error match is the difference in offset error between any two channels. Gain Error Gain error is the deviation of the last code transition (111 … 110 to 111 … 111) from the ideal, that is, REFIN − 1 LSB, after the offset error has been adjusted out. Gain Error Match Gain error match is the difference in gain error between any two channels. Zero Code Error Zero code error is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, that is, REFIN − 1 LSB. It applies when using the twos complement output coding option with the 2 × REFIN input range (−REFIN to +REFIN biased about the REFIN point). Zero Code Error Match Zero code error match is the difference in zero code error between any two channels. Positive Gain Error Positive gain error is the deviation of the last code transition (011 … 110 to 011 … 111) from the ideal, that is, +REFIN − 1 LSB, after the zero code error is adjusted out. It applies when using the twos complement output coding option with the 2 × REFIN input range (−REFIN to +REFIN biased about the REFIN point). Positive Gain Error Match Positive gain error match is the difference in positive gain error between any two channels. Negative Gain Error Negative gain error is the deviation of the first code transition (100 … 000 to 100 … 001) from the ideal, that is, −REFIN + 1 LSB, after the zero code error is adjusted out. It applies when using the twos complement output coding option with the 2 × REFIN input range (−REFIN to +REFIN biased about the REFIN point). Negative Gain Error Match Negative gain error match is the difference in negative gain error between any two channels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of cross- talk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all three nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all four channels for the AD7904/AD7914/AD7924. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 6). Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC AVDD supply of frequency fS. PSRR(dB) = 10 log(Pf/Pfs) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS coupled onto the ADC AVDD supply. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of a conversion. Signal to (Noise + Distortion) (SINAD) Ratio SINAD is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitiza- tion process: the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N +1.76) dB Thus, for a 12-bit converter, SINAD is 74 dB, for a 10-bit converter, it is 62 dB, and for an 8-bit converter, it is 50 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the funda- mental. For the AD7904/AD7914/AD7924, it is defined as log20(dB) V VVVVV THD ++++ where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
data stream. The bit functions are outlined in Table 8. Table 7. Channel Selection Table 8. Control Register Bit Functions loaded to the control register, which remains unchanged. 10 SEQ1 The SEQ1 bit is used in conjunction with the SEQ0 bit to control the use of the sequencer function (see Table 10). [9:8] DONTC Don’t care bits. channel to be converted on will be selected by the mux on the 14th SCLK falling edge. 3 SEQ0 The SEQ0 bit is used in conjunction with the SEQ1 bit to control the use of the sequencer function (see Table 10). conversion). For the 0 V to 2 × REFIN input range, VDD = 4.75 V to 5.25 V. the part will be straight binary (for the next conversion). Table 9. Power Mode Selection while in full shutdown. The part remains in full shutdown until these bits are changed. 0 0 Invalid Invalid selection. This configuration is not allowed.
SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL ADD1, ADD0 FOR CONVERSION. Figure 12. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
2.5 V (if the RANGE bit is set to 1) or 0 V to 5 V (if the RANGE
of 5 V , the serial interface is connected to a 3 V microprocessor.
- ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND.
Figure 19. Typical Connection Diagram configurations are shown in Table 7. sequence programmed by executing a conversion on Channel 0. sequencer returns to Channel 0 and restarts the sequence.
Data Sheet AD7904/AD7914/AD7924 Rev. C | Page 21 of 32 Digital Inputs The digital inputs applied to the AD7904/AD7914/AD7924 can go to 7 V and are not restricted by the AVDD + 0.3 V limit on the analog inputs. Because the SCLK, DIN, and CS inputs are not restricted by the AVDD + 0.3 V limit, power supply sequencing issues are avoided. If CS, DIN, or SCLK is applied before AVDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V is applied prior to AVDD. VDRIVE The AD7904/AD7914/AD7924 also include the VDRIVE feature. VDRIVE controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7904/AD7914/AD7924 are operated with a VDD o f 5 V, t h e VDRIVE pin can be powered from a 3 V supply. The AD7904/AD7914/AD7924 have better dynamic performance with a VDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure that VDRIVE does not exceed AVDD by more than 0.3 V (see the Absolute Maximum Ratings section). Reference An external reference source should be used to supply the 2.5 V reference to the AD7904/AD7914/AD7924. Errors in the refer- ence source result in gain errors in the AD7904/AD7914/ AD7924 transfer function and add to the specified full-scale errors of the part. A capacitor of at least 0.1 µF should be placed on the REFIN pin. Suitable reference sources for the AD7904/ AD7914/AD7924 include the AD780, REF193, and AD1582. If 2.5 V is applied to the REFIN pin, the analog input range can be either 0 V to 2.5 V or 0 V to 5 V , depending on the setting of the RANGE bit in the control register.
The AD7904/AD7914/AD7924 have three modes of operation. (see the Powering Up the AD7904/AD7914/AD7924 section). operation of the AD7904/AD7914/AD7924 in this mode.
- CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
Figure 20. Normal Mode Operation and the part remains in normal mode. to track mode on the 14th SCLK falling edge. time prior to the next conversion (effectively idling CS low). tQUIET, has elapsed by bringing CS low again. bits in the control register, PM1 and PM0, are changed. track mode on the 14th SCLK falling edge. the general diagram for this sequence. attempting a valid conversion. therefore, the WRITE bit should be set to 0 on the DIN line.
2 IDENTIFICATION
Figure 27. AD7904 Serial Interface Timing Diagram Figure 28. AD7914 Serial Interface Timing Diagram Figure 29. AD7924 Serial Interface Timing Diagram
integer value N, equidistant sampling is implemented by the DSP . serial interface) of the DSP563xx family of DSPs from Motorola. zation signal from the DSP563xx provide equidistant sampling. the ESSI so the SCK0 pin must be set as an output (SCKD = 1). *ADDITIONAL PINS REMOVED FOR CLARITY. Figure 32. Interfacing to the DSP563xx should be taken with regard to grounding and layout. established as close as possible to the AD7904/AD7914/AD7924. ground planes while signals are placed on the solder side. transient currents due to internal logic switching.
Figure 33. 16-Lead Thin Shrink Small Outline Package (TSSOP) 2 W = Qualified for Automotive Applications. 3 Linearity error refers to integral linearity error. ordering information and to obtain the specific Automotive Reliability reports for these models.
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 30 of 32 NOTES
Data Sheet AD7904/AD7914/AD7924 Rev. C | Page 31 of 32 NOTES
AD7904/AD7914/AD7924 Data Sheet Rev. C | Page 32 of 32 NOTES ©2002–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03087-0-6/13(C)