AD7902BRQZ-RL7

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Dual Pseudo Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP Data Sheet AD7902 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

16-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 7.0 mW at 1 MSPS (VDD1 and VDD2 only) 12.0 mW at 1 MSPS (total) 140 µW at 10 kSPS INL: ±1.0 LSB typical, ±2.5 LSB maximum SINAD: 91 dB at 1 kHz THD: −105 dB at 1 kHz Pseudo differential analog input range 0 V to VREF with VREF between 2.4 V to 5.1 V Allows use of any input range Easy to drive with the ADA4841-1/ADA4841-2 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial port interface (SPI) QSPI/MICROWIRE/DSP compatible 20-lead QSOP package Wide operating temperature range: −40°C to +125°C

APPLICATIONS

Automated test equipment (ATE) Data acquisition Medical instrumentation Redundant measurement Simultaneous sampling GENERAL DESCRIPTION The AD7902 is a dual 16-bit, successive approximation, analog- to-digital converter (ADC) that operates from a single power supply, VDDx, per ADC. It contains two low power, high speed, 16-bit sampling ADCs and a versatile serial port interface (SPI). On the CNVx rising edge, the AD7902 samples an analog input, IN+, in the range of 0 V to VREF with respect to a ground sense, IN−. The externally applied reference voltage of the REFx pins (VREF) can be set independently from the supply voltage pins, VDDx. The power of the device scales linearly with throughput. Using the SDIx inputs, the SPI-compatible serial interface can also daisy-chain multiple ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V , 2.5 V , 3 V , or 5 V logic, using the separate VIOx supplies. The AD7902 is available in a 20-lead QSOP package with operation specified from −40°C to +125°C. Table 1. MSOP 14-/16-/18-Bit PulSAR® ADCs

18 AD76911 AD76901 AD79821 ADA4941-1

16 AD7680 AD76851 AD76861 AD79801 ADA4941-1

14 AD7940 AD79421 AD79461

AD7902* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD7902 Evaluation Board DOCUMENTATION Application Notes
• AN-742: Frequency Domain Response of Switched- Capacitor ADCs
• AN-877: Interfacing to High Speed ADCs via SPI
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD7902: Dual Pseudo Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP Data Sheet Product Highlight
• [NO TITLE FOUND] Product Highlight
• Lowest-Power 16-Bit ADC Optimizes Portable Designs (eeProductCenter, 10/4/2006) User Guides
• UG-608: Evaluating the AD7902 Dual Pseudo Differential, 16-Bit, 1 MSPS PulSAR ADC TOOLS AND SIMULATIONS
• AD7902 IBIS Model REFERENCE MATERIALS Press
• Analog Devices Releases Two Dual A/D Converters with Lowest Power/Highest Linearity Combination Available
• Most Power Efficient Drivers For 12-, 14- And 16-bit A/D Converters Unveiled Product Selection Guide
• SAR ADC & Driver Quick-Match Guide Technical Articles
• MS-1779: Nine Often Overlooked ADC Specifications
• MS-2022: Seven Steps to Successful Analog-to-Digital Signal Conversion (Noise Calculation for Proper Signal Conditioning)
• MS-2124: Understanding AC Behaviors of High Speed ADCs
• MS-2210: Designing Power Supplies for High Speed ADC Tutorials
• MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design
• MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND" DESIGN RESOURCES
• AD7902 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD7902 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

8/15—Rev. A to Rev. B Changed ADA4841-x to ADA4841-1/ADA4841-2 .. Throughout 7/14—Rev. 0 to Rev. A 2/14—Revision 0: Initial Version

Rev. B | Page 3 of 28 SPECIFICATIONS VDD = 2.5 V , VIO = 2.3 V to 5.5 V , VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.1 Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT2 Voltage Range INx+ − INx− 0 VREF V Absolute Input Voltage INx+ −0.1 VREF + 0.1 V INx− −0.1 0 +0.1 V Analog Input CMRR fIN = 450 kHz 67 dB Leakage Current at 25°C Acquisition phase 200 nA ACCURACY No Missing Codes 16 Bits Differential Nonlinearity Error3 VREF = 5 V −1.0 ±0.5 +1.0 LSB VREF = 2.5 V ±0.8 LSB Integral Nonlinearity Error3 VREF = 5 V −2.5 ±1.0 +2.5 LSB VREF = 2.5 V ±0.9 LSB Transition Noise3 VREF = 5 V 0.75 LSB VREF = 2.5 V 1.2 LSB Gain Error4 TMIN to TMAX −0.08 ±0.012 +0.08 % FS Gain Error Temperature Drift 0.3 ppm/°C Gain Error Match4 TMIN to TMAX 0.016 0.08 % FS Zero Error4 TMIN to TMAX −1.25 ±0.25 +1.25 mV Zero Temperature Drift 0.19 ppm/°C Zero Error Match4 TMIN to TMAX 0.2 1.0 mV Power Supply Sensitivity3 VDD = 2.5 V ± 5% ±0.1 LSB THROUGHPUT Conversion Rate VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C, up to 125°C 0 1 MSPS Transient Response Full-scale step 290 ns AC ACCURACY5 Dynamic Range VREF = 5 V 92 dB VREF = 2.5 V 87 dB Oversampled Dynamic Range fOUT = 10 kSPS 111 dB Signal-to-Noise Ratio (SNR) fIN = 1 kHz, VREF = 5 V 89.5 91.5 dB fIN = 1 kHz, VREF = 2.5 V 84.5 86.5 dB Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz −105 dB Total Harmonic Distortion (THD) fIN = 1 kHz −105 dB Signal-to-Noise-and-Distortion Ratio (SINAD) fIN = 1 kHz, VREF = 5 V 89 91 dB fIN = 1 kHz, VREF = 2.5 V 84 86 dB Channel-to-Channel Isolation fIN = 10 kHz −112 dB 1 The voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. 2 For information regarding input impedance, see the Analog Inputs section. 4 See the Terminology section. These specifications include full temperature range variation, but they do not include the error contribution from the external reference. 5 All specifications in decibels (dB) are referred to a full-scale input FSR. Although these parameters are referred to full scale, they are tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Rev. B | Page 4 of 28 VDD = 2.5 V , VIO = 2.3 V to 5.5 V , TA = −40°C to +125°C, unless otherwise noted.1 Table 3. Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE Voltage Range 2.4 5.1 V Load Current 1 MSPS, VREF = 5 V, each ADC 330 µA SAMPLING DYNAMICS −3 dB Input Bandwidth 10 MHz Aperture Delay VDD = 2.5 V 2.0 ns Aperture Delay Match VDD = 2.5 V 2.0 ns DIGITAL INPUTS Logic Levels VIL VIO > 3 V −0.3 +0.3 × VIO V VIO ≤ 3 V −0.3 +0.1 × VVIO V VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format Straight binary Bits Pipeline Delay No delay, conversion results available immediately after conversion is complete

0 Samples

VOL ISINK = 500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VDDx 2.375 2.5 2.625 V VIOx Specified performance 2.3 5.5 V VIOx Range Full range 1.8 5.5 V IVDDx Each ADC 1.4 1.6 mA IVIOx Each ADC 0.2 0.45 mA Standby Current2, 3 VDD and VIO = 2.5 V, 25°C 0.35 µA Power Dissipation 10 kSPS throughput 140 µW 1 MSPS throughput 12.0 16 mW VDDx Only 1 MSPS throughput 7.0 mW REF Only 3.3 mW VIO Only 1.7 mW Energy per Conversion 7.0 nJ/sample TEMPERATURE RANGE4 Specified Performance TMIN to TMAX −40 +125 °C 1 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. 2 With all digital inputs forced to VIOx or to ground, as required. 3 During the acquisition phase. 4 Contact Analog Devices, Inc., for the extended temperature range.

Rev. B | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs INx+, INx− to GND1 −0.3 V to VREF + 0.3 V or ±10 mA Supply Voltage REFx, VIOx to GND −0.3 V to +6.0 V VDDx to GND −0.3 V to +3.0 V VDDx to VIOx +3 V to −6 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Lead Temperatures Vapor Phase (60 sec) 255°C Infrared (15 sec) 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1 See the Analog Inputs section for an explanation of INx+ and INx−.

Figure 4. Pin Configuration Table 6. Pin Function Descriptions decouple each pin closely to the GND pin with a 10 µF capacitor. 3, 8 IN1+, IN2+ AI Pseudo Differential Positive Analog Inputs. 4, 9 IN1−, IN2− AI Pseudo Differential Negative Analog Inputs. 5, 10 GND P Power Supply Ground. 13, 18 SCK2, SCK1 DI Serial Data Clock Inputs. When the device is selected, the conversion results are shifted out by these clocks. complete, the busy indicator feature is enabled. 15, 20 VIO2, VIO1 P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (2.5 V or 3 .3 V). 1 AI is analog input, DI is digital input, DO is digital output, and P is power.

Rev. B | Page 13 of 28 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 32). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The first transition should occur at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The zero error is the deviation of the actual transition from that point. Zero Error Match It is the difference in offsets, expressed in millivolts between the channels of a multichannel converter. It is computed with the following equation: Zero Matching = V ZEROMAX − VZEROMIN where: VZEROMAX is the most positive zero error. VZEROMIN is the most negative zero error. Zero error matching is usually expressed in millivolts with the full-scale input range stated in the product data sheet. Gain Error The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Gain Error Match It is the ratio of the maximum full scale to the minimum full scale of a multichannel ADC. It is expressed as a percentage of full scale using the following equation: %1002 ×  −= N MINMAX FSRFSRMatchingGain where: FSRMAX is the most positive gain error of the ADC. FSRMIN is the most negative gain error. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as follows: Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as follows: Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels (dB). It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels (dB). Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNVx input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

in buffer configuration; see Figure 35). that is commensurate with the AD7902. to verify the settling time prior to driver selection. Table 8. Recommended Driver Amplifiers pins, as explained in the Layout section. ADR433, ADR434, or ADR435 reference.

allows direct interface with any logic between 1.8 V and 5.5 V . range, as shown in Figure 36. Figure 36. PSRR vs. Frequency rates (of even a few hertz) and low battery-powered applications. Figure 37. Operating Currents per ADC vs. Sampling Rate flexibility in its serial interface modes. simultaneous sampling applications. together, chain mode is always selected. out the maximum conversion time prior to readback.

• In CS mode when CNVx or SDIx is low when the ADC conversion ends (see Figure 41 and Figure 45).
• In chain mode when SCKx is high during the CNVx rising edge (see Figure 49).

60 PSRR (dB)

0.001 OPERATING CURRENTS (mA)

separating the verification ADC from the system under control. opposite direction as expected. access to the leads for inspection. Figure 52. Typical Functional Safety Block Diagram

monotonicity of digital edges in the PCB layout. the planes underneath the AD7902. with wide, low impedance traces. See Figure 53 for an example of layout following these rules. the board from a PC via the EVAL-SDP-CB1Z. Figure 53. Example Layout of the AD7902 (Top Layer)

Figure 54. 20-Lead Shrink Small Outline Package [QSOP] REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Rev. B | Page 28 of 28 NOTES ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11756-0-8/15(B)