AD7810YRM

AD7810 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7810 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 2.7 V to 5.5 V, 2 ms, 10-Bit ADC in 8-Lead microSOIC/DIP FUNCTIONAL BLOCK DIAGRAM CLOCK OSC D OUT SCLK VREFAGNDVDD VIN+ VIN– CONVST SERIAL PORT CHARGE REDISTRIBUTION DAC CONTROL LOGIC AD7810 COMP VDD /3

FEATURES

10-Bit ADC with 2 ms Conversion Time Small Footprint 8-Lead microSOIC Package Specified Over a –40 8C to +105 8C Temperature Range Inherent Track-and-Hold Functionality Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V to 5.5 V Microcontroller-Compatible Serial Interface Optional Automatic Power-Down at End of Conversion Low Power Operation 270 mW at 10 kSPS Throughput Rate 2.7 mW at 100 kSPS Throughput Rate Analog Input Range: 0 V to V REF Reference Input Range: 0 V to V DD

APPLICATIONS

Low Power, Hand-Held Portable Applications that Require Analog-to-Digital Conversion with 10-Bit Accuracy; e.g., Battery Powered Test Equipment, Battery Powered Communications Systems GENERAL DESCRIPTION The AD7810 is a high speed, low power, 10-bit A/D con- verter that operates from a single 2.7 V to 5.5 V supply. The part contains a 2 ms successive approximation A/D converter, with inherent track/hold functionality, a pseudo differential input and a high speed serial interface that interfaces to most microcontrollers. The AD 7810 is fully specified over a tem- perature range of –40°C to +105°C. By using a technique that samples the state of the CONVST (convert start) signal at the end of a conversion, the AD7810 may be used in an automatic power-down mode. When used in this mode, the AD7810 automatically powers down at the end of a conversion and “wakes up” at the start of a new conversion. This feature significantly reduces the power consumption of the part at lower throughput rates. The AD7810 can also operate in a high speed mode where the part is not powered down between conversions. In this high speed mode of operation, the conver- sion time of the AD7810 is 2 ms. The maximum throughput rate is dependent on the speed of the serial interface of the micro- controller. The part is available in a small 8-lead, 0.3" wide, plastic dual- in-line package (mini-DIP); in an 8-lead, small outline IC (SOIC); and in an 8-lead microSOIC package. PRODUCT HIGHLIGHTS 1. Complete, 10-Bit ADC in 8-Lead Package The AD7810 is a 10-bit 2 ms ADC with inherent track/hold functionality and a high speed serial interface—all in an 8-lead microSOIC package. V REF may be connected to V DD to eliminate the need for an external reference. The result is a high speed, low power, space saving ADC solution. 2. Low Power, Single Supply Operation The AD7810 operates from a single +2.7 V to +5.5 V supply and typically consumes only 9 mW of power while convert- ing. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode, e.g., at a throughput rate of 10 kSPS the power consumption is only 270 mW. 3. Automatic Power-Down The automatic power-down mode, whereby the AD7810 powers down at the end of a conversion and “wakes up” before the next conversion, means the AD7810 is ideal for battery powered applications. See Power vs. Throughput Rate section. 4. Serial Interface An easy to use, fast serial interface allows connection to most popular microprocessors with no external circuitry.

–2– REV. A AD7810–SPECIFICATIONS Parameter Y Version Units Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 30 kHz, fSAMPLE = 350 kHz Signal to (Noise + Distortion) Ratio 1 58 dB min Total Harmonic Distortion 1 –64 dB max Peak Harmonic or Spurious Noise –64 dB max Intermodulation Distortion 2 fa = 48 kHz, fb = 48.5 kHz 2nd Order Terms –67 dB typ 3rd Order Terms –67 dB typ DC ACCURACY Resolution 10 Bits Relative Accuracy1 – 1L S B m a x Differential Nonlinearity (DNL) 1 – 1L S B m a x Offset Error1 – 2L S B m a x Gain Error1 – 2L S B m a x Minimum Resolution for Which No Missing Codes Are Guaranteed 10 Bits ANALOG INPUT Input Voltage Range 0 V min VREF V max Input Leakage Current 2 – 1 mA max Input Capacitance2 15 pF max REFERENCE INPUTS2 VREF Input Voltage Range 1.2 V min VDD V max Input Leakage Current – 3 mA max Input Capacitance 20 pF max LOGIC INPUTS2 VINH, Input High Voltage 2.0 V min VINL, Input Low Voltage 0.4 V max Input Current, IIN – 1 mA max Typically 10 nA, V IN = 0 V to VDD Input Capacitance, CIN 8 pF max LOGIC OUTPUTS Output High Voltage, V OH 2.4 V min I SOURCE = 200 mA Output Low Voltage, V OL 0.4 V max I SINK = 200 mA High Impedance Leakage Current – 10 mA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 2.3 ms max Track/Hold Acquisition Time 1 100 ns max See DC Acquisition Time Section POWER SUPPLY VDD 2.7–5.5 Volts For Specified Performance IDD 3.5 mA max Sampling at 350 kSPS and Logic Power Dissipation 17.5 mW max Inputs at V DD or 0 V. VDD = 5 V Power-Down Mode IDD 1 mA max V DD = 5 V; VDD = 3 V Power Dissipation 5 mW max Automatic Power Down 1 kSPS Throughput 27 mW max 10 kSPS Throughput 270 mW max 100 kSPS Throughput 2.7 mW max NOTES 1See Terminology section. 2Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. (GND = 0 V, VREF = +VDD. All specifications –40 8C to +1058C unless otherwise noted.)

1Sample tested to ensure compliance. of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. Figure 1. Load Circuit for Digital Output Timing Specifications conditions for extended periods may affect device reliability.

–5–REV. A TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 10-bit converter, this is 62␣ dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7810 it is defined as: THD dB() = 20 log 2 + V3 2 + V4 2 + V5 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms values of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa – nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the sec- ond order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7810 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of differ- ent significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified sepa- rately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1␣ LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (0000 . . . 000) Gain Error This is the deviation of the last code transition (1111 . . . 110) offset error has been adjusted out. Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within – 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the V IN+ input of the AD7810. It means that the user must wait for the duration of the track/hold acquisition time, after the end of conversion or after a step input change to V IN+, before starting another conversion to ensure that the part operates to specification.

ures 4 and 5 below show simplified schematics of the ADC. Figure 4. ADC Acquisition Phase the ADC output code. Figure 11 shows the ADC transfer function. Figure 5. ADC Conversion Phase mance. See Power vs. Throughput Rate section of the data sheet. Figure 6. Typical Connection Diagram forward biased and start conducting current into the substrate. capacitor and has a capacitance of 3.5 pF. Figure 7. Equivalent Analog Input Circuit

0.5 V, the offset could be applied to V

to VIN+. This has the effect of offsetting the input span by 0.5 V. voltage (VREF) is less than VDD – VOFFSET. Figure 8. Pseudo Differential Input Scheme

–11–REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-Lead Small Outline Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35)SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 8-Lead Micro Small Outline Package (RM-8) 8 5 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.122 (3.10) 0.114 (2.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33° 27° 0.120 (3.05) 0.112 (2.84) C2980a–0–8/98PRINTED IN U.S.A.