AD7804BRZ

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The AD7804/AD7808 are quad/octal 10-bit digital-to-analog converters, with serial load capabilities, while the AD7805/AD7809 are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3.3 V to +5 V (–10%) power supply and incorporates an on-chip reference. These DACs provide output signals in the form of V BIAS – VSWING. VSWING is derived internally from VBIAS. On-chip control registers include a system control register and channel control registers. The system control register has control over all DACs in the package. The channel control registers allow individual control of DACs. The complete transfer function of each individual DAC can be shifted around the V BIAS point using an on-chip Sub DAC. All DACs contain double buffered data inputs, which allow all analog outputs to be simultaneously updated using the asynchronous LDAC input. Control Features Channels Controlled Main DAC Sub DAC Hardware Clear All ˇˇ System Control Power Down1 All ˇˇ System Standby 2 All ˇˇ System Clear All ˇ Input Coding All ˇˇ Channel Control Channel Standby

2 Selective ˇˇ

Channel Clear Selective ˇ VBIAS Selective ˇˇ NOTES 1Power-down function powers down all internal circuitry including the reference. 2Standby functions power down all circuitry except for the reference. FUNCTIONAL BLOCK DIAGRAMS VOUT D VOUT C VOUT B VOUT A CHANNEL C CONTROL REG CHANNEL B CONTROL REG CHANNEL A CONTROL REG DAC REGISTER DAC D VBIAS DATA REGISTER AV DD DIVIDER CHANNEL D CONTROL REG REFIN REFOUT LDACCLR AV DD DV DD AGND DGND CLKIN FSIN AD7804/ AD7808 COMP SDIN POWER ON RESET DAC REGISTER DAC C VBIAS DATA REGISTER DAC REGISTER DAC B VBIAS DATA REGISTER MUX DAC REGISTER DAC A VBIAS DATA REGISTER SYSTEM CONTROL REG INPUT SHIFT REGISTER & CONTROL LOGIC MUX MUX 1.23V REF MUX VOUT G* VOUT E* VOUT H* VOUT F* PD ONLY AD7804 SHOWN FOR CLARITY SHOWS ADDITIONAL CHANNELS ON THE AD7808 PIN ON THE AD7808 ONLY VOUT D VOUT C VOUT B VOUT A CHANNEL C CONTROL REG CHANNEL B CONTROL REG CHANNEL A CONTROL REG DAC REGISTER DAC D VBIAS DATA REGISTER AV DD DIVIDER CHANNEL D CONTROL REG REFIN REFOUT LDACCLR AV DD DV DD AGND DGND WR CS AD7805/ AD7809 COMP POWER ON RESET MUX DAC REGISTER DAC C VBIAS DATA REGISTER DAC REGISTER DAC B VBIAS DATA REGISTER MUX DAC REGISTER DAC A VBIAS DATA REGISTER SYSTEM CONTROL REG INPUT REGISTER MUX MUX 1.23V REF CONTROL LOGIC MODE A0 A1 DB9 DB2 DB1 DB0 VOUT G* VOUT H* PD ONLY AD7805 SHOWN FOR CLARITY SHOWS ADDITIONAL CHANNELS ON THE AD7809 PIN ON THE AD7809 ONLY A2** VOUT E* VOUT F* Index on Page 26.REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a +3.3 V to +5 V Quad/Octal 10-Bit DACs

FEATURES

Four 10-Bit DACs in One Package Serial and Parallel Loading Facilities Available AD7804 Quad 10-Bit Serial Loading AD7805 Quad 10-Bit Parallel Loading AD7808 Octal 10-Bit Serial Loading AD7809 Octal 10-Bit Parallel Loading +3.3 V to +5 V Operation Power-Down Mode Power-On Reset Standby Mode (All DACs/Individual DACs) Low Power All CMOS Construction 10-Bit Resolution Double Buffered DAC Registers Dual External Reference Capability

APPLICATIONS

Instrumentation and Communication Systems Process Control and Voltage Setpoint Control Trim Potentiometer Replacement Automatic Calibration AD7804/AD7805/AD7808/AD7809 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998

AD7804/AD7805/AD7808/AD7809 REV. A–2– Parameter B Grade1 C Grade1 Units Comments STATIC PERFORMANCE MAIN DAC Resolution 10 10 Bits Relative Accuracy – 3 – 3 LSB max Gain Error – 3 – 3 % FSR max Bias Offset Error 2 –80/+40 –80/+40 mV max DAC Code = 0.5 Full Scale Zero-Scale Error 3 mV max DAC Code = 000H for Offset Binary Monotonicity 9 10 Bits and 200H for Twos Complement Coding Minimum Load Resistance 2 2 k W min SUB DAC Resolution 8 8 Bits Differential Nonlinearity – 0.125 – 0.125 LSB typ Refers to an LSB of the Main DAC – 0.5 – 0.5 LSB max OUTPUT CHARACTERISTICS Output Voltage Range 3 VBIAS – 15/16 · VBIAS VBIAS – 15/16 · VBIAS V Twos Complement Coding VBIAS/16 to 31/16 · VBIAS VBIAS/16 to 31/16 · VBIAS V Offset Binary Coding Voltage Output Settling Time to 10 Bits 4 4 ms max Typically 1.5 ms Slew Rate 2.5 2.5 V/ms typ Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around the Major Carry Digital Feedthrough 0.5 0.5 nV-s typ Digital Crosstalk 0.5 0.5 nV-s typ Analog Crosstalk – 0.2 – 0.2 LSB typ DC Output Impedance 2 2 W typ Power Supply Rejection Ratio 0.002 0.002 %/% typ DVDD – 10% DAC REFERENCE INPUTS REF IN Range 1.0 to V DD/2 1.0 to VDD/2 V min to V max REF IN Input Leakage – 1 – 1 mA max Typically – 1 nA DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V 2.4 2.4 V min Input High Voltage, VIH @ VDD = 3.3 V 2.1 2.1 V min Input Low Voltage, VIL @ VDD = 5 V 0.8 0.8 V max Input Low Voltage, VIL @ VDD = 3.3 V 0.6 0.6 V max Input Leakage Current – 10 mA max Input Capacitance 10 10 pF max Input Coding Twos Comp/Binary Twos Comp/Binary REFERENCE OUTPUT REF OUT Output Voltage 1.23 1.23 V nom REF OUT Error – 8 – 8 % max REF OUT Temperature Coefficient –100 –100 ppm/°C typ REF OUT Output Impedance 5 5 kW nom POWER REQUIREMENTS VDD (AVDD and DVDD) 3/5.5 3/5.5 V min to V max IDD (AIDD Plus DIDD) Excluding Load Currents Normal Mode 12 12 mA max V IH = VDD, VIL = DGND System Standby (SSTBY) Mode 250 250 mAV IH = VDD, VIL = DGND Power-Down (PD) Mode @ +25°C 0.8 0.8 mA max V IH = VDD, VIL = DGND TMIN–TMAX 1.5 1.5 mA max Power Dissipation Excluding Power Dissipated in Load Normal Mode 66 66 mW max System Standby (SSTBY) Mode 1.38 1.38 mW max Power-Down (PD) Mode @ +25°C 4.4 4.4 mW max TMIN–TMAX 8.25 8.25 mW max NOTES 1Temperature range is – 40°C to +85°C. 2Can be minimized using the Sub DAC. 3VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice. (AVDD and DVDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference = Internal Reference; C L = 100 pF; RL = 2 kV to GND. Sub DAC at Midscale. All specifications T MIN to TMAX unless otherwise noted.) AD7804/AD7805–SPECIFICATIONS ±VBIAS 16 / +40 ±VBIAS 16 / +40

Parameter B Grade1 Units Comments STATIC PERFORMANCE MAIN DAC Resolution 10 Bits Relative Accuracy – 4 LSB max Gain Error – 3 % FSR max Bias Offset Error 2 – 60 mV max DAC Code = 0.5 Full Scale Zero-Scale Error – 35 mV max DAC Code = 000H for Offset Binary Monotonicity 9 Bits and 200H for Twos Complement Minimum Load Resistance 2 k W min Coding SUB DAC Resolution 8 Bits Differential Nonlinearity – 0.125 LSB typ Refers to an LSB of the Main DAC – 0.5 LSB max OUTPUT CHARACTERISTICS Output Voltage Range 3 VBIAS – 15/16 · VBIAS V Twos Complement Coding VBIAS/16 to 31/16 · VBIAS V Offset Binary Coding Voltage Output Settling Time to 10 Bits 4 ms max Typically 1.5 ms Slew Rate 2.5 V/ms typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around the Major Carry Digital Feedthrough 0.5 nV-s typ Digital Crosstalk 0.5 nV-s typ Analog Crosstalk – 0.2 LSB typ DC Output Impedance 2 W typ Power Supply Rejection Ratio 0.002 %/% typ DVDD – 10% DAC REFERENCE INPUTS REF IN Range 1.0 to V DD/2 V min to V max REF IN Input Leakage – 1 mA max Typically – 1 nA DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V 2.4 V min Input High Voltage, VIH @ VDD = 3.3 V 2.1 V min Input Low Voltage, VIL @ VDD = 5 V 0.8 V max Input Low Voltage, VIL @ VDD = 3.3 V 0.6 V max Input Leakage Current – 10 mA max Input Capacitance 8 pF max Input Coding Twos Comp/Binary REFERENCE OUTPUT REF OUT Output Voltage 1.23 V nom REF OUT Error – 8 % max REF OUT Temperature Coefficient –100 ppm/°C typ REF OUT Output Impedance 5 kW nom POWER REQUIREMENTS VDD (AVDD and DVDD) 3/5.5 V min to V max IDD (AIDD Plus DIDD) Excluding Load Currents Normal Mode 18 mA max V IH = VDD, VIL = DGND System Standby (SSTBY) Mode 250 mA max V IH = VDD, VIL = DGND Power-Down (PD) Mode @ +25°C1 mA max V IH = VDD, VIL = DGND TMIN–TMAX 3 mA max Power Dissipation Excluding Power Dissipated in Load Normal Mode 99 mW max System Standby (SSTBY) Mode 1.38 mW max Power-Down (PD) Mode @ +25°C 5.5 mW max TMIN–TMAX 16.5 mW max NOTES 1Temperature range is – 40°C to +85°C. 2Can be minimized using the Sub DAC. 3VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice. (AVDD and DVDD = 3.3 V 6 10% to 5 V 6 10%; AGND = DGND = 0 V; Reference = Internal Reference; C L = 100 pF; RL = 2 kV to GND. Sub DAC at Midscale. All specifications T MIN to TMAX unless otherwise noted.) AD7808/AD7809–SPECIFICATIONS AD7804/AD7805/AD7808/AD7809 REV. A –3–

timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice. 1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 1. Timing Diagram for AD7804 and AD7808

timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice. 1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write

AD7804/AD7805/AD7808/AD7809 REV. A–6– Lead Temperature, Soldering Lead Temperature, Soldering Lead Temperature, Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. 3Transient currents of up to 100 mA will not cause SCR latch-up. ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted ) Operating Temperature Range AD7804/AD7805 Commercial Plastic AD7808/AD7809 Commercial Plastic Lead Temperature, Soldering Lead Temperature, Soldering ORDERING GUIDE Supply Temperature Relative Package Model Voltage Range Accuracy Package Descriptions Options AD7804BN 3.3 V to 5 V –40 °C to +85°C – 3 LSB 16-Lead Plastic DIP N-16 AD7804BR 3.3 V to 5 V –40 °C to +85°C – 3 LSB 16-Lead Small Outline IC R-16 AD7805BN 3.3 V to 5 V –40 °C to +85°C – 3 LSB 28-Lead Plastic DIP N-28 AD7805BR 3.3 V to 5 V –40 °C to +85°C – 3 LSB 28 Lead Small Outline IC R-28 AD7805BRS 3.3 V to 5 V –40 °C to +85°C – 3 LSB 28-Lead Shrink Small Outline Package RS-28 AD7805CR 3.3 V to 5 V –40 °C to +85°C – 3 LSB 28-Lead Small Outline IC R-28 AD7808BN 3.3 V to 5 V –40 °C to +85°C – 4 LSB 24-Lead Plastic DIP N-24 AD7808BR 3.3 V to 5 V –40 °C to +85°C – 4 LSB 24 Lead Small Outline IC R-24 AD7809BST 3.3 V to 5 V –40 °C to +85°C – 4 LSB 44-Lead Thin Plastic Quad Flatpack (TQFP) S U-44 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

AD7804/AD7805/AD7808/AD7809 –7–REV. A AD7804/AD7808 PIN FUNCTION DESCRIPTION AD7804 AD7808 Pin No. Pin No. Mnemonic Description 1 1, 6 AGND Ground reference point for analog circuitry. 2, 3 2, 3 V OUTB, VOUTA Analog output voltage from the DACs. 4 4 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V.

5 PD Active low input used to put the part into low power mode reducing current consumption

to 1 mA. 7, 8 V OUTF, VOUTE Analog output voltages from the DACs. 59 FSIN Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register and data is transferred on the falling edges of CLKIN. 61 0 LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the data registers. If LDAC is tied permanently low, or is low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic update will take place. 7 11 SDIN Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift register on the falling edge of CLKIN. 8 12 DGND Ground reference point for digital circuitry. 91 3 D V DD Digital Power Supply. 10 14 CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Duty Cycle should be between 40% and 60%. 11 15 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to VBIAS or to VBIAS/16 volts. All Sub DACs are also cleared and thus the transfer function of the Main DAC will remain centered around the V BIAS point. 16 NC No Connect. This pin should be left open circuit. 17, 18 V OUTH, VOUTG Analog output voltages from the DACs. 12 20 REFIN This is an external reference input for the DACs. When this reference is selected for a DAC in the control register, the analog output from the selected DAC swings around this point. 13 21 COMP Compensation Pin. This pin provides an output from the internal V DD/2 divider and is provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors to both AV DD and AGND. This pin can be overdriven with an external reference, thus giving the facility for two external references on the part. 14, 15 22, 23 V OUTD, VOUTC Analog output voltage from the DACs. 16 19, 24 AV DD Analog Power Supply. +3.3 V to +5 V. AD7804 PIN CONFIGURATION TOP VIEW (Not to Scale) AGND VOUT B VOUT A REFOUT FSIN LDAC SDIN DGND AV DD VOUT C VOUT D COMP REFIN CLR CLKIN DV DD AD7804 AD7808 PIN CONFIGURATION TOP VIEW (Not to Scale) AD7808 NC = NO CONNECT DGND SDIN LDAC FSIN VOUT E AGND VOUT B VOUT A REFOUT VOUT F AGND PD DV DD CLKIN CLR NC VOUT H AV DD VOUT C VOUT D COMP VOUT G AV DD REFIN

AD7804/AD7805/AD7808/AD7809 REV. A–8– AD7805/AD7809 PIN FUNCTION DESCRIPTIONS AD7805 AD7809 Pin No. Pin No. Mnemonic Description 1, 11, 13, NC No Connect. These pins should be left open circuit. 20, 33 1 2, 5, 39, 40 AGND Ground reference point for analog circuitry. 2, 3 41, 42 V OUTB, VOUTA Analog output voltages from the DACs. 4 43 REFOUT Reference Output. This is a bandgap reference and is typically 1.23 V. 5–10, 3, 4, 6, 7, 9, DB9–DB2 Data Inputs. DB9 to DB2 are the 8 MSBs of the data word. 12, 13 10, 15, 23 19, 20 24, 26 DB1, DB0 DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but have other functions when BYTE loading structure is used. 8, 12 V OUTF, VOUTE Analog output voltages from the DACs. 11 14 LDAC LDAC Input. When this digital input is taken low, all DAC registers are simultaneously updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is low during the rising edge of WR similar to data inputs, an automatic update will take place. 14 16 DGND Ground reference point for digital circuitry. 15 17 DVDD Digital Power Supply. 16 18 WR Write Input WR is an active low logic input which is used in conjunction with CS and the address pins to write data to the relevant registers. 17 21 CS Chip Select. Active low logic input. 18 19 CLR Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are cleared either to VBIAS or to VBIAS/16 volts. All Sub DACs are also cleared and thus the transfer function of the MAIN DAC will remain centered around the V BIAS point. 22, 25 V OUTH, VOUTG Analog output voltages from the DACs. 21, 22 27, 29, 30 A2, A1, A0 DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to determine which DAC channel control register or DAC data register is loaded from the input register. These address bits are don’t cares when writing to the system control register. 23 31 MODE Logic Input. Logic high enables writing to the DAC data registers, a logic low enables writing to the control registers. 24 32 REFIN This is an external reference input for the DAC. When this reference is selected for the DAC in the control register, the analog output from the selected DAC swings around this point. 25 34 COMP Compensation Pin. This pin provides an output from the internal V DD/2 divider and is provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors to both AVDD and AGND. This pin can be overdriven with an external reference, thus giving the facility for two external references on the part. 26, 27 35, 36 V OUTD, VOUTC Analog output voltages from the DACs. 28 28, 37, 38 AV DD Analog Power Supply.

44 PD Active low input used to put the part into low power mode reducing current consump-

tion to 1 mA. AD7805 PIN CONFIGURATION TOP VIEW (Not to Scale) AD7805 DGND DB2 DB3 LDAC DB4 DB5 DB6 AGND VOUT B VOUT A REFOUT DB7 DB8 DB9 DV DD WR CS CLR DB1 DB0 AV DD VOUT C VOUT D COMP MODE REFIN AD7809 PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) NC = NO CONNECT NC REFIN MODE AV DD DB0 V OUT G DB1 DB2 NC AGND DB9 DB8 AGND DB7 DB6 V OUT F DB5 DB4 NC PD REFOUT VOUT A VOUT B AGND AGND AV DD VOUT E NC LDAC DB3 DV DD WR CLR NC CS VOUT H DGND AV DD VOUT C VOUT D COMP AD7809

tion in slope of the DAC transfer characteristic from ideal. the data bus, i.e., from all 0s to all 1s and vice versa. of one converter due to a digital code change to another DAC. diagram is shown in Figure 1. each individual DAC. Table I shows how to access these registers. 0 0 Write enable to system control register. 0 1 Write enable to channel control register. 1 X Write enable to DAC data registers. DAC structure is shown for clarity. Figure 3. AD7804/AD7808 Internal Registers

AD7804/AD7805/AD7808/AD7809 –11–REV. A VBIAS can be the internal bandgap reference, the internal V DD/2 reference or the external REFIN as determined by MX1 and MX0 in the channel control register. A second external refer- ence can be used if required by overdriving the V DD/2 reference which appears at the COMP pin. System Standby (SSTBY) This bit allows all the DACs in the package to be put into low power mode simultaneously but the reference is not affected. Writing a one to the SSTBY bit in the system control register puts all DACs into standby mode. On writing a one to this bit all linear circuitry is switched off and the DAC outputs are connected through a high impedance to ground. The DACs come out of standby mode when a 0 is written to the SSTBY bit. System Clear Function (SCLR) This function allows the user to clear the contents of all data and DAC registers in software. Writing a one to the SCLR bit in the control register clears the DAC’s outputs. A zero in this bit position puts the DAC in normal operating mode. The out- put of the Main DACs are cleared to one of two voltages de- pending on the input coding used. If twos complement coding is selected, then issuing a software clear will reset the output of the Main DAC to midscale (V BIAS). If offset binary coding is selected, the Main DAC output will be reset to V BIAS /16 follow- ing the execution of a software clear. This system clear function does not affect the Sub DAC; the Sub DAC data register retains its value during a system software clear (SCLR). AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0, MD0 = 1) This register allows the user to have control over individual DACs in the package. The control bits in this register include the address bits for the selected DAC, standby ( STBY), indi- vidual DAC clear (CLR) and multiplexer output selection (MX1 and MX0). The function of these bits follows. DAC Selection (A2, A1, A0) Bits A2, A1 and A0 in the input registers are used to address a specific DAC. Table IIa shows the selection table for the DACs of the AD7804. Table IIb shows the selection table for the DACs of the AD7808. Table IIa. DAC Selection Table for the AD7804 A2 A1 A0 Function X 0 0 DAC A Selected X 0 1 DAC B Selected X 1 0 DAC C Selected X 1 1 DAC D Selected Table IIb. DAC Selection Table for the AD7808 A2 A1 A0 Function 0 0 0 DAC A Selected 0 0 1 DAC B Selected 0 1 0 DAC C Selected 0 1 1 DAC D Selected 1 0 0 DAC E Selected 1 0 1 DAC F Selected 1 1 0 DAC G Selected 1 1 1 DAC H Selected Standby (STBY) This bit allows the selected DAC in the package to be put into low power mode. Writing a zero to the STBY bit in the channel control register puts the selected DAC into standby mode. On writing a zero to this bit all linear circuitry is switched off and the DAC output is connected through a high impedance to ground. The DAC is returned to normal operation by writing a one to the STBY bit. Software Clear Function (CLR) This function allows the user to clear the contents of the se- lected DAC’s data in software. Writing a one to the CLR bit in the control register clears the DAC’s output. A zero in the CLR bit position puts the DAC in normal operating mode. This software CLR operation clears only the Main DAC, the con- tents of the Sub DAC is unaffected by a CLR operation. The output of the Main DAC can be cleared to one of two places depending on the input coding used. An LDAC pulse is re- quired to activate the channel clear function and must be ap- plied after the bit in the channel control register is set or reset. If twos complement coding is selected, then issuing a software clear will reset the output of the Main DAC to midscale (V BIAS). If offset binary coding is selected, the Main DAC output will be reset to VBIAS/16 following the execution of a software clear. Multiplexer Selection (MX1, MX0) These two bits are used to select the reference input for the selected DAC. Table III shows the options available. Table III. Multiplexer Output Selection MX1 MX0 V BIAS 00V DD/2 0 1 INTERNAL V REF 1 0 REFIN 1 1 Undetermined AD7804/AD7808 SUB DAC DATA REGISTER Figure 7 shows the loading sequence for writing to the data registers of the DACs. DB15 determines whether writing is to the Main or Sub DAC’s data register. A one in this position selects the addressed Sub DAC’s data register. The Sub DAC is 8 bits wide and thus DB1 and DB0 of the 16-bit input word are don’t cares when writing to the Sub DAC. This Sub DAC al- lows the complete transfer function of each individual DAC to be offset around the V BIAS point. This is achieved by either adding or subtracting to the output of the Main DAC. This Sub DAC has a span of – VBIAS/32 with 1/8-bit resolution. The coding scheme for the Sub DAC is the same as that for the Main DAC. With offset binary coding the transfer function for the Sub DAC is VBIAS 16 · (NB ±128) 256 where NB is the digital code written to the Sub DAC and varies from 0 to 255. With twos complement coding the transfer function for the Sub DAC is VBIAS 16 · NB 256() where NB is the digital code written to the Sub DAC and varies from –128 to 127. VBIAS can be either the internal bandgap reference, the internal V DD/2 reference or the external REFIN as

AD7804/AD7805/AD7808/AD7809 REV. A–14– Table IVb. AD7809 DAC Data/Control Register Selection Table MODE A2 A1 A0 Function Selected 0 0 0 0 DAC A Control Register 0 0 0 1 DAC B Control Register 0 0 1 0 DAC C Control Register 0 0 1 1 DAC D Control Register 0 1 0 0 DAC E Control Register 0 1 0 1 DAC F Control Register 0 1 1 0 DAC G Control Register 0 1 1 1 DAC H Control Register 1 0 0 0 DAC A Data Register 1 0 0 1 DAC B Data Register 1 0 1 0 DAC C Data Register 1 0 1 1 DAC D Data Register 1 1 0 0 DAC E Data Register 1 1 0 1 DAC F Data Register 1 1 1 0 DAC G Data Register 1 1 1 1 DAC H Data Register AD7805/AD7809 SYSTEM OR CHANNEL CONTROL REGISTER SELECTION MD0 0 This enables writing to the system control register. The contents of this are shown in Figure 12. Mode must be low to access this control register. 1 This enables writing to the channel control register. The contents of this are shown in Figure 13. Mode must also be low to access this control register. AD7805/AD7809 SYSTEM CONTROL REGISTER The bits in this register allow control over all DACs in the pack- age. The control bits include data format ( 10/8), power down (PD), DAC input coding select (BIN/ COMP), system standby (SSTBY) and a system clear (SCLR). The function of these bits is as follows: Data Format 0 10-bit parallel loading structure. 1 Byte loading structure . (8+2 loading). Input Coding BIN/COMP 0 Twos complement coding. 1 Offset Binary Coding. Power Down PD 0 Complete power-down of device. 1 Normal operation (default on power-up). System Standby SSTBY 0 Normal operation.

1 All DACs in the package put in standby mode (default

on power-up). System Clear SCLR 0 Normal operation.

1 All DACs in the package are cleared to a known state

depending on the coding scheme selected. The SCLR bit clears the Main DACs only; the Sub DACs are unaf- fected by the system clear function. The main DAC is cleared to different levels depending on the coding scheme. With offset binary coding the Main DAC output is cleared to the bottom of the transfer function V BIAS/16. With twos complement coding the Main DAC output is cleared to midscale V BIAS. The channel output will be the sum of the Main DAC and Sub DAC contributions. AD7805/AD7809 CHANNEL CONTROL REGISTER This register allows the user to have control over individual DACs in the package. The control bits in this register include multiplexer output selection (MX1 and MX0), Main or Sub DAC selection (MAIN/SUB), standby (STBY) and individual DAC clear (CLR). The function of these bits is as follows. Multiplexer Selection (MX1, MX0) Table V shows the V BIAS selection using MX1 and MX0 bits in the channel control register. Table V. V BIAS Selection Table MX1 MX0 V BIAS

00 V DD/2 (Default on Power-Up)

Main DAC or Sub DAC Selection MAIN/SUB

0 Writing a 0 to this bit means that the data in the next

data register write is transferred to the selected Main DAC.

1 Writing a 1 to this bit means that the data in the next

data register write is transferred to the selected Sub DAC. This applies to the 10-bit parallel load feature. In byte load mode, (Figure 15) DB0 selects the Main or Sub DAC data registers. Standby STBY

0 Places the selected DAC and its associated linear cir-

cuitry in Standby Mode. 1 Normal operation (default on power-up). Clear CLR 0 Normal operation.

1 Clears the output of the selected Main DAC to one

of two conditions depending on the input coding se- lected. With offset binary coding the Main DAC out- put is cleared to the bottom of the transfer function, V BIAS/16 and with twos complement coding the Main DAC output is cleared to midscale V BIAS. The Sub DAC is unaffected by a clear operation. An LDAC signal has to be applied to the DAC for a channel clear to be implemented.

and power dissipation from the package is at its minimum. Figure 21. Implementation of Power-Down and Standby not switched off when any of the standby functions are invoked. functions are implemented for a single DAC in the package. edge of WR, an automatic or synchronous update will take place. to that of the data inputs to operate in the synchronous mode. WR before the LDAC can be activated. of VBIAS – VSWING where VSWING is 15/16 of V BIAS. is for offset binary coding.

0000000000 V BIAS

16 VBIAS

Figure 22. Main DAC Output Voltage vs. DAC Input Codes

1000000000 V BIAS

0000000000 VBIAS/16

Figure 25. Main DAC Output Voltage vs. DAC Input Codes code. NA ranges from 0 to 1023. code. NB ranges from 0 to 255. log output variations available from the Sub DAC. MODE = 0, address inputs (A2, A1, A0) are don’t cares. MODE = 0, address inputs (A2, A1, A0) select desired channel. MODE = 1, address inputs (A2, A1, A0) select desired channel. MODE = 0, address inputs (A2, A1, A0) select desired channel. MODE = 1, address inputs (A2, A1, A0) select desired channel.

11111111 V BIAS/16 · 127/256

11111110 V BIAS/16 · 126/256

10000001 V BIAS/16 · 1/256

Figure 26. Sub DAC Output Voltage vs. DAC Input Codes Figure 27 shows a typical configuration for the AD7804/AD7808. show the contents of the registers on the AD7804/AD7808. Figure 27. Typical Configuration for AD7804/AD7808 coding and normal operation. A and writes full scale to the Main DAC. from the Main DAC and the Sub DAC.

Figure 28. Pictorial View of Transfer Function for Any DAC Channel while simultaneously minimizing the inductance of this loop. to a minimum thus reducing the possibility of power supply spikes. with analog ground from the digital pins located next to it. and AGND has very fast settling time, typically less than 500 ns.

AD7804/AD7805/AD7808/AD7809 REV. A–24– Opto-Isolated Interface for Process Control Applications The AD7804/AD7808 has a versatile serial three-wire serial interface making it ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD7804/AD7808 from the controller. This can easily be achieved by using opto-isolators which will provide isolation in excess of 3 kV. The serial loading structure of the AD7804/ AD7808 makes it ideally suited for use in opto-isolated appli- cations. Figure 41 shows an opto-isolated interface to the AD7804/AD7808 where SDIN, CLKIN and FSIN are driven from optocouplers. LDAC is hardwired low to reduce the number of interface lines and this ensures that each DAC is updated follow- ing the sixteenth serial clock of a write cycle. AD7804/ AD7808 AV DD VDD 1 VOUT A VOUT B VOUT C VOUT D AGNDDGND LDAC CLR CLKIN DV DD REFIN 0.1mF10mF REFOUT +5V REGULATOR CLKIN VDD 10kV FSINFSIN SDINDATA POWER

1 TO 10nFVDD

Figure 41. AD7804/AD7808 Opto-Isolated Interface system decoding multiple AD7808s in a multichannel system. Figure 42. Decoding Multiple AD7808s Using the FSIN Pin Figure 43. Digitally Programmable Window Detector

Figure 45. Two Externally Applied References Figure 44. Low Cost, Two-Channel Mixer

5 V V

required to provide the full 100 dB of attenuation.

AD7804/AD7805/AD7808/AD7809 REV. A–26– PAGE INDEX (AD7804/AD7808 SERIAL INTERFACE PART) Topic Page No. Timing Information Terminology Transfer Functions Microprocessor Interfacing (AD7805/AD7809 PARALLEL INTERFACE PART) Topic Page No. Timing Information Terminology Transfer Functions Microprocessor Interfacing

AD7804/AD7805/AD7808/AD7809 –27–REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-28) PIN 1 0.580 (14.73) 0.485 (12.32) 1 14 1528 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.250 (6.35) MAX 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) MAX 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 1.565 (39.70) 1.380 (35.10) SOIC (R-28) PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 28 15 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25) x 45° 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10) SSOP (RS-28) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 0°0.0256 (0.65) BSC 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) PIN 1 14 1 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) 0.015 (0.38) 0.010 (0.25) Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) SOIC (R-16) 16 9 0.4133 (10.50) 0.3977 (10.00) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45°

AD7804/AD7805/AD7808/AD7809 REV. A–28– C2107A–1–12/98PRINTED IN U.S.A. Plastic DIP (N-24) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.203) 0.195 (4.95) 0.115 (2.93) PIN 1 0.280 (7.11) 0.240 (6.10) 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.130 (3.30) MIN 1.275 (32.30) (0.38) MIN 0.160 (4.06) 0.115 (2.92) SOIC (R-24) 24 13 121 0.614 (15.6) 0.598 (15.2) 0.299 (7.6) 0.291 (7.4)PIN 1 0.419 (10.65) 0.394 (10.00) SEATING PLANE 0.012 (0.3) 0.004 (0.1) 0.019 (0.49) 0.014 (0.35) 0.104 (2.65) 0.093 (2.35) 0.0500 (1.27) BSC 08 0.0500 (1.27) 0.0157 (0.40) 0.03 (0.75) 0.01 (0.25) 0.013 (0.32) 0.009 (0.25) TQFP (SU-44) TOP VIEW (PINS DOWN) 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) BSC 0.394 (10.0) SQ 0.472 (12.00) SQ 0.04134 (1.05) 0.0374 (0.95) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.047 (1.20) MAX 0.030 (0.75) 0.018 (0.45) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).