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REV. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. a Signal Conditioning ADC AD7710

FEATURES

24 Bits, No Missing Codes

/H115500.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 1 to 128 Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single- or Dual-Supply Operation Low Power (25 mW Typ) with Power-Down Mode (7 mW Typ)

APPLICATIONS

The AD7710 is a complete analog front end for low frequency measurement applications. The device accepts low level signals directly from a strain gage or transducer and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register, allowing adjustment of the filter cutoff and settling time. The part features two differential analog inputs and a differen- tial reference input. Typically, one of the channels will be used as the main channel with the second channel used as an auxil- iary input to measure a second voltage periodically. It can be operated from a single supply (by tying the V SS pin to AGND), provided that the input signals on the analog inputs are more positive than –30 mV. By taking the V SS pin negative, the part can convert signals down to –V REF on its inputs. The AD7710 thus performs all signal conditioning and conversion for a single- or dual-channel system. The AD7710 is ideal for use in smart, microcontroller based systems. Input channel selection, gain settings, and signal polar- ity can be configured in software using the bidirectional serial port. The AD7710 contains self-calibration, system calibration, and background calibration options, and also allows the user to read and write the on-chip calibration registers. CMOS construction ensures low power dissipation, and a soft- ware programmable power-down mode reduces the standby power consumption to only 7 mW typical. The part is available in a 24-lead, 0.3 inch-wide, plastic and hermetic dual-in-line package (DIP) as well as a 24-lead small outline (SOIC) package. PRODUCT HIGHLIGHTS 1. The programmable gain front end allows the AD7710 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. 2. The AD7710 is ideal for microcontroller or DSP processor applications with an on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity, and calibration modes. 3. The AD7710 allows the user to read and write the on-chip calibration registers. This means that the microcontroller has much greater control over the calibration procedure. 4. No missing codes ensures true, usable, 23-bit dynamic range coupled with excellent ± 0.0015% accuracy. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. CLOCK GENERATION SERIAL INTERFACE CONTROL REGISTER OUTPUT REGISTER CHARGE-BALANCING A/D CONVERTER DIGITAL FILTER AD7710 M U X PGA AGND DGND MODE SDATA SCLK A0 MCLK OUT MCLK IN AIN1(+) AIN1(–) REF IN (–) REF IN (+) SYNC 4.5/H9262A A = 1 – 128 DRDYTFSRFS REF OUT 2.5V REFERENCE AVDD AVDD 20/H9262A AIN2(+) AIN2(–) IOUT VSS VBIASAVDD DVDD AUTO-ZEROED /H9018-/H9004 MODULATOR

REV. G–2– Parameter A, S Versions 1 Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz

22 Bits min For Filter Notch = 100 Hz

18 Bits min For Filter Notch = 250 Hz

15 Bits min For Filter Notch = 500 Hz

12 Bits min For Filter Notch = 1 kHz

Output Noise Tables I and II Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity @ +25 °C ± 0.0015 % of FSR max Filter Notches ≤ 60 Hz T MIN to TMAX ± 0.003 % of FSR max Typically ± 0.0003% Positive Full-Scale Error 2, 3 See Note 4 Excluding Reference Full-Scale Drift 5 1 µV/°C typ Excluding Reference. For Gains of 1, 2 0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 Unipolar Offset Error 2 See Note 4 Unipolar Offset Drift 5 0.5 µV/°C typ For Gains of 1, 2 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128 Bipolar Zero Error 2 See Note 4 Bipolar Zero Drift 5 0.5 µV/°C typ For Gains of 1, 2 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128 Gain Drift 2 ppm/ °C typ Bipolar Negative Full-Scale Error 2 @ 25°C ± 0.003 % of FSR max Excluding Reference TMIN to TMAX ± 0.006 % of FSR max Typically ± 0.0006% Bipolar Negative Full-Scale Drift 5 1 µV/°C typ Excluding Reference. For Gains of 1, 2 0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR) 100 dB min At DC and AV DD = 5 V 90 dB min At DC and AV DD = 10 V Common-Mode Voltage Range 6 VSS to AVDD V min to V max Normal-Mode 50 Hz Rejection 7 100 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 × fNOTCH Normal-Mode 60 Hz Rejection 7 100 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 × fNOTCH Common-Mode 50 Hz Rejection 7 150 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 × fNOTCH Common-Mode 60 Hz Rejection 7 150 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 × fNOTCH DC Input Leakage Current 7 @ 25°C1 0 pA max TMIN to TMAX 1 nA max Sampling Capacitance 7 20 pF max Analog Inputs8 Input Voltage Range 9 For Normal Operation. Depends on Gain Selected 0 to +VREF 10 nom Unipolar Input Range (B/U Bit of Control Register = 1) ± VREF nom Bipolar Input Range (B/U Bit of Control Register = 0) Input Sampling Rate, f S See Table III Reference Inputs REF IN(+) – REF IN(–) Voltage 11 2.5 to 5 V min to V max For Specified Performance. Part Is Functional with Lower VREF Voltages Input Sampling Rate, f S fCLK IN/256 NOTES 1Temperature ranges are as follows: A Version, –40 °C to +85°C; S Version, –55 °C to +125°C. See also Note 16. 2Applies after calibration at the temperature of interest. 3Positive full-scale error applies to both unipolar and bipolar input ranges. 4These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors wi ll be 20 µV typical after self-calibration or background calibration. 5Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and V SS – 30 mV. 7These numbers are guaranteed by design and/or characterization. 8The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximu m recommended source resistance depends on the selected gain (see Tables IV and V). 9The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and A IN2(–) inputs. The absolute voltage on the analog inputs should not go more positive than AV DD + 30 mV or go more negative than V SS – 30 mV. 10VREF = REF IN(+) – REF IN(–). 11The reference input voltage range may be restricted by the input voltage range requirement on the V BIAS input. AD7710–SPECIFICATIONS(AVDD = +5 V /H11550 5%; DVDD = +5 V /H11550 5%; VSS = 0 V or –5 V /H11550 5%; REF IN(+) = +2.5 V; REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise noted. All specifications T MIN to TMAX, unless otherwise noted.)

Parameter A, S Versions 1 Unit Conditions/Comments REFERENCE OUTPUT Output Voltage 2.5 V nom Initial Tolerance @ 25 °C ± 1% max Drift 20 ppm/ °C typ Output Noise 30 µV typ Peak-peak Noise 0.1 Hz to 10 Hz Bandwidth Line Regulation (AV DD)1 mV/V max Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA External Current 1 mA max VBIAS INPUT12 Input Voltage Range AV DD – 0.85 × VREF See VBIAS Input Section or AVDD – 3.5 V max Whichever Is Smaller: +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or AVDD – 2.1 V max Whichever Is Smaller; +5 V/0 V Nominal AV DD/VSS VSS + 0.85 × VREF See VBIAS Input Section or VSS + 3 V min Whichever Is Greater; +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or VSS + 2.1 V min Whichever Is Greater; +5 V/0 V Nominal AV DD/VSS VBIAS Rejection 65 to 85 dB typ Increasing with Gain LOGIC INPUTS Input Current ± 10 µΑ max All Inputs Except MCLK IN VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 2.0 V min MCLK IN Only VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min LOGIC OUTPUTS VOL, Output Low Voltage 0.4 V max I SINK = 1.6 mA VOH, Output High Voltage DV DD – 1 V min I SOURCE = 100 µA Floating State Leakage Current ± 10 µA max Floating State Output Capacitance 13 9 pF typ TRANSDUCER BURNOUT Current 4.5 µA nom Initial Tolerance @ 25 °C ± 10 % typ Drift 0.1 %/ °C typ COMPENSATION CURRENT Output Current 20 µA nom Initial Tolerance @ 25 °C ± 4 µA max Drift 35 ppm/ °C typ Line Regulation (AV DD)2 0 nA/V max AV DD = +5 V Load Regulation 20 nA/V max Output Compliance AV DD – 2 V max SYSTEM CALIBRATION Positive Full-Scale Calibration Limit l4 (1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Negative Full-Scale Calibration Limit l4 –(1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Offset Calibration Limits 15 –(1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Input Span15 0.8 × VREF/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128) (2.1 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) NOTES 12The AD7710 is tested with the following V BIAS voltages. With AV DD = 5 V and V SS = 0 V, VBIAS = 2.5 V; with AV DD = 10 V and V SS = 0 V, VBIAS = 5 V; and with AVDD = 5 V and V SS = –5 V, VBIAS = 0 V. 13Guaranteed by design, not production tested. 14After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is le ss than negative full scale then the device will output all 0s. 15These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AV DD + 30 mV or go more negative than V SS – 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. REV. G –3– AD7710

Parameter A, S Versions l Unit Conditions/Comments POWER REQUIREMENTS Power Supply Voltages AVDD Voltage16 5 to 10 V nom ± 5% for Specified Performance DVDD Voltage17 5V nom ± 5% for Specified Performance AVDD-VSS Voltage 10.5 V max For Specified Performance Power Supply Currents AVDD Current 4 mA max DVDD Current 4.5 mA max VSS Current 1.5 mA max V SS = –5 V Power Supply Rejection 18 Rejection w.r.t. AGND; Assumes V BIAS Is Fixed Positive Supply (AV DD and DVDD) See Note 19 dB typ Negative Supply (V SS)9 0 dB typ Power Dissipation Normal Mode 45 mW max AV DD = DVDD = 5 V, VSS = 0 V; Typically 25 mW 52.5 mW max AV DD = DVDD = 5 V, VSS = –5 V; Typically 30 mW Standby (Power-Down) Mode 15 mW max AV DD = DVDD = 5 V, VSS = 0 V or –5 V; Typically 7 mW NOTES 16The AD7710 is specified with a 10 MHz clock for AV DD voltages of +5 V ±5%. It is specified with an 8 MHz clock for AV DD voltages greater than 5.25 V and less 17The ± 5% tolerance on the DV DD input is allowed provided that DV DD does not exceed AV DD by more than 0.3 V. 18Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 5 0 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz. 19PSRR depends on gain: Gain of 1: 70 dB typ; Gain of 2: 75 dB typ; Gain of 4: 80 dB typ; Gains of 8 to 128: 85 dB typ. These num bers can be improved (to 95 dB typ) by deriving the V BIAS voltage (via Zener diode or reference) from the AV DD supply. Specifications subject to change without notice. Operating Temperature Range *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS * (TA = 25°C, unless otherwise noted.) Analog Input Voltage to AGND Reference Input Voltage to AGND AD7710–SPECIFICATIONS REV. G–4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7710 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. G –5– (DVDD = +5 V /H11550 5%; AVDD = +5 V or +10 V3 /H11550 5%; VSS = 0 V or –5 V /H11550 10%; AGND = DGND = 0 V; fCLK IN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DV DD, unless otherwise noted.)TIMING CHARACTERISTICS1, 2 Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments fCLK IN 4, 5 Master Clock Frequency: Crystal Oscillator or Externally 400 kHz min Supplied for Specified Performance

10 MHz max AV

DD = +5 V ± 5% 8 MHz max AV DD = +5.25 V to +10.5 V tCLK IN LO 0.4 × tCLK IN ns min Master Clock Input Low Time. t CLK IN = 1/fCLK IN tCLK IN HI 0.4 × tCLK IN ns min Master Clock Input High Time tr 6 50 ns max Digital Output Rise Time. Typically 20 ns tf 6 50 ns max Digital Output Fall Time. Typically 20 ns t1 1000 ns min SYNC Pulse Width Self-Clocking Mode t2 0 ns min DRDY to RFS Setup Time t3 0 ns min DRDY to RFS Hold Time t4 2 × tCLK IN ns min A0 to RFS Setup Time t5 0 ns min A0 to RFS Hold Time t6 4 × tCLK IN + 20 ns max RFS Low to SCLK Falling Edge 7 4 × tCLK IN + 20 ns max Data Access Time ( RFS Low to Data Valid) 7 tCLK IN/2 ns min SCLK Falling Edge to Data Valid Delay tCLK IN/2 + 30 ns max t9 tCLK IN/2 ns nom SCLK High Pulse Width t10 3 × tCLK IN/2 ns nom SCLK Low Pulse Width t14 50 ns min A0 to TFS Setup Time t15 0 ns min A0 to TFS Hold Time t16 4 × tCLK IN + 20 ns max TFS to SCLK Falling Edge Delay Time t17 4 × tCLK IN ns min TFS to SCLK Falling Edge Hold Time t18 0 ns min Data Valid to SCLK Setup Time t19 10 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 10 to 13. 3The AD7710 is specified with a 10 MHz clock for AV DD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV DD voltages greater than 5.25 V and less than 10.5 V. 4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7710 is not in STANDBY mode. If no clock is prese nt in this case, the device can draw higher current than specified and possibly become uncalibrated. 5The AD7710 is production tested with f CLK IN at 10 MHz (8 MHz for AV DD > 5.25 V). It is guaranteed by characterization to operate at 400 kHz. 6Specified using 10% and 90% points on waveform of interest. 7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. ORDERING GUIDE Temperature Package Model1 Range Options 2 AD7710AN –40 °C to +85°C N-24 AD7710AR –40 °C to +85°C R-24 AD7710AR-REEL –40 °C to +85°C R-24 AD7710AR-REEL7 –40 °C to +85°C R-24 AD7710ARZ3 –40°C to +85°C R-24 AD7710ARZ-REEL3 –40°C to +85°C R-24 AD7710ARZ-REEL73 –40°C to +85°C R-24 AD7710AQ –40 °C to +85°C Q-24 AD7710SQ –55 °C to +125°C Q-24 EVAL-AD7710EB Evaluation Board NOTES 1Contact your local sales office for military data sheet and availability. 2N = PDIP; Q = CERDIP; R = SOIC. 3Z = Pb-free part.

relinquish times of the part and, as such, are independent of external bus loading capacitances. Specifications subject to change without notice. Figure 1. Load Circuit for Access Time and

REV. G –7– PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when the device has completed transmission of an output word. When MODE is low, the device is in its external clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7710 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz. 3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. 4A 0A ddress Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. 5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7710s. It resets the nodes of the digital filter. 6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its external clocking mode. 7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source that can be used to check that an external transducer has burned out or gone open circuit. This output current source can be turned on/off via the control register. 8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input. 9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input. 10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input. 11 V SS Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1 or AIN2 should not go > 30 mV negative w.r.t. V SS for correct operation of the device. 12 AV DD Analog Positive Supply Voltage, 5 V to 10 V. 13 V BIAS Input Bias Voltage. This input voltage should be set such that V BIAS + 0.85 × VREF < AVDD and VBIAS – 0.85 × VREF > VSS where VREF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AVDD and VSS. Thus with AVDD = 5 V and VSS = 0 V, it can be tied to REF OUT; with AV DD = 5 V and VSS = –5 V, it can be tied to AGND; with AV DD = 10 V, it can be tied to 5 V. 14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV DD and VSS provided REF IN(+) is greater than REF IN(–). 15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–). REF IN(+) can lie anywhere between AV DD and VSS. 16 REF OUT Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output which is referred to AGND. It is a buffered output which is capable of providing 1 mA to an external load. 17 I OUT Compensation Current Output. A 20 µA constant current is provided at this pin. This current can be used in association with an external thermistor to provide cold junction compensation in thermocouple applications. This current can be turned on or off via the control register. 18 AGND Ground Reference Point for Analog Circuitry.

REV. G–8– AD7710 Pin Mnemonic Function 19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7710 has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis- ters, and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DV DD Digital Supply Voltage, 5 V. DV DD should not exceed AVDD by more than 0.3 V in normal operation. 24 DGND Ground Reference Point for Digital Circuitry. Terminology Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be con- fused with bipolar zero), a point 0.5 LSB below the first code 111). The error is expressed as a percentage of full scale. Positive Full-Scale Error Positive full-scale error is the deviation of the last code transi- (AIN(–) + V REF/GAIN – 3/2 LSBs). It applies to both unipolar and bipolar analog input ranges. Unipolar Offset Error Unipolar offset error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- ating in the unipolar mode. Bipolar Zero Error This is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB) when operating in the bipolar mode. Bipolar Negative Full-Scale Error This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – V REF/GAIN + 0.5 LSB) when operat- ing in the bipolar mode. Positive Full-Scale Overrange Positive full-scale overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than AIN(–) + V REF/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without intro- ducing errors due to overloading the analog modulator or to overflowing the digital filter. Negative Full-Scale Overrange This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) –VREF/GAIN without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the uni- polar mode provided that AIN(+) is greater than AIN(–) and greater than V SS – 30 mV. Offset Calibration Range In the system calibration modes, the AD7710 calibrates its offset with respect to the analog input. The offset calibration range specification defines the range of voltages that the AD7710 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the range of voltages that the AD7710 can accept in the system calibration mode and still calibrate full scale correctly. Input Span In system calibration schemes, two voltages applied in sequence to the AD7710’s analog input define the analog input range. The input span specification defines the minimum and maxi- mum input voltages from zero- to full-scale that the AD7710 can accept and still calibrate gain accurately.

REV. G –9– CONTROL REGISTER (24 BITS) A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low acc esses the contents of the control register. The control register is 24 bits wide; 24 bits of data must be written to the register or the data will not be loaded. In other words, it is not possible to write just the first 12 bits of data into the control register. If more than 2 4 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data. MSB MD2 MD1 MD0 G2 G1 G0 CH PD WL IO BO B/U FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 LSB Operating Mode MD2 MD1 MD0 Operating Mode 00 0N ormal Mode. This is the normal mode where a read to the device with A0 high accesses data from the data register. This is the default condition of these bits after the internal power-on reset. 00 1A ctivate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of the control register returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete. For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the full-scale calibration is done internally on V REF. 01 0A ctivate System Calibration. This activates system calibration on the channel selected by CH. This is a two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the end of this first step in the two-step sequence. 01 1A ctivate System Calibration. This is the second step of the system ca libration sequence with full-scale calibration being performed on the selected input channel. Once again, DRDY indicates when the full- scale calibration is complete. When this calibration is complete, the part returns to normal mode. 10 0A ctivate System Offset Calibration. This activates system offset calibration on the channel selected by CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale calibration is done on the selected input channel, and the full-scale calibration is done internally on V REF. 10 1A ctivate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7710 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. The major advantage of using this mode is that the user does not have to recalibrate the device when there is a change in the ambient temperature. In this mode, the shorted (zeroed) inputs and V REF, as well as the analog input voltage, are continuously monitored and the calibration registers of the device are automatically updated. 11 0R ead/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, 24 bits of data must be written to the calibration register, or the new data will not be transferred to the calibration register. 11 1R ead/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, 24 bits of data must be written to the calibration register, or the new data will not be transferred to the calibration register.

REV. G–10– AD7710 PGA GAIN G2 G1 G0 Gain 000 1( Default Condition after the Internal Power-On Reset) 001 2 010 4 011 8 100 1 6 101 3 2 110 6 4 111 1 2 8 CHANNEL SELECTION CH Channel

0 AIN1 (Default Condition after the Internal Power-On Reset)

1 AIN2

0N ormal Operation (Default Condition after the Internal Power-On Reset)

1 Power-Down

0 16-Bit (Default Condition after Internal Power-On Reset) 1 24-Bit Output Compensation Current IO 0O ff (Default Condition after Internal Power-On Reset) 1O n Burn-Out Current BO 0O ff (Default Condition after Internal Power-On Reset) 1O n Bipolar/Unipolar Selection (Both Inputs) B/U

0 Bipolar (Default Condition after Internal Power-On Reset)

1 Unipolar

FILTER SELECTION (FS11–FS0) The on-chip digital filter provides a sinc 3 (or (sinx/x)3) filter response. The 12 bits of data programmed into these bits deter- mine the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selection, it also determines the output noise (and therefore the effective resolution) of the device. The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f CLK IN/512)/code where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal f CLK IN of 10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7710, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the AD7710. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms. The settling time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). This settling time is to 100% of the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be reduced to 3 × l/(output data rate) by syn- chronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with SYNC low, the settling time will be 3 × l/(output data rate). If a change of chan- nels takes place, the settling time is 3 × l/(output data rate) regardless of the SYNC input. The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency = 0.262 × first notch frequency.

REV. G –11– Table I. Output Noise vs. Gain and First Notch Frequency First Notch of Typical Output RMS Noise (/H9262V) Filter and O/P –3 dB Data Rate1 Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 250 Hz3 65.5 Hz 130 75 25 12 7.5 4 2.7 1.7 500 Hz3 131 Hz 0.6 × 103 0.26 × 103 140 70 35 25 15 8 1 kHz3 262 Hz 3.1 × 103 1.6 × 103 0.7 × 103 0.29 × 103 180 120 70 40 NOTES 1The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz. 2For these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independe nt of the value of the reference voltage. Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (that is, the ratio of the rms noise to the input full scale is increased because the output rms noise remains constant as the input full scale increases). 3For these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage. Table II. Effective Resolution vs. Gain and First Notch Frequency First Notch of Effective Resolution* (Bits) Filter and O/P –3 dB Data Rate Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 60 Hz 15.72 Hz 20 20 20 19.5 19 18 17 16 500 Hz 131 Hz 13 13 13 13 13 12.5 12.5 12.5 1 kHz 262 Hz 10.5 10.5 11 11 11 10.5 10 10 NOTE *Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 × VREF/GAIN). The above table applies for a V REF of 2.5 V and resolution numbers are rounded to the nearest 0.5 LSB. Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar input ranges with a V REF of 2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). Second, when the analog input signal is converted into the digital do- main, quantization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increas- ing frequency to become the dominant noise source. Conse- quently, lower filter notch settings (below 60 Hz approximately) tend to be device-noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. At the lower filter notch settings (below 60 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at the 1 kHz notch setting; no missing codes performance is guaranteed only to the 12-bit level. However, because the effective reso- lution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should be more than adequate for all applications. The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not re- main constant with increasing gain or with increasing band- width. Table II is the same as Table I except that the output is expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 × V REF/GAIN, the input full scale). It is possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce the output noise (see the Digital Filtering section).

adequate antialiasing filtering. channels look into similar input circuitry. Figure 7. Analog Input Impedance channels that can handle either unipolar or bipolar input signals. between VSS –30 mV and AVDD +30 mV. tial input capability of the part and its system calibration mode. the BO bit in the control register. IO bit of the control register enables this compensation current. variation of the thermistor’s resistance with temperature.

are chosen by programming the B/U bit of the control register. This programs both channels for either type of operation. inputs and offset binary for bipolar inputs. to provide the nominal 2.5 V reference for the AD7710. VSS limits, and the VBIAS input voltage range limits are obeyed. than REF IN(–) for correct operation of the AD7710. and for a gain of 128, it is 1.25 pF. Figure 8. REF OUT/REF IN Connection be driven from a low impedance point to minimize errors. allowable range for the V BIAS voltage is 2.125 V to 2.625 V. and VREF = +2.5 V, the VBIAS range is –2.625 V to +2.625 V. power supply rejection performance.

REV. G –17– USING THE AD7710 SYSTEM DESIGN CONSIDERATIONS The AD7710 operates differently from successive approxima- tion ADCs or integrating ADCs. Because it samples the signal continuously, like a tracking ADC, there is no need for a start convert command. The output register is updated at a rate determined by the first notch of the filter, and the output can be read at any time, either synchronously or asynchronously. Clocking The AD7710 requires a master clock input, which may be an external TTL/CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal of the correct frequency can be connected between MCLK IN and MCLK OUT, in which case the clock circuit will function as a crystal-controlled oscillator. For lower clock frequencies, a ceramic resonator may be used instead of the crystal. For these lower frequency oscillators, external capacitors may be required on either the ceramic resonator or on the crystal. The input sampling frequency, the modulator sampling fre- quency, the –3 dB frequency, the output update rate, and the calibration time are all directly related to the master clock fre- quency f CLK IN. Reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and will double the calibration time. The current drawn from the DV DD power supply is also directly related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the DVDD current but will not affect the current drawn from the AVDD power supply. System Synchronization If multiple AD7710s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. A falling edge on the SYNC input resets the filter and places the AD7710 into a consistent, known state. A common signal to the AD7710s’ SYNC inputs will synchronize their operation. This would typically be done after each AD7710 has performed its own calibration or has had calibration coefficients loaded to it. The SYNC input can also be used to reset the digital filter in systems where the turn-on time of the digital power supply (DV DD) is very long. In such cases, the AD7710 will start oper- ating internally before the DV DD line has reached its minimum operating level, 4.75 V. With a low DV DD voltage, the AD7710’s internal digital filter logic does not operate correctly. Thus, the AD7710 may have clocked itself into an incorrect operating condition by the time that DV DD has reached its cor- rect level. The digital filter will be reset upon issue of a calibra- tion command (whether it is self-calibration, system calibration, or background calibration) to the AD7710. This ensures correct operation of the AD7710. In systems where the power-on default conditions of the AD7710 are acceptable, and no cali- bration is performed after power-on, issuing a SYNC pulse to the AD7710 will reset the AD7710’s digital filter logic. An R, C on the SYNC line, with R, C time constant longer than the DV DD power-on time, will perform the SYNC function. Accuracy Sigma-delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7710 achieves excellent linearity by the use of high quality, on-chip silicon dioxide capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper stabilized techniques in its input stage. To ensure excellent perfor- mance over time and temperature, the AD7710 uses digital calibration techniques that minimize offset and gain error. Autocalibration Autocalibration on the AD7710 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch, or bipolar/unipolar input range. However, if the AD7710 is in its background cali- bration mode, these changes are all automatically taken care of (after the settling time of the filter has been allowed for). The AD7710 offers self-calibration, system calibration, and background calibration facilities. For calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are zero-scale and full-scale points. With these readings, the micro- controller can calculate the gain slope for the input to output transfer function of the converter. Internally, the part works with a resolution of 33 bits to determine its conversion result of either 16 bits or 24 bits. The AD7710 also provides the facility to write to the on-chip calibration registers, and, in this manner, the span and offset for the part can be adjusted by the user. The offset calibration regis- ter contains a value that is subtracted from all conversion results, while the full-scale calibration register contains a value that is multiplied by all conversion results. The offset calibration coefficient is subtracted from the result prior to the multiplica- tion by the full-scale coefficient. In the first three modes out- lined here, the DRDY line indicates that calibration is complete by going low. If DRDY is low before (or goes low during) the calibration command, it may take up to one modulator cycle before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the control register. Self-Calibration In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with both inputs shorted (that is, AIN(+) = AIN(–) = V BIAS) and the full-scale point is V REF. The zero-scale coefficient is determined by converting an internal shorted inputs node. The full-scale coefficient is determined from the span between this shorted inputs conversion and a conversion on an internal V REF node. The self-calibration mode is invoked by writing the appro- priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the control register. In this calibration mode, the shorted inputs node is switched in to the modulator first and a conversion is

REV. G–18– AD7710 performed; the VREF node is then switched in and another conver- sion is performed. When the calibration sequence is complete, the calibration coefficients updated, and the filter resettled to the ana- log input voltage, the DRDY output goes low. The self-calibration procedure takes into account the selected gain on the PGA. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points that the AD7710 calibrates are midscale (bipolar zero) and positive full scale. System Calibration System calibration allows the AD7710 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as self-calibration but uses voltage values presented by the sys- tem to the AIN inputs for the zero- and full-scale points. System calibration is a two-step process. The zero-scale point must be presented to the converter first. It must be applied to the con- verter before the calibration step is initiated and remain stable until the step is complete. System calibration is initiated by writing the appropriate values (0, 1, 0) to the MD2, MD1, MD0 bits of the control register. The DRDY output from the device will signal when the step is complete by going low. After the zero-scale point is calibrated, the full-scale point is applied, and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to MD2, MD1, MD0. Again the full-scale voltage must be set up before the calibration is initiated, and it must remain stable throughout the calibration step. DRDY goes low at the end of this second step to indicate that the system calibration is complete. In the uni- polar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. This two-step system calibration mode offers another feature. After the sequence has been completed, additional offset or gain calibrations can be performed by themselves to adjust the zero reference point or the system gain. This is achieved by perform- ing the first step of the system calibration sequence (by writing 0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or offset point but will not change the slope factor from that set during a full system calibration sequence. System calibration can also be used to remove any errors from an antialiasing filter on the analog input. A simple R, C anti- aliasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. System Offset Calibration System offset calibration is a variation of both the system cali- bration and self-calibration. In this case, the zero-scale point for the system is presented to the AIN input of the converter. System offset calibration is initiated by writing 1, 0, 0 to MD2, MD1, MD0. The system zero-scale coefficient is determined by converting the voltage applied to the AIN input, while the full- scale coefficient is determined from the span between this AIN conversion and a conversion on V REF. The zero-scale point should be applied to the AIN input for the duration of the cali- bration sequence. This is a one-step calibration sequence with DRDY going low when the sequence is completed. In unipolar mode, the system offset calibration is performed between the two endpoints of the transfer function; in bipolar mode, it is performed between midscale and positive full scale. Background Calibration The AD7710 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. In background calibration mode, the same voltages are used as the calibration points that are used in the self-calibration mode, that is, shorted inputs and V REF. The background calibration mode is invoked by writing 1, 0, 1 to MD2, MD1, MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7710 by a factor of 6 while the –3 dB bandwidth remains unchanged. The advantage is that the part is continually per- forming calibration and automatically updating its calibration coefficients. As a result, the effects of temperature drift, sup- ply sensitivity, and time drift on zero- and full-scale errors are automatically removed. When the background calibration mode is turned on, the part will remain in this mode until bits MD2, MD1, and MD0 of the control register are changed. With back- ground calibration mode on, the first result from the AD7710 will be incorrect because the full-scale calibration will not have been performed. For a step change on the input, the second output update will have settled to 100% of the final value. Table VI summarizes the calibration modes and the calibration points associated with them. It also gives the duration from when the calibration is invoked to when valid data is available to the user. Table VI. Calibration Truth Table Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration Self-Cal 0, 0, 1 Shorted Inputs V REF One Step 9 × 1/Output Rate System Cal 0, 1, 0 AIN Two Steps 4 × 1/Output Rate System Cal 0, 1, 1 AIN Two Steps 4 × 1/Output Rate System Offset Cal 1, 0, 0 AIN V REF One Step 9 × 1/Output Rate Background Cal 1, 0, 1 Shorted Inputs V REF One Step 6 × 1/Output Rate

the offset can be is (0.25 × VREF/GAIN). allowable offset range is ±(0.65 × VREF/GAIN). routine should be performed after power-up. internal capacitors. It is not affected by leakage currents. errors are not significantly affected by temperature changes. AGND is the ground return for this reference voltage. except at integer multiples of the modulator sampling frequency. Figure 9. Recommended Decoupling Scheme microprocessors, microcontrollers, and digital signal processors. or the calibration registers. mode, are discussed in detail in the following sections. instead of the pull-up resistor shown in Figure 10 and Figure 11.

REV. G–28– AD7710 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1 12 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) SEATING PLANE 0.015 (0.38) MIN 0.180 (4.57) MAX 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) BSC 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AG 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) 11 2 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 1.280 (32.51) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. G –29– 24-Lead Standard Small Outline Package [SOIC] Wide Body (R-24) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AD 8/H11543 0/H11543 0.75 (0.0295) 0.25 (0.0098) /H11547 45/H11543 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 24 13 121 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) COPLANARITY 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) OUTLINE DIMENSIONS

REV. G–30– AD7710

Revision History

3/04—Data Sheet changed from REV. F to REV. G.

–31– 3/26/04 5:00 AM_MB

C01168-0-3/04(G) –32–