AD7709ARUZ

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a AD7709 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. REV. A 16-Bit /H9018-/H9004 ADC with Switchable Current Sources FUNCTIONAL BLOCK DIAGRAM VDD IEXC1 IEXC2 8IIOUT1 IOUT2 IEXC3 I OSCILLATOR AND PLL XTAL2REFIN1(–) REFIN2(–)REFIN1(+) REFIN2(+) XTAL1 DOUT RESET RDY CS SCLK DINSERIAL INTERFACE AND CONTROL LOGICBUF PGA MUX I/O PORT VDD 16-BIT /H9018-/H9004 ADC AIN1 AIN2 AIN3/P3 AIN4/P4 AINCOM AD7709 VDD GND PWRGND P1/SW1 P2/SW2 I = 25/H9262A

FEATURES

Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz Update Rate VREF Select ™ Allows Absolute and Ratiometric Measurement Capability ISOURCE Select ™ 16-Bit No Missing Codes 13-Bit p-p Resolution @ 20 Hz, 20 mV Range 16-Bit p-p Resolution @ 20 Hz, 2.56 V Range INTERFACE 3-Wire Serial SPI® , QSPI™, MICROWIRE™, and DSP Compatible Schmitt Trigger on SCLK POWER Specified for Single 3 V and 5 V Operation Normal: 1.25 mA Typ @ 3 V Power-Down: 7 /H9262A (32.768 kHz Crystal Running) ON-CHIP FUNCTIONS Rail-to-Rail Input Buffer and PGA Selectable Reference Inputs

3 Switchable, Ratioed Current Sources for

V BE Measurements 4-Bit Digital I/O Port Low-Side Power Switches

APPLICATIONS

4–20 mA Loops GENERAL DESCRIPTION The AD7709 is a complete analog front end for low frequency measurement applications. It contains a 16-bit /H9018-/H9004 ADC, selectable reference inputs, three switchable matched excitation current sources, low-side power switches, and a digital I/O port. The 16-bit channel with PGA accepts fully differential, unipolar, and bipolar input signal ranges from 1.024 /H11003 REFIN/128 to 1.024 /H11003 REFIN. It can be configured as two fully differential input channels or four pseudo-differential input channels. Signals can be converted directly from a transducer without the need for signal conditioning. The device operates from a 32.768 kHz crystal with an on-chip PLL generating the required internal operating frequency. The output data rate from the part is software programmable. The p-p resolution from the part varies with the programmed gain and output data rate. The part operates from a single 3 V or 5 V supply. When operating from 3 V supplies, the power dissipation for the part is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package.

REV. A AD7709 –2– TABLE OF CONTENTS TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10 MICROCOMPUTER/MICROPROCESSOR

REV. A –3– AD7709 32.768 kHz Crystal; all specifications T MIN to TMAX, unless otherwise noted.) Parameter AD7709A, AD7709B Unit Test Conditions ADC CHANNEL SPECIFICATION Output Update Rate 5.4 Hz min 0.732 ms Increments

105 Hz max

No Missing Codes 2 16 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ± 20 mV Range, 20 Hz Update Rate 16 Bits p-p ± 2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables II to V Integral Nonlinearity 2 ± 30 ppm of FSR max Typically 2 ppm FSR REFIN GAIN= ¥21 024. Offset Error ± 3 mV typ Offset Error Drift vs. Temperature ± 10 nV/ ∞C typ Full-Scale Error 3 ± 0.75 LSB typ B Grade, V DD = 4 V ± 0.2 % of FS typ A Grade Gain Drift vs. Temperature ± 0.5 ppm/ ∞C typ Power Supply Rejection (PSR) 85 dB typ Input Range = ± 2.56 V 100 dB typ on ± 20 mV Range ANALOG INPUTS Differential Input Voltage Ranges ±¥1 024. REFIN GAIN V nom REFIN = REFIN(+) – REFIN(–) GAIN = 1 to 128 ADC Range Matching ± 2 mV typ Input Voltage = 19 mV on All Ranges V DD – 100 mV V max AIN1–AIN4 Analog Input Current DC Input Current 2 ± 1 nA max DC Input Current Drift ± 5 pA /∞C typ Absolute AINCOM Voltage Limits 2 GND – 30 mV V min VDD + 30 mV V max AINCOM Analog Input Current Pseudo-Differential Mode of Operation DC Input Current ± 125 nA/V typ Input Current Varies with Input Range DC Input Current Drift ± 2 pA/V/∞C typ Normal-Mode Rejection 2, 4 @ 50 Hz 100 dB min 50 Hz ± 1H z, 16.65 Hz Update Rate, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68 Common-Mode Rejection @ DC 100 dB typ Input Range = ± 2.56 V, AIN = 1 V 110 dB typ on ± 20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V REFERENCE INPUTS (REFIN1 and REFIN2) REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) REFIN Voltage Range 2 1V min VDD V max Absolute REFIN Voltage Limits 2 GND – 30 mV V min VDD + 30 mV V max Average Reference Input Current 0.5 mA/V typ Average Reference Input Current Drift ± 0.01 nA/V/ ∞C typ Normal-Mode Rejection 2, 4 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF = 68 Common-Mode Rejection @ DC 110 dB typ Input Range = ± 2.56 V, AIN = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V See Notes on page 5.

REV. A–4– AD7709 Parameter AD7709A, AD7709B Unit Test Conditions EXCITATION CURRENT SOURCES (IEXC1, IEXC2, and IEXC3) Output Current IEXC1, IEXC2 200 mA nom IEXC3 25 mA nom Initial Tolerance at 25 ∞C ± 10 % typ Drift 200 ppm/ ∞C typ Initial Current Matching at 25 ∞C ± 2.5 % max B Grade, No Load (between IEXC1 and IEXC2) ± 2.5 % typ A Grade, No Load Drift Matching (between IEXC1 and IEXC2) 20 ppm/ ∞C typ Initial Current Matching at 25 ∞C ± 5% max B Grade, No Load (between 8 /H11003 IEXC3 and IEXC1/IEXC2) ± 5% typ A Grade, No Load Drift Matching (between 8 /H11003 IEXC3 and IEXC1/IEXC2) 20 ppm/ ∞C typ Line Regulation VDD = 5 V ± 5% IEXC1, IEXC2 1.25 mA/V typ A, B Grades 2.6 mA/V max B Grade IEXC3 1 mA/V max B Grade 1 mA/V typ A Grade Load Regulation 300 nA/V typ Output Compliance V DD – 0.6 V max GND –30 mV V min LOW-SIDE POWER SWITCHES (SW1 and SW2) RON 3 W typ V DD = 5 V, A and B Grade

5 W max B Grade

4.5 W typ V DD = 3 V, A and B Grade

7 W max B Grade

Allowable Current 2 20 mA max Continuous Current per Switch LOGIC INPUTS All Inputs Except SCLK and XTAL1 2 VINL, Input Low Voltage 0.8 V max V DD = 5 V

0.4 V max V DD = 3 V

VINH, Input High Voltage 2.0 V min V DD = 3 V or 5 V SCLK Only (Schmitt-Triggered Input)2 VT(+) 1.4/2 V min/V max V DD = 5 V VT(–) 0.8/1.4 V min/V max V DD = 5 V VT(+) – VT(–) 0.3/0.85 V min/V max V DD = 5 V VT(+) 0.95/2 V min/V max V DD = 3 V VT(–) 0.4/1.1 V min/V max V DD = 3 V VT(+) – VT(–) 0.3/0.85 V min/V max V DD = 3 V XTAL1 Only2 VINL, Input Low Voltage 0.8 V max V DD = 5 V VINH, Input High Voltage 3.5 V min V DD = 5 V VINL, Input Low Voltage 0.4 V max V DD = 3 V VINH, Input High Voltage 2.5 V min V DD = 3 V Input Currents (except XTAL) ± 2 mA max V IN = VDD –70 mA max V IN = GND, Typically –40 mA @ 5 V and –20 mA at 3 V; Weak Pull-Ups on the Logic Inputs Input Capacitance 10 pF typ All Digital Inputs (continued)SPECIFICATIONS

REV. A Parameter AD7709A, AD7709BU nit Test Conditions LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage 2 VDD – 0.6 V min V DD = 3 V, ISOURCE = 100 mA VOL, Output Low Voltage 2 0.4 V max V DD = 3 V, ISINK = 100 mA VOH, Output High Voltage 2 4V min V DD = 5 V, ISOURCE = 200 mA VOL, Output Low Voltage 2 0.4 V max V DD = 5 V, ISINK = 1.6 mA Floating-State Leakage Current ± 10 mA max Floating-State Output Capacitance ± 10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode I/O PORT VINL, Input Low Voltage 2 0.8 V max V DD = 5 V VINH, Input High Voltage 2 2.0 V min V DD = 3 V or 5 V Input Currents ± 2 mA max V IN = VDD –70 mA max V IN = GND, Typically –40 mA @ VDD = 5 V and –20 mA at VDD = 3 V; Weak Pull-Ups on the Logic Inputs Input Capacitance 10 pF typ All Digital Inputs VOH, Output High Voltage 2 VDD – 0.6 V min V DD = 3 V, ISOURCE = 100 mA VOL, Output Low Voltage 2 0.4 V max V DD = 3 V, ISINK = 100 mA VOH, Output High Voltage 2 4V min V DD = 5 V, ISOURCE = 200 mA VOL, Output Low Voltage 2 0.4 V max V DD = 5 V, ISINK = 1.6 mA Floating-State Output Leakage Current ± 10 mA max Floating-State Output Capacitance ± 10 pF typ START-UP TIME From Power-On 300 ms typ From Standby Mode 1 ms typ OSCPD = 0 From Power-Down Mode 300 ms typ OSCPD = 1 POWER REQUIREMENTS Power Supply Voltage VDD – GND 2.7/3.6 V min/max V DD = 3 V nom 4.75/5.25 V min/max V DD = 5 V nom Power Supply Currents IDD Current 1.5 mA max V DD = 3 V, 1.25 mA typ 1.75 mA max V DD = 5 V, 1.45 mA typ IDD (Low Power Mode) 7 mA max B Grade, V DD = 3 V, Standby Mode 7 mA typ A Grade, V DD = 3 V, Standby Mode 1.5 mA max B Grade, V DD = 3 V, Power-Down Mode 1.5 mA typ A Grade, V DD = 3 V, Power-Down Mode 26 mA max B Grade, V DD = 5 V, Standby Mode 26 mA typ A Grade, V DD = 5 V, Standby Mode 6.5 mA max B Grade, V DD = 5 V, Power-Down Mode 6.5 mA typ A Grade, V DD = 5 V, Power-Down Mode IDD for One Conversion Second 107 5 mA typ V DD = 3 V, Standby Mode 1345 mA typ V DD = 5 V, Standby Mode NOTES 1Temperature Range –40 ∞C to +85∞C. 2Guaranteed by design and/or characterization data on production release. 3Full-scale error applies to both positive and negative full scale. 4Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.79 Hz update rate. Normal mode rejection in this case is 60 dB min. 5When the part is placed in power-down mode for a single conversion/second, at an update rate of 19.79 Hz, the current consumpti on is higher compared to when the part is placed in standby mode as the crystal oscillator takes approximately 100 ms to begin clocking. The device will, therefo re, use full current for the conversion time and the 100 ms period required for the oscillator to begin clocking. However, if the conversion rate is lower, the current consumption will be reduced so that it is worthwhile to use the power-down rather than the standby mode. Specifications subject to change without notice. AD7709 –5–

REV. A AD7709 –6– TIMING CHARACTERISTICS1, 2 Limit at TMIN, TMAX Parameter (A, B Version) Unit Conditions/Comments t1 30.5176 ms typ Crystal Oscillator Period t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 4 0 ns min SCLK Active Edge to Data Valid Delay 3 60 ns max V DD = 4.75 V to 5.25 V 80 ns max V DD = 2.7 V to 3.6 V t5A 4, 5 0 ns min CS Falling Edge to Data Valid Delay 60 ns max V DD = 4.75 V to 5.25 V 80 ns max V DD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 3 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge 3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 5This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Cha racteristics table are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Logic 1 = VDD unless otherwise noted.)

REV. A AD7709 –8– WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATION TOP VIEW (Not to Scale) AD7709 GND VDD XTAL2 XTAL1 RDY DOUT DIN RESET SCLK CS P1/SW1 PWRGND IOUT1 IOUT2 REFIN1(+) REFIN1(–) AIN1 AIN2 AIN3/P3 AIN4/P4 AINCOM P2/SW2 REFIN2(+) REFIN2(–) ABSOLUTE MAXIMUM RATINGS * (TA = 25∞C, unless otherwise noted.) Lead Temperature, Soldering *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option AD7709ARU –40 ∞C to +85∞C TSSOP RU-24 AD7709BRU –40 ∞C to +85∞C TSSOP RU-24 EVAL-AD7709EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A AD7709 –9– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 IOUT1 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina- tion of the current sources, can be switched to this output. 2 IOUT2 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina- tion of the current sources, can be switched to this output. 3 REFIN1(+) Positive Reference Input. REFIN1(+) can lie anywhere between V DD and GND + 1 V. The nominal refer- ence voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to VDD. 4 REFIN1(–) Negative Reference Input. This reference input can lie anywhere between GND and V DD – 1 V. 5 AIN1 Analo g Input. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully differential input pair when used with AIN2. 6 AIN2 Analo g Input. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully differential input pair when used with AIN1. 7 AIN3/P3 Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully differential input pair when used with AIN4. This pin can also be programmed as a general-purpose digital input bit. 8 AIN4/P4 Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3. This pin can also be programmed as a general-purpose digital input bit. 9 AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode. 10 REFIN2(+) Positive Reference Input. REFIN2(+) can lie anywhere between V DD and GND + 1 V. The nominal reference voltage (REFIN2(+) – REFIN2(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V DD. 11 REFIN2(–) Negative Reference Input. This reference input can lie anywhere between GND and V DD – 1 V. 12 P2/SW2 Dual-Purpose Pin. It can act as a general-purpose output (P2) bit or as a low-side power switch (SW2) to PWRGND. 13 PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to GND. 14 P1/SW1 Dual-Purpose Pin. It can act as a general-purpose output (P1) bit or as a low-side power switch (SW1) to PWRGND. 15 RESET Digital Input Used to Reset the ADC to Its Power-On-Reset Status. This pin has a weak pull-up internally to VDD. 16 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input making the interface suitable for opto-isolated applications. The serial clock can be conti nuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7709 in smaller batches of data. A weak pull-up to V DD is provided on the SCLK input. 17 CS Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the AD7709 in systems with more than one device on the serial bus or as a frame synchronization signal in com- municating with the device. CS can be hardwired low allowing the AD7709 to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to VDD is provided on the CS input. 18 RDY RDY is a Logic Low Status Output from the AD7709. RDY is low if the ADC has valid data in its data register. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update indicating to the user that a read operation should not be initiated. 19 DOUT Serial Data Output Accessing the Output Shift Register of the AD7709. The output shift register can contain data from any of the on-chip data or control registers. 20 DIN Serial Data Input Accessing the Input Shift Register on the AD7709. Data in this shift register is transferred to the control registers within the ADC, the selection bits of the communications register selecting which control register. A w eak pull-up to VDD is provided on the DIN input.

21 GND Ground Reference Point for the AD7709

22 V DD Supply Voltage, 3 V or 5 V Nominal

23 XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter 24 XTAL1 Input to the 32.768 kHz Crystal Oscillator Inverter

REV. A AD7709–Typical Performance Characteristics –10– 200 3276732766 32768 32770 32769 600 500 400 300 700 CODE OCCURRENCE 32771 100 TPC 3. Noise Histogram OSCILLA TOR VDD = 5V TA = 25/H11543C TIME BASE = 100ms/DIV TRACE 1 = TRACE 2 = 2V/DIV VDD TPC 4. Typical Oscillator Power-Up 32767 1000 200 400300 32771 32770 32769 32768 32772 READING NUMBER CODE READ 500 32766 32765 32764 600 700 800 900 1000 VDD = 5V INPUT RANGE = /H1155020mV UPDA TE RA TE = 19.79Hz VREF = 2.5V TA = 25 C TPC 1. Typical Noise Plot on ±20 mV Input Range 2.5 2.0 1.5 1.0 0.5 3.0 VREF – V RMS NOISE – /H9262V /H1155020mV RANGE /H115502.56V RANGE VDD = 5V VREF = 2.5V INPUT RANGE = /H115502.56V UPDA TE RA TE = 19.79Hz TA = 25/H11543C TPC 2. RMS Noise vs. Reference Input

pressure transducer, or temperature measurement applications. reduction) can be placed on the analog inputs if required. tors. With chopping, the ADC repeatedly reverses its inputs. fADC is the ADC update rate. fMOD is the modulator sampling rate of 32.768 kHz. ADC. The chop rate of the channel is half the output data rate. SF = value programmed into Filter Register. Figure 4. ADC Channel Block Diagram

within a six-sigma limit. The output noise comes from two sources. (device noise) used in the implementation of the modulator. Figure 9. On-Chip Registers which effectively means losing 1 bit of resolution. state and cleared implies a Logic 0 state, unless otherwise stated.

REV. A AD7709 –14– Communications Register (A1, A0 = 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation t o the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or wr ite operation to the selected register is complete, the interface returns to where it expects a write operation to the Communicatio ns Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for a write operation to the Communications Register. In situations w here the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table IV outlines the bit designations for the Communications Register. CR0 to CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. 7RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC NEW )0( /R W )0() 0(YBTS) 0(DPCSO) 0(0) 0(0) 0(1A) 0(A Table IV. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register. CR6 R/ W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR5 STBY Standby Bit Location. A 1 in this location places the AD7709 in low power mode. A 0 in this location powers up the AD7709. CR4 OSCPD Oscillator Power-Down Bit. If this bit is set, placing the AD7709 in standby mode will stop the crystal oscillator also, reducing the power consumed by the part to a minimum. The oscillator will require 300 ms to begin oscillating when the ADC is taken out of power-down mode. If this bit is cleared, the oscillator is not stopped when the ADC is placed in power-down mode. When the ADC is taken out of power-down mode, the oscillator does not require the 300 ms start-up time. CR3–CR2 0 These bits must be programmed with a Logic 0 for correct operation. CR1–CR0 A1–A0 Register Address Bits. These address bits are used to select which of the AD7709 registers are accessed during this serial interface communication. Table V. Register Selection Table A1 A0 Register 00C ommunications Register during a Write Operation

00 Status Register during a Read Operation

11 ADC Data Register

REV. A AD7709 –15– Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H) The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica - tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first b it of the data stream. The number in brackets indicates the power-on-reset default status of that bit. Table VI. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY Ready Bit for ADC. Set when data is written to the ADC data register. The RDY bit is cleared automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result. SR6 0T his bit is autom atically cleared. SR5 0T his bit is autom atically cleared. SR4 0T his bit is autom atically cleared. SR3 ERR ADC Error Bit. This bit is set at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones. Error sources include Overrange, Underrange. Cleared by a write to the mode bits to initiate a conversion. SR2 0T his bit is autom atically cleared. SR1 STBY Standby Bit Indication. When this bit is set, the AD7709 is in power-down mode. This bit is cleared when the ADC is powered up. SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies, etc., the LOCK bit should be interrogated and the re sult discarded if the LOCK bit is 0. 7RS6 RS5 RS4 RS3 RS2 RS1 RS0 RS )0(YDR) 0(0) 0(0) 0(0) 0(RRE) 0(0) 0(YBTS) 0(KCOL

REV. A AD7709 –16– Table VII. Configuration Register Bit Designations Bit Bit Location Name Description CONFIG23 PSW2 Power Switch 2 Control Bit. Set by user to enable power switch SW2/P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. CONFIG22 PSW1 Power Switch 1 Control Bit. Set by user to enable power switch SW1/P1 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. CONFIG21 I3EN1 IEXC3 Current Source Enable Bit CONFIG20 I3EN0 IEXC3 Current Source Enable Bit CONFIG19 I2EN1 IEXC2 Current Source Enable Bit CONFIG18 I2EN0 IEXC2 Current Source Enable BitCONFIG17 I1EN1 IEXC1 Current Source Enable Bit Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H) The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register. CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that b it. A write to the Configuration Register has immediate effect and do es not reset the ADC. Therefore, if a current s ource is switched while the ADC is converting, the user will have to wait for the full settling time of the sinc3 filter before obtaining a fully settled output. This equates to three outputs. 7GIFNOC7 GIFNOC 7GIFNOC 7GIFNOC7 GIFNOC6 GIFNOC6 GIFNOC 6GIFNOC 6GIFNOC6 GIFNOC5 GIFNOC5 GIFNOC 5GIFNOC 5GIFNOC5 GIFNOC4 GIFNOC4 GIFNOC 4GIFNOC 4GIFNOC4 GIFNOC3 GIFNOC3 GIFNOC 3GIFNOC 3GIFNOC3 GIFNOC2 GIFNOC2 GIFNOC 2GIFNOC 2GIFNOC2 GIFNOC1 GIFNOC1 GIFNOC 1GIFNOC 1GIFNOC1 GIFNOC0 GIFNOC0 GIFNOC 0GIFNOC 0GIFNOC0 GIFNOC )0(LESFER) 0(LESFER )0(LESFER )0(LESFER) 0(LESFER) 0(2HC) 0(2HC )0(2HC )0(2HC) 0(2HC) 0(1HC) 0(1HC )0(1HC )0(1HC) 0(1HC) 0(0HC) 0(0HC )0(0HC )0(0HC) 0(0HC) 0(INU) 1(2NR) 1(1NR) 1(0NR 32GIFNOC3 2GIFNOC 32GIFNOC 32GIFNOC3 2GIFNOC2 2GIFNOC2 2GIFNOC 22GIFNOC 22GIFNOC2 2GIFNOC1 2GIFNOC1 2GIFNOC 12GIFNOC 12GIFNOC1 2GIFNOC0 2GIFNOC0 2GIFNOC 02GIFNOC 02GIFNOC0 2GIFNOC9 1GIFNOC9 1GIFNOC 91GIFNOC 91GIFNOC9 1GIFNOC8 1GIFNOC8 1GIFNOC 81GIFNOC 81GIFNOC8 1GIFNOC7 1GIFNOC7 1GIFNOC 71GIFNOC 71GIFNOC7 1GIFNOC6 1GIFNOC6 1GIFNOC 61GIFNOC 61GIFNOC6 1GIFNOC )0(2WSP) 0(2WSP )0(2WSP )0(2WSP) 0(2WSP) 0(1WSP) 0(1WSP )0(1WSP )0(1WSP) 0(1WSP) 0(1NE3I) 0(1NE3I )0(1NE3I )0(1NE3I) 0(1NE3I) 0(0NE3I) 0(0NE3I )0(0NE3I )0(0NE3I) 0(0NE3I) 0(1NE2I) 0(1NE2I )0(1NE2I )0(1NE2I) 0(1NE2I) 0(0NE2I) 0(0NE2I )0(0NE2I )0(0NE2I) 0(0NE2I) 0(1NE1I) 0(1NE1I )0(1NE1I )0(1NE1I) 0(1NE1I) 0(0NE1I) 0(0NE1I )0(0NE1I )0(0NE1I) 0(0NE1I I2EN1 I2EN0 Function

00 IEXC2 Current Source OFF

01 IEXC2 Current Source Routed to the IOUT1 Pin

10 IEXC2 Current Source Routed to the IOUT2 Pin

11 Reserved

00 IEXC3 Current Source OFF

01 IEXC3 Current Source Routed to the IOUT1 Pin

10 IEXC3 Current Source Routed to the IOUT2 Pin

51GIFNOC4 1GIFNOC3 1GIFNOC2 1GIFNOC1 1GIFNOC0 1GIFNOC9 GIFNOC8 GIFNOC )0(GID4P) 0(GID3P) 0(NE2P) 0(NE1P) 0(TAD4P) 0(TAD3P) 0(TAD2P) 0(TAD1P

REV. A AD7709 –17– Bit Bit Location Name Description CONFIG16 I1EN0 IEXC1 Current Source Enable Bit CONFIG15 P4DIG Digital Input Enable. Set by user to enable pin AIN4/P4 as a digital input. A weak pull-up resistor is activated in this state. Cleared by user to configure pin AIN4/P4 as an analog input. CONFIG14 P3DIG Digital Input Enable. Set by user to enable pin AIN3/P3 as a digital input. A weak pull-up resistor is activated in this state. Cleared by user to configure pin AIN3/P3 as an analog input. CONFIG13 P2EN SW2/P2 Digital Output Enable Bit. Set by user to enable P2 as a regular digital output pin. Cleared by user to three-state the P2 output. PSW2 takes precedence over P2EN. CONFIG12 P1EN SW1/P1 Digital Output Enable Bit. Set by user to enable P1 as a regular digital output pin. Cleared by user to three-state the P1 output. PSW1 takes precedence over P1EN. CONFIG11 P4DAT Digital Input Port Data Bit. P4DAT is read only and will return a zero if P4DIG equals zero. If P4 is enabled as a digital input, the readback value indicates the status of pin P4. CONFIG10 P3DAT Digital Input Port Data Bit. P3DAT is read only and will return a zero if P3DIG equals zero. If P3 is enabled as a digital input, the readback value indicates the status of pin P3. CONFIG9 P2DAT Digital Output Port Data Bit. P2 is a digital output only. When the port is active as an output (P2EN = 1), the value written to this data bit appears at the output port. Reading P2DAT will return the last value written to the P2DAT bit. CONFIG8 P1DAT Digital Output Port Data Bit. P1 is a digital output only. When the port is active as an output (P1EN = 1), the value written to this data bit appears at the output port. Reading P1DAT will return the last value written to the P1DAT bit. CONFIG7 REFSEL ADC Reference Input Select. Cleared by the user to select REFIN1(+) and REFIN1(–) as the ADC reference. Set by the user to select REFIN2(+) and REFIN2(–) as the ADC reference. CONFIG6 CH2 ADC Input Channel Selection Bit. It is used in conjunction with CH1 and CH0 as shown below. CONFIG5 CH1 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH0 as shown below. CONFIG4 CH0 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH1 as shown below. The Buffer column indicates if the analog inputs are buffered or unbuffered. This determines the common-mode input range on each input. If the input is unbuffered (AINCOM), the common-mode input includes ground. Table VII. Configuration Register Bit Designations (continued) CH2 CH1 CH0 Positive Input Negative Input Buffer 0 00 AIN1 AINCOM Positive Analog Input 0 01 AIN2 AINCOM Positive Analog Input 0 10 AIN3 AINCOM Positive Analog Input 0 11 AIN4 AINCOM Positive Analog Input 1 00 AIN1 AIN2 Positive and Negative Analog Inputs 1 01 AIN3 AIN4 Positive and Negative Analog Inputs 1 10 AINCOM AINCOM None 1 11 AIN2 AIN2 Positive and Negative Analog Inputs I1EN1 I1EN0 Function

00 IEXC1 Current Source OFF

01 IEXC1 Current Source Routed to the IOUT1 Pin

10 IEXC1 Current Source Routed to the IOUT2 Pin

REV. A AD7709 –18– Table VIII. Filter Register Bit Designations Table IX. Update Rate vs. SF WORD SF (Dec) SF (Hex) fADC (Hz) t ADC (ms) 13 0D 105.3 9.52 69 45 19.79 50.34 255 FF 5.35 186.77 Table VII. Configuration Register Bit Designations (continued) Bit Bit Location Name Description CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit. Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a code of FFFFh. Cleared by the user to enable pseudo-bipolar operation. The device uses offset binary coding, i.e., a nega- tive full-scale differential input will result in a code of 0000h, a 0 differential input will generate a code of 8000h, while a positive full-scale differential input will result in a code of FFFFh. CONFIG2 RN2 This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below. CONFIG1 RN1 This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below. CONFIG0 RN0 This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below. Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h) The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the amount of averaging performed by the sinc filter. Table VIII outlines the bit designations for the Filter Register. FR7 through FR0 indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decima- tion factor and thus the output update rate for the ADC. The Filter Register cannot be written to by the user while the ADC is active. The update rate is calculated as follows: f SF fADC MOD=¥ ¥ ¥1 where: fADC is the ADC output update rate. fMOD is the Modulator Clock Frequency = 32.768 kHz. SF is the decimal value written to the SF Register. The allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (f ADC) and time (tADC) are shown in Table IX. It should also be noted that the ADC input channel is chopped to minimize offset errors. This means that the time for a single conversion or the time to the first con- version result is 2 /H11003 t ADC. ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset = 0000h) The conversion result is stored in the ADC Data Register (DATA). This register is 16-bits wide. This is a read-only register. On completion of a read from this register, the RDY bit in the Status Register is cleared. 7RF6 RF5 RF4 RF3 RF2 RF1 RF0 RF )0(7FS) 1(6FS) 0(5FS) 0(4FS) 0(3FS) 1(2FS) 0(1FS) 1(0FS RN2 RN1 RN0 Selected ADC Input Range (V REF = 2.5 V) 00 0 ± 20 mV 00 1 ± 40 mV 01 0 ± 80 mV 01 1 ± 160 mV 10 0 ± 320 mV 10 1 ± 640 mV 11 0 ± 1.28 V 11 1 ± 2.56 V

REV. A AD7709 –20– DIGITAL INTERFACE As previously outlined, AD7709 programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All com- munications to the part must start with a write operation to the Communications Register. After power-on or reset, the device expects a write to its Communications Register. The data writ- ten to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any other register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The AD7709 serial interface consists of five signals: CS, SCLK, DIN, DOUT, and RDY. The DIN line is used for transferring data into the on-chip registers, while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The RDY line is used as a status signal to indicate when data is ready to be read from the AD7709 data register. RDY goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7709 in systems where a number of parts are connected to the serial bus. Figures 2 and 3 show timing diagrams for interfacing to the AD7709 with CS used to decode the part. Figure 3 is for a read operation from the AD7709 output shift register while Figure 2 shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though the RDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. The AD7709 serial interface can operate in 3-wire mode by tying the CS input low. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the AD7709, and the status of the RDY bit can be obtained by interr ogating the Status Register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7709 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7709 DIN line for at least 32 serial clock cycles, the serial in terface is reset. This ensures that in 3-wire systems, if the interface gets lost either via a software error or by some glitch in the system, it can be reset back to a known state. This state returns the interface to where the AD7709 is expecting a write operation to its Communications Register. This operation resets the contents of all registers to their power-on reset values. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7709 DOUT and DIN lines together and connect them to the single data line of the processor. A 10 k W pull-up resistor should be used on this single data line. In this case, if the interface gets lost, because the read and write operations share the same line, the procedure to reset it back to a known state is somewhat different than previously described. It requires a read operation of 24 serial clocks followed by a write operation where a Logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back into a known state. MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7709 flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of Figure 10 outlines the sequence that should be followed when interfacing a microcontroller or microprocessor to the AD7709. Figures 11, 12, and 13 show some typical interface circuits. The serial interface on the AD7709 is capable of operating from just three wires and is compatible with SPI interface protocols. The 3-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The serial clock input is a Schmitt-triggered input to accommodate slow edges from opto-couplers. The rise and fall tim es of other digital inputs to the AD7709 should be no longer than 1 ms. Some of the registers on the AD7709 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of microcon- trollers. The Data Register on the AD7709 is 16 bits and the Configuration Register is 24 bits, but data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7709. Even though some of the registers on the AD7709 are only 8 bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the Filter Register is to be updated, the processor must first write to the Communications Register (say- ing that the next operation is a write to the Filter Register), and then write 8 bits to the Filter Register. If required, this can all be done in a single 16-bit transfer because once the eight serial clocks of the write operation to the Communications Register have been completed, the part immediately sets itself up for a write operation to the Filter Register.

REV. A AD7709 –24– When the ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. The output code from the ADC for any analog input voltage can be represented as follows: Code AIN GAIN VN REF=¥ ¥ ¥ ()() +[] -21 024 11 /. where: AIN is the analog input voltage. GAIN in the PGA gain, i.e., 1 on the ± 2.56 V range and 128 on the ± 20 mV range. N = 16. Excitation Currents The AD7709 also contains three software configurable constant current sources. IEXC1 and IEXC2 provide 200 mA of current while IEXC3 provides 25 mA of current. All source current from VDD is directed to either the IOUT1 or IOUT2 pins of the device. These current sources are controlled via bits in the Configuration Register. The configuration bits enable the current sources, and they can be configured to source current individually to both pins or a combination of currents, i.e., 400 mA, 225 mA, or 425 mA to either of the selected output pins. These current sources can be used to excite external resistive bridge or RTD sensors. Crystal Oscillator The AD7709 is intended for use with a 32.768 kHz watch crys- tal. A PLL internally locks onto a multiple of this frequency to provide a stable 4.194304 MHz clock for the ADC. The modu- lator sample rate is the same as the crystal oscillator frequency. The start-up time associated with 32.768 kHz crystals is typically 300 ms. The OSCPD bit in the Communications Register can be used to prevent the oscillator from powering down when the AD7709 is placed in power-down mode. This avoids having to wait 300 ms after exiting power-down to start a conversion at the expense of raising the power-down current. Reference Input The AD7709 has a fully differential reference input capability for the channel. On the channel, the reference inputs can be REFIN1(+) and REFIN1(–) or REFIN2(+) and REFIN2(–). They provide a differential reference input capability. The common-mode range for these differential inputs is from GND to V DD. The reference input is unbuffered and therefore excessive R-C source impedances will introduce gain errors. The nominal reference voltage, V REF, ((REFIN1(+) – REFIN1(–) or (REFIN2(+) – REFIN2(–)), for specified operation is 2.5 V, but the AD7709 is functional with refer ence voltages from 1 V to V DD. In applications where th e excitation (voltage or current) for the trans ducer on the an alog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed because the application is ratiometric. If the AD7709 is used in a nonratiometric application, a low noise reference should be used. Recommended reference voltage sources for the AD7709 include the AD780, REF43, and REF192. It should also be noted that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources like those recommended above (e.g., AD780) will typically have low output impedances and are therefore tolerant to having decoupling capaci- tors on the REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor, as shown in Figure 18, will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit configuration. Reset Input The RESET input on the AD7709 resets all the logic, the digital filter, and the analog modulator while all on-chip registers are reset to their default state. RDY is driven high and the AD7709 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7709 operates with its default setup conditions and it is necessary to set up all registers after a RESET command. Power-Down Mode Loading 0 to the STBY bit in the ADC Communications Register places the AD7709 in device power-down mode. The AD7709 retains the contents of all its on-chip registers (including the data register) while in power-down mode. The device power-down mode does not affect the digital interface, but it does affect the status of the RDY pin. Putting the AD7709 into power-down mode will reset the RDY line high. Placing the part in power-down mode reduces the total current to 26 mA typical when the part is operated at 5 V with the oscillator running during power-down mode. With the oscillator shut down, the total IDD is 1.5 mA typical at 3 V and 6.5 mA typical at 5 V. Grounding and Layout Since the analog inputs and reference inputs on the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs, provided these noise sources do not saturate the analog modulator. As a result, the AD7709 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7709 is so high, and the noise levels from the AD7709 so low, care must be taken with regard to grounding and layout.

Figure 23. Smart Transmitter Employing the AD7709 Smart transmitters are another key design-in area for the AD7709.

REV. A AD7709 –29– 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 24 13 121

6.40 BSC

4.50 4.40 4.30 PIN 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 BSC 1.20 MAX 0.20 0.09 0.75 0.60 0.45 8/H11543 0/H11543SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AD

0.10 COPLANARITY

REV. A AD7709 –30–

Revision History

3/03—Data Sheet changed from REV. 0 to REV. A.

–31–

–32– C02700–0–3/03(A) PRINTED IN U.S.A.