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3 V/5 V, 1 mW, 2-/3-Channel,

16-Bit, Sigma-Delta ADCs AD7705/AD7706 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

AD7705: 2 fully differential input channel ADCs AD7706: 3 pseudo differential input channel ADCs 16 bits no missing codes 0.003% nonlinearity Programmable gain front end: gains from 1 to 128 3-wire serial interface SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible Schmitt-trigger input on SCLK Ability to buffer the analog input 2.7 V to 3.3 V or 4.75 V to 5.25 V operation Power dissipation 1 mW maximum @ 3 V Standby current 8 μA maximum 16-lead PDIP , 16-lead SOIC, and 16-lead TSSOP packages GENERAL DESCRIPTION The AD7705/AD7706 are complete analog front ends for low f requency measurement applications. These 2-/3-channel devices can accept low level input signals directly from a transducer and produce serial digital output. The devices employ a Σ-Δ conversion technique to realize up to 16 bits of no missing codes performance. The selected input signal is applied to a proprietary, programmable-gain front end based around an analog modulator. The modulator output is processed by an on- chip digital filter. The first notch of this digital filter can be pro- grammed via an on-chip control register, allowing adjustment of the filter cutoff and output update rate. The AD7705/AD7706 devices operate from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply. The AD7705 features two fully differential analog input channels; the AD7706 features three pseudo differential input channels. Both devices feature a differential reference input. Input signal ranges of 0 mV to 20 mV through 0 V to 2.5 V can be incorporated on both devices when operating with a V DD of 5 V and a reference of 2.5 V . They can also handle bipolar input signal ranges of ±20 mV through ±2.5 V , which are referenced to the AIN(−) inputs on the AD7705 and to the COMMON input on the AD7706. FUNCTIONAL BLOCK DIAGRAM VDD REF IN(–) REF IN(+) AD7705/AD7706 MAX PGABUFFER CHARGE BALANCING A/D CONVERTER Σ -Δ MODULATOR DIGITAL FILTER A = 1 ≈128 SERIAL INTERFACE REGISTER BANK CLOCK GENERATION MCLK IN MCLK OUT GND DRDY RESET DIN DOUT CS SCLK ANALOG INPUT CHANNELS 01166-001 Figure 1. The AD7705/AD7706 devices, with a 3 V supply and a 1.225 V reference, can handle unipolar input signal ranges of 0 mV to 10 mV through 0 V to 1.225 V . The devices can accept bipolar input ranges of ±10 mV through ±1.225 V . Therefore, the AD7705/AD7706 devices perform all signal conditioning and conversion for a 2-channel or 3-channel system. The AD7705/AD7706 are ideal for use in smart, microcontroller, or DSP-based systems. The devices feature a serial interface that can be configured for 3-wire operation. Gain settings, signal polarity, and update rate selection can be configured in software using the input serial port. The parts contains self-calibration and system calibration options to eliminate gain and offset errors on the part itself or in the system. CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to 20 μW typ. These parts are available in a 16-lead, wide body (0.3 inch), plastic dual in-line package (DIP); a 16-lead, wide body (0.3 inch), standard small outline (SOIC) package; and a low profile, 16-lead, thin shrink small outline package (TSSOP).

Rev. C | Page 2 of 44 TABLE OF CONTENTS Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1);

Rev. C | Page 3 of 44

REVISION HISTORY

5/06—Rev. B to Rev. C 6/05—Rev. A to Rev. B Changed Range of Absolute Voltage on Analog Inputs Universal 11/98—Rev. 0 to Rev. A Revision 0: Initial V ersion

Rev. C | Page 4 of 44 PRODUCT HIGHLIGHTS 1. The AD7705/AD7706 devices consume less than 1 mW at

3 V supplies and 1 MHz master clock, making them ideal

for use in low power systems. Standby current is less than 8 μA. 2. The programmable gain input allows the AD7705/AD7706 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. 3. The AD7705/AD7706 are ideal for microcontroller or DSP processor applications with a 3-wire serial interface, reducing the number of interconnect lines and reducing the number of opto-couplers required in isolated systems. 4. The parts feature excellent static performance specifications with 16 bits, no missing codes, ±0.003% accuracy, and low rms noise (<600 nV). Endpoint errors and the effects of temperature drift are eliminated by on- chip calibration options, which remove zero-scale and full- scale errors.

Rev. C | Page 5 of 44 SPECIFICATIONS VDD = 3 V or 5 V , REF IN(+) = 1.225 V with VDD = 3 V , and 2.5 V with VDD = 5 V; REF IN(−) = GND; MCLK IN = 2.4576 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter B Version 1 Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 16 Bits min Guaranteed by design, filter notch < 60 Hz Output Noise See Table 5 and Table 7 Depends on filter cutoffs and selected gain Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz, typically ±0.0003% Unipolar Offset Error3 Unipolar Offset Drift4 0.5 μV/°C typ Bipolar Zero Error3 Bipolar Zero Drift4 0.5 μV/°C typ For gains 1, 2, and 4 0.1 μV/°C typ For gains 8, 16, 32, 64, and 128 Positive Full-Scale Error3, 5 Full-Scale Drift4, 6 0.5 μV/°C typ Gain Error3, 7 Gain Drift4, 8 0.5 ppm of FSR/°C typ Bipolar Negative Full-Scale Error2 ±0.003 % of FSR typ Typically ±0.001% Bipolar Negative Full-Scale Drift4 1 μV/°C typ For gains of 1 to 4 0.6 μV/°C typ For gains of 8 to 128 ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN, unless otherwise noted Common-Mode Rejection (CMR)2 VDD = 5 V Gain = 1 96 dB typ Gain = 2 105 dB typ Gain = 4 110 dB typ Gain = 8 to 128 130 dB typ VDD = 3 V Gain = 1 105 dB typ Gain = 2 110 dB typ Gain = 4 120 dB typ Gain = 8 to 128 130 dB typ Normal-Mode 50 Hz Rejection2 98 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f NOTCH Normal-Mode 60 Hz Rejection2 98 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f NOTCH Common-Mode 50 Hz Rejection2 150 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f NOTCH Common-Mode 60 Hz Rejection2 150 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f NOTCH Absolute/Common-Mode REF IN Voltage2 GND to VDD V min to V max Absolute/Common-Mode AIN Voltage2, 9, 10 GND − 100 mV V min BUF bit of setup register = 0 V DD + 30 mV V max Absolute/Common-Mode AIN Voltage2, 9 GND + 50 mV V min BUF bit of setup register = 1 V DD − 1.5 V V max AIN DC Input Current2 1 nA max AIN Sampling Capacitance2 10 pF max AIN Differential Voltage Range11 0 to +V REF/gain12 nom Unipolar input range (B/U bit of setup register = 1) ±V REF/gain nom Bipolar input range (B/U bit of setup register = 0)

Rev. C | Page 6 of 44 Parameter B Version 1 Unit Conditions/Comments AIN Input Sampling Rate, fS Gain × f CLKIN/64 For gains of 1 to 4 f CLKIN/8 For gains of 8 to 128 Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/V max VDD = 2.7 V to 3.3 V VREF = 1.225 ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/V max VDD = 4.75 V to 5.25 V VREF = 2.5 ± 1% for specified performance REF IN Input Sampling Rate, fS f CLKIN/64 LOGIC INPUTS Input Current All Inputs, Except MCLK IN ±1 μA max Typically ±20 nA MCLK IN ±10 μA max Typically ±2 μA All Inputs, Except SCLK and MCLK IN Input Low Voltage, VINL 0.8 V max V DD = 5 V

0.4 V max V DD = 3 V

Input High Voltage, VINH 2.0 V min V DD = 3 V and 5 V SCLK Only (Schmitt-Triggered Input) V DD = 5 V nominal VT+ 1.4/3 V min/V max VT− 0.8/1.4 V min/V max VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt-Triggered Input) V DD = 3 V nominal VT+ 1/2 V min/V max VT− 0.4/1.1 V min/V max VT+ − VT− 0.375/0.8 V min/V max MCLK IN Only V DD = 5 V nominal Input Low Voltage, VINL 0.8 V max Input High Voltage, VINH 3.5 V min MCLK IN Only V DD = 3 V nominal Input Low Voltage, VINL 0.4 V max Input High Voltage, VINH 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) Output Low Voltage, VOL 0.4 V max I SINK = 800 μA, except for MCLK OUT;13 VDD = 5 V Output Low Voltage, VOL 0.4 V max I SINK = 100 μA, except for MCLK OUT;13 VDD = 3 V Output High Voltage, VOH 4 V min I SOURCE = 200 μA, except for MCLK OUT;13 VDD = 5 V Output High Voltage, VOH V DD − 0.6 V min I SOURCE = 100 μA, except for MCLK OUT;13 VDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Positive Full-Scale Limit15 (1.05 × V REF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Limit15 −(1.05 × V REF)/gain V max Gain is the selected PGA gain (1 to 128) Offset Limit15 −(1.05 × V REF)/gain V max Gain is the selected PGA gain (1 to 128) Input Span16 (0.8 × V REF)/gain V min Gain is the selected PGA gain (1 to 128) (2.1 × V REF)/gain V max Gain is the selected PGA gain (1 to 128)

Rev. C | Page 7 of 44 Parameter B Version 1 Unit Conditions/Comments POWER REQUIREMENTS VDD Voltage 2.7 to 3.3 V min to V max For specified performance Power Supply Currents17 Digital I/Ps = 0 V or V DD, external MCLK IN and CLKDIS = 1 0.32 mA max BUF bit = 0, f CLKIN = 1 MHz, gains of 1 to 128 0.6 mA max BUF bit = 1, f CLKIN = 1 MHz, gains of 1 to 128 0.4 mA max BUF bit = 0, f CLKIN = 2.4576 MHz, gains of 1 to 4 0.6 mA max BUF bit = 0, f CLKIN = 2.4576 MHz, gains of 8 to 128 0.7 mA max BUF bit = 1, f CLKIN = 2.4576 MHz, gains of 1 to 4 1.1 mA max BUF bit = 1, f CLKIN = 2.4576 MHz, gains of 8 to 128 VDD Voltage 4.75 to 5.25 V min to V max For specified performance Power Supply Currents17 Digital I/Ps = 0 V or V DD, external MCLK IN and CLKDIS = 1 0.45 mA max BUF bit = 0, f CLKIN = 1 MHz, gains of 1 to 128 0.7 mA max BUF bit = 1, f CLKIN = 1 MHz, gains of 1 to 128 0.6 mA max BUF bit = 0, f CLKIN = 2.4576 MHz, gains of 1 to 4 0.85 mA max BUF bit = 0, f CLKIN = 2.4576 MHz, gains of 8 to 128 0.9 mA max BUF bit = 1, f CLKIN = 2.4576 MHz, gains of 1 to 4 1.3 mA max BUF bit = 1, f CLKIN = 2.4576 MHz, gains of 8 to 128 Standby (Power-Down) Current18 16 μA max External MCLK IN = 0 V or V DD, VDD = 5 V, see Figure 12 8 μA max External MCLK IN = 0 V or V DD, VDD = 3 V Power Supply Rejection19, 20 dB typ 1 Temperature range is −40°C to +85°C. 2 These numbers are established from characterization or design data at initial product release. 3 A calibration is effectively a conversion; therefore, these errors are of the order of the conversion noise shown in Table 5 and Table 7. This applies after calibration at the temperature of interest. 4 Recalibration at any temperature removes these drift errors. 5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 7 Gain error does not include zero-scale errors. It is calculated as (full-scale error – unipolar offset error) for unipolar ranges and (full-scale error - bipolar zero error) for bipolar ranges. 8 Gain drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if only zero-scale calibrations are performed. 9 This common-mode voltage range is allowed, provided that the input voltage on analog inputs is not more positive than VDD + 30 mV or more negative than GND − 100 mV. Parts are functional with voltages down to GND − 200 mV, but with increased leakage at high temperatures. 10 The AD7705/AD7706 can tolerate absolute analog input voltages down to GND − 200 mV, but the leakage current increases. 11 The analog input voltage range on AIN(+) is given with respect to the voltage on AIN(−) on the AD7705, and with respect to the voltage of the COMMON input on the AD7706. The absolute voltage on the analog inputs should not be more positive than VDD + 30 mV, or more negative than GND − 100 mV for specified performance. Input voltages of GND − 200 mV can be accommodated, but with increased leakage at high temperatures. 12 VREF = REFIN(+) − REFIN(−). 13 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 14 Sample tested at 25°C to ensure compliance. 15 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. 16 These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed VDD + 30 mV or go more negative than GND − 100 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 17 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the VDD current and power dissipation varies depending on the crystal or resonator type (see Clocking and Oscillator Circuit section). 18 If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode, and the power dissipation depends on the crystal or resonator type (see Standby Mode section). 19 Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB, with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB, with filter notches of 20 Hz or 60 Hz.

20 PSRR depends on both gain and VDD, as follows:

VDD = 3 V 86 78 85 93 VDD = 5 V 90 78 84 91

VDD = 2.7 V to 5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V , Logic 1 = VDD, unless otherwise noted. Table 2. Timing Characteristics1, 2

2.5 MHz max For specified performance

1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 19 and Figure 20. higher current than specified, and possibly become uncalibrated. 4 The AD7705/AD7706 are production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. relinquish times of the part and as such are independent of external bus loading capacitances. taken that subsequent reads do not occur close to the next output update. Figure 2. Load Circuit for Access Time and Bus Relinquish Time

Rev. C | Page 9 of 44 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameters Ratings VDD to GND −0.3 V to +7 V Analog Input Voltage to GND −0.3 V to V DD + 0.3 V Reference Input Voltage to GND −0.3 V to V DD + 0.3 V Digital Input Voltage to GND −0.3 V to V DD + 0.3 V Digital Output Voltage to GND −0.3 V to V DD + 0.3 V Operating Temperature Range Commercial (B Version) −40°C to + 85°C Storage Temperature Range −65°C to + 150°C Junction Temperature 150°C θJA Thermal Impedance 105°C/W Lead Temperature (Soldering, 10 sec) 260°C θJA Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C θJA Thermal Impedance 139°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD Rating >4000 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 11 of 44 Mnemonic Pin No. AD7705 AD7706 Description 14 DIN DIN Serial Data Input. Serial data is written to the input shift register on the part. Data from the input shift register is transferred to the setup register, clock register, or communication register, depending on the register selection bits of the communication register. 15 V DD V DD Supply Voltage. 2.7 V to 5.25 V operation. 16 GND GND Ground Reference Point for the AD7705/AD7706 Internal Circuitry.

the bipolar input ranges with a VREF of 2.5 V and VDD = 5 V . selectable notch and −3 dB frequencies for the parts. the clock register set to 0. Table 5. Output RMS Noise vs. Gain and Output Update Rate @ 5 V Table 6. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V

500 Hz 131 Hz 10 10 10 10 10 10 10 10

the bipolar input ranges with a VREF of 1.225 V and a VDD = 3 V . selectable notch and −3 dB frequencies for the parts. the clock register set to 0. Table 7. Output RMS Noise vs. Gain and Output Update Rate @ 3 V Table 8. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V

reading from the communication register. more detail in the following sections. Table 9. Communication Register Table 10. Communication Register Bit Description serial interface communication. next operation to the selected register, and a 1 indicates a read operation from the selected register. this bit places the parts in normal operating mode. Table 12. Following a calibration on a channel, three pairs of calibration registers store the calibration coefficients. Table 12 (for the AD7705) and Table 13 (for the AD7706) show which channel combinations have independent calibration coefficients. within the allowable common-mode range for the parts.

Table 11. Register Selection Table 12. Channel Selection for AD7705 Table 13. Channel Selection for AD7706 The setup register is an 8-bit register from which data can be read or to which data can be written. Table 14 outlines the bit designations for the setup register. Table 14. Setup Register Table 15. Setup Register Description MD1, MD0 ADC Mode Bits. These bits select the operational mode of the ADC as outlined in Table 16. G2 to G0 Gain Selection Bits. These bits select th e gain setting for the on-chip PGA, as outlined in Table 17. B/U Bipolar/Unipolar Operation. A 0 in this bit selects bipolar operation; a 1 in this bit selects unipolar operation. to handle higher source impedances. interface and does not reset the DRDY output if it is low.

Table 16. Operating Mode Options 0 0 Normal Mode. In this mode, the device performs normal conversions. generated VREF/selected gain. end of the calibration, the part returns to normal mode, with both MD1 and MD0 returning to 0. Table 17. Gain Selection

The clock register is an 8-bit register from which data can be read or to which data can be written. Table 18 outlines the bit designations for the clock register. Table 18. Clock Register Table 19. Clock Register Description unspecified operation of the device. are stopped, and no conversions take place when the CLKDIS bit is active. Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used internally by the part. Table 20. Output Update Rates 1 Assumes correct clock frequency on MCLK IN pin with the CLKDIV bit set appropriately.

written to the part will be ignored by the AD7705/AD7706. and will not operate correctly. MD0, to return to 0 represents the duration of the calibration. tCLKIN. The time for both methods is shown in Table 21. Table 21. Calibration Sequences

at a rate determined by the first notch frequency of this filter. periodically at any rate up to the output register update rate.

50 Hz to 500 Hz; therefore, the programmable range for the

range for the −3 dB frequency of 5.24 Hz to 52.4 Hz. Figure 13. AD7705 Basic Connection Diagram

which are referenced to the COMMON input. input voltage lies between GND − 100 mV and VDD + 30 mV . otherwise, there is a degradation in linearity performance. AIN(+) and discharged to AIN(−) every input sample cycle. The effective on resistance of the switch, RSW, is typically 7 kΩ. from the pins and lead frame of the devices. Figure 14. Unbuffered Analog Input Structure Table 22. External Resistance-Capacitance Combination for impedance, but not in a gain error. and a scaling of the ratio of reference capacitor to input capacitor. and fS is the input sample rate. Table 23. Input Sampling Frequency vs. Gain

Rev. C | Page 23 of 44 On the AD7706, the voltages applied to the analog input channels are referenced to the COMMON input. For example, if AIN1(−) is 2.5 V and AD7705 is configured for unipolar operation with a gain of 2 and a V REF of 2.5 V , the input voltage range on the AIN1(+) input is 2.5 V to 3.75 V . If AIN1(−) is 2.5 V and AD7705 is configured for bipolar mode with a gain of 2 and a VREF of 2.5 V , the analog input range on AIN1(−) is at GND, the part cannot be configured for bipolar ranges in excess of ±100 mV . Bipolar or unipolar options are chosen by programming the B/U bit of the setup register. This programs the channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change the input signal conditioning, it simply changes the data output coding and the points on the transfer function where calibrations occur. REFERENCE INPUT The AD7705/AD7706 reference inputs, REF IN(+) and REF IN(−), provide a differential reference input capability. The common- mode range for these differential inputs is from GND to VDD. The nominal reference voltage, VREF (REF IN(+) − REF IN(−)), for specified operation is 2.5 V for the AD7705/AD7706 operated with a VDD of 5 V , and 1.225 V for the AD7705/AD7706 operated with a VDD of 3 V . The parts are functional with VREF voltages down to 1 V , but performance will be degraded because the output noise, in terms of LSB size, is larger. REF IN(+) must be greater than REF IN(−) for correct operation of the AD7705/AD7706. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ±1 nA over temperature, and source resistance might result in gain errors on the part. In this case, the sampling switch resistance is 5 kΩ typ, and the reference capacitor, C REF, varies with gain. The sample rate on the reference inputs is fCLKIN/64 and does not vary with gain. For gains of 1 and 2, CREF is 8 pF; for gains of 16, 32, 64, and 128, it is 5.5 pF, 4.25 pF, 3.625 pF, and 3.3125 pF, respectively. The output noise performance outlined in Table 5, Table 6, Table 7, and Table 8 is for an analog input of 0 V , which effectively removes the effect of noise on the reference. To obtain the noise performance shown in the noise tables over the full input range requires a low noise reference source for the AD7705/AD7706. If the reference noise in the bandwidth of interest is excessive, it degrades the performance of the AD7705/AD7706. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage is removed because the application is ratiometric. Recommended reference voltage sources for the AD7705/ AD7706 with a V DD of 5 V include the AD780, REF43, and REF192; the recommended reference sources for the AD7705/ AD7706 operated with a VDD of 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references to reduce the noise level further. DIGITAL FILTERING The AD7705/AD7706 each contain an on-chip, low-pass digital filter that processes the output of the Σ-Δ modulator. Therefore, the parts not only provide the ADC function, but also provide a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain, rather than in the analog domain. For example, because it occurs after the A/D conversion process, digital filtering can remove noise injected during the conversion process, whereas analog filtering cannot do this. In addition, the digital filter can be made programmable far more readily than the analog filter. Depending on the digital filter design, this provides the user with the update rate. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. T o alleviate this problem, the AD7705/AD7706 have overrange headroom built into the Σ-Δ modulator and digital filter that allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consider filtering the analog input, or reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This provides an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenuated bands occur around multiples of the sampling frequency, f S, as defined in Table 23. Thus, the unattenuated bands occur at n × fS (where n = 1, 2, 3 . . .). At these frequencies, there are frequency bands ±f3 dB wide (f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output.

Rev. C | Page 25 of 44 ANALOG FILTERING The digital filter does not provide any rejection at integer multiples of the modulator sample frequency, as outlined earlier. However, due to the part’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. Therefore, the analog filtering requirements in front of the AD7705/AD7706 are considerably reduced vs. a conventional converter without on-chip filtering. In addition, because the parts’ common-mode rejection performance of 100 dB extends to several kHz, common-mode noise in this frequency range is substantially reduced. Depending on the application, however, it might be necessary to provide attenuation of the signal before it reaches the AD7705/ AD7706 to eliminate unwanted frequencies that can pass through the digital filter. It might also be necessary to provide analog filtering in front of the AD7705/AD7706 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7705/ AD7706 in unbuffered mode, care must be taken to ensure that the source impedance is low enough not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering, which can be provided in front of the AD7705/AD7706 when the parts are used in unbuffered mode. However, when the parts are used in buffered mode, large source impedances result in a small dc offset error (a 10 kΩ source resistance causes an offset error of less than 10 μV). Therefore, if the system requires significant source impedances to provide passive analog filtering in front of the AD7705/AD7706, it is recommended to operate the part in buffered mode. CALIBRATION The AD7705/AD7706 provide a number of calibration options that can be programmed via the MD1 and MD0 bits of the setup register. The different calibration options are outlined in the Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01 Hex, and Calibration Sequences sections. A calibration cycle can be initiated at any time by writing to these bits of the setup register. Calibration on the AD7705/AD7706 removes offset and gain errors from the devices. A calibration routine should be initiated on these devices whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch, or bipolar/unipolar input range. The AD7705/AD7706 offer self-calibration and system calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two input conditions: zero-scale point and full-scale point. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration is only as good as the noise level that it provides in normal mode. The result of the zero-scale calibration conversion is stored in the zero-scale calibration register, and the result of the full-scale calibration conversion is stored in the full-scale calibration register. With these readings, the microcontroller can calculate the offset and the gain slope for the input-to-output transfer function of the converter. Internally, the part works with a resolution of 33 bits to determine the conversion result of 16 bits. Self-Calibration A self-calibration is initiated on the AD7705/AD7706 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the setup register. In self-calibration mode with a unipolar input range, the zero-scale point used to determine the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., AIN(+) = AIN(−) = internal bias voltage on the AD7705, and AIN = COMMON = internal bias voltage on the AD7706). The PGA is set for the selected gain for this zero-scale calibration conversion, as per the G1 and G0 bits in the communication register. The full-scale calibration conversion is performed at the selected gain on an internally generated voltage of V REF/selected gain. The duration time for the calibration is 6 × 1/output rate. This is composed of 3 × 1/output rate for the zero-scale calibration and 3 × 1/output rate for the full-scale calibration. Then, the MD1 and MD0 bits in the setup register return to 0, 0. This provides the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/output rate. This is composed of 3 × 1/output rate for the zero-scale calibration, 3 × 1/output rate for the full-scale calibration, 3 × 1/output rate for a conversion on the analog input, and some overhead to set up the coeffi- cients correctly. If DRDY is low before (or goes low during) writing the calibration command to the setup register, it can take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that a calibration is in progress. Therefore, DRDY should be ignored for one modulator cycle after the last bit is written to the setup register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that outlined in the previous paragraph. In this case, the two points are the same as above, but the shorted inputs point is midscale of the transfer function because the part is configured for bipolar operation. System Calibration System calibration allows the AD7705/AD7706 to compensate for system gain and offset errors, as well as their own internal errors. System calibration performs the same slope factor calculations as self-calibration, but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. Full system calibration requires a two-step process, a zero-scale system calibration followed by a full-scale system calibration.

Rev. C | Page 26 of 44 For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the zero-scale voltage is set up, a zero-scale system calibration is initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the setup register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. Then, Bit MD1 and Bit MD0 in the setup register return to 0, 0, providing the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and returns low when there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate, because the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) writing the calibration command to the setup register, it can take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that a calibration is in progress. Therefore, DRDY should be ignored for one modulator cycle after the last bit is written to the setup register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to AIN, and the second step of the calibration process is initiated by writing the appropriate values (1, 1) to MD1 and MD0. The full-scale voltage must be set up before the calibration is initiated and must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. Then, the MD1 and MD0 bits in the setup register return to 0, 0, providing the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and returns low when there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate, because the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) writing the calibration command to the setup register, it can take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for one modulator cycle after the last bit is written to the setup register in the calibration command. In unipolar mode, the system calibration is performed between the two endpoints of the transfer function. In bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. The fact that the system calibration involves two steps offers another feature. After the sequence of a full system calibration is complete, additional offset or gain calibrations can be performed individually to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, does not affect the other parameter. When the part is used in unbuffered mode, system calibration can be used to remove errors from source impedances on the analog input. A simple R-C antialiasing filter on the front end can introduce a gain error on the analog input voltage, but the system calibration can be used to remove this error. Span and Offset Limits Whenever the system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The overriding requirement for determining the amount of offset and gain that can be accommodated by the part is that the positive full-scale calibration limit is < 1.05 × VREF/gain. This allows the input range to go 5% above the nominal range. The built-in headroom in the AD7705/AD7706 analog modulator ensures that the parts operate correctly with a positive full-scale voltage that is 5% beyond the nominal. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/gain and a maximum value of 2.1 × VREF/gain. However, when determining the span, which is the difference between the bottom and top of the devices’ input range, the user must take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is used, and the user must also take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative offsets with respect to AIN(−) on the AD7705, and with respect to COMMON on the AD7706. In both unipolar and bipolar modes, the range of positive offsets that can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user must ensure that the offset range plus the span range does not exceed 1.05 × V REF/gain. If the part is used in unipolar mode with a required span of 0.8 × VREF/gain, the offset range that the system calibration can handle is –1.05 × VREF/gain to +0.25 × VREF/gain. If the part is used in unipolar mode with a required span of VREF/gain, the offset range that the system calibration can handle is −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2 × V REF/gain, the maximum span range that the system calibration can handle is 0.85 × VREF/gain.

the MCLK IN pin with the MCLK OUT pin left unconnected. time are directly related to the master clock frequency, fCLKIN. current drawn by the analog circuitry. Figure 17. Crystal/Resonator Connection for the AD7705/AD7706 the current taken by the oscillator circuit. CMOS buffer before being applied to the rest of the circuit.

Rev. C | Page 29 of 44 The FSYNC input can also be used as a software start convert command, allowing the AD7705/AD7706 to be operated in a conventional converter fashion. In this mode, writing to the FSYNC bit starts conversion, and the falling edge of DRDY indicates when conversion is complete. The disadvantage of this scheme is that the settling time of the filter must be taken into account for every data register update; therefore, the rate at which the data register is updated is three times slower in this mode. Because the FSYNC bit resets the digital filter, the full settling time of 3 × 1/output rate must elapse before a new word is loaded to the output register. If the DRDY signal is low when FSYNC goes to 0, the DRDY signal is not reset to high by the FSYNC command, because the AD7705/AD7706 recognize that there is a word in the data register that has not been read. The DRDY line stays low until an update of the data register takes place, at which time it goes high for 500 × tCLKIN before returning low again. A read from the data register resets the DRDY signal high, and it does not return low until the settling time of the filter has elapsed and there is a valid new word in the data register. If the DRDY line is high when the FSYNC command is issued, the DRDY line does not return low until the settling time of the filter has elapsed. RESET INPUT The RESET input on the AD7705/AD7706 resets the logic, digital filter, analog modulator, and on-chip registers to their default states. DRDY is driven high, and the AD7705/AD7706 ignore all communication to their registers while the RESET input is low. When the RESET input returns high, the AD7705/AD7706 start to process data, and DRDY returns low in 3 × 1/output rate, indicating a valid new word in the data register. However, the AD7705/AD7706 operate with their default setup conditions after a reset, and it is generally necessary to set up all registers and perform a calibration after a RESET command. The AD7705/AD7706 on-chip oscillator circuit continues to function even when the RESET input is low, and the master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7705/AD7706 clock, the AD7705/AD7706 produce an uninterrupted master clock during a RESET command. STANDBY MODE The STBY bit in the communication register of the AD7705/ AD7706 allows the user to place the part in a power-down mode when it is not required to provide conversion results. The AD7705/AD7706 retain the contents of their on-chip registers, including the data register, while in standby mode. When released from standby mode, the parts start to process data, and a new word is available in the data register in 3 × 1/output rate from when a 0 is written to the STBY bit. The STBY bit does not affect the digital interface, nor does it affect the status of the DRDY line. If DRDY is high when the STBY bit is brought low, it remains high until there is a valid new word in the data register. If DRDY is low when the STBY bit is brought low, it remains low until the data register is updated, at which time the DRDY line returns high for 500 × tCLKIN before returning low again. If DRDY is low when the part enters standby mode, indicating a valid unread word in the data register, the data register can be read while the part is in standby. At the end of this read operation, DRDY is reset to high. Placing the part in standby mode reduces the total current to 9 μA typical with VDD = 5 V , and 4 μA with VDD = 3 V when the part is operated from an external master clock, provided that this master clock has stopped. If the external clock continues to run in standby mode, the standby current increases to 150 μA typical with 5 V supplies, and 75 μA typical with 3.3 V supplies. If a crystal or ceramic resonator is used as the clock source, the total current in standby mode is 400 μA typical with 5 V supplies, and 90 μA with 3.3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in standby mode. This is important in applications where the system clock is provided by the AD7705/AD7706 clock so that the AD7705/AD7706 produce an uninterrupted master clock in standby mode. ACCURACY Σ-Δ ADCs, like VFCs and other integrating ADCs, do not contain a source of nonmonotonicity and inherently offer no missing codes performance. The AD7705/AD7706 achieve excellent linearity by using high quality, on-chip capacitors that have a very low capacitance/voltage coefficient. The devices also achieve low input drift by using chopper-stabilization techniques in their input stage. To ensure excellent performance over time and temperature, the AD7705/AD7706 use digital calibration techniques that minimize offset and gain error. DRIFT CONSIDERATIONS The AD7705/AD7706 use chopper-stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc-leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain. Gain drift within the converter primarily depends on the temperature tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter. Using the system calibration mode also minimizes offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes.

digital circuitry, the AD7705/AD7706 should be powered up first. current. The latch-up current is greater than 100 mA. 25°C. The AD7705/AD7706 are operated in unbuffered mode. Figure 18. IDD vs. Supply Voltage except at integer multiples of the modulator sampling frequency. facilitates the use of ground planes that can be separated easily. as possible to the AD7705/AD7706 GND. and signals are placed on the solder side.

Rev. C | Page 31 of 44 EVALUATING THE PERFORMANCE The recommended layout for the AD7705/AD7706 is outlined in their associated evaluations. Each evaluation board package includes a fully assembled and tested evaluation board, documentation, software for controlling the board over the printer port of a PC, and software for analyzing its performance on a PC. Noise levels in the signals applied to the AD7705/AD7706 can also affect performance of the parts. The AD7705/AD7706 software evaluation packages allow the user to evaluate the true performance of the parts independently of the analog input signals. For the AD7705, the scheme involves using a test mode with the inputs internally shorted together to provide a zero differential voltage for the analog modulator. External to the AD7705, the AIN1(−) input should be connected to a voltage that is within the allowable common-mode range of the part. Similarly, on the AD7706 for evaluation purposes, the COMMON input should be connected to a voltage within its allowable common-mode range. This scheme should be used after a calibration is performed on the parts. DIGITAL INTERFACE As previously outlined, the AD7705/AD7706 programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the serial interface, which also provides read access to the on-chip registers. All communication to the parts must start with a write operation to the communication register. After a power-on or reset, the devices expect a write to their communication registers. The data written to these registers determine whether the next operation is a read or write operation and to which register this operation occurs. Therefore, write access to a register on either part starts with a write operation to the communication register, followed by a write to the selected register. Likewise, a read operation from any register, including the output data register, starts with a write operation to the communication register, followed by a read operation from the selected register. The AD7705/AD7706 serial interfaces each consist of five signals: CS , SCLK, DIN, DOUT, and DRDY. The DIN line is used for transferring data into the on-chip registers, and the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers on either DIN or DOUT take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the AD7705/AD7706 data registers. DRDY goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to updating the output register, indicating not to read from the device, to ensure that a data read is not attempted while the register is updated. CS is used to select the device. It can be used to decode the AD7705/AD7706 in systems where a number of parts are connected to the serial bus. Figure 19 and Figure 20 show timing diagrams for interfacing to the AD7705/AD7706, with CS used to decode the parts. Figure 19 shows a read operation from the AD7705/AD7706 output shift register, and Figure 20 shows a write operation to the input shift register. It is possible to read the same data twice from the output register, even though the DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operation is complete before the next output update takes place. The AD7705/AD7706 serial interface can operate in 3-wire mode by tying the CS input low. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the AD7705/ AD7706, and the status of DRDY can be obtained by interrogating the MSB of the communication register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7705/AD7706 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS, because CS normally occurs after the falling edge of SCLK in DSP interfaces. The SCLK can continue to run between data transfers, provided that the timing numbers are obeyed. The serial interface can be reset by exercising the RESET input. It can also be reset by writing a series of 1s on the DIN input. If Logic 1 is written to the AD7705/AD7706 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, if the interface is lost via either a software error or a glitch in the system, it can be reset to a known state. This state returns the interface to where the AD7705/AD7706 are expecting a write operation to their communication registers. This operation in itself does not reset the contents of any registers, but it is advisable to set up all registers again, because the information written to the registers is unknown due to the interface being lost. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7705/AD7706 DATA OUT and DATA IN lines together and connect them to the single data line of the processor. A 10 kΩ pull-up resistor should be used on this single data line. In this case, if the interface is lost, the procedure to reset it back to a known state is somewhat different than previously described because the read and write operations share the same line. Instead, a read operation of 24 serial clocks is required, followed by a write operation where Logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface resets to a known state.

Rev. C | Page 36 of 44 C Code for Interfacing AD7705 to 68HC11 #include <math.h> #include <io6811.h> #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main() /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg(0x20); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the clock register */ Writetoreg(0x0C); /* master clock enabled, 4.9512MHz Clock, set output rate to 50Hz*/ Writetoreg(0x10); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the setup register */ Writetoreg(0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/ while(PORTC & 0x10); /* wait for /DRDY to go low */ for(a=0;a<NUM_SAMPLES;a++); Writetoreg(0x38); /*set the next operation for 16 bit read from the data register */ Read(NUM_SAMPES,2); Writetoreg(int byteword); int q; SPCR = 0x3f; SPCR = 0X7f; /* this sets the WiredOR mode(DWOM=1), Master mode(MSTR=1), SCK idles high(CPOL=1), /SS can be low always (CPHA=1), lowest clock speed(slowest speed which is master clock /32 */ DDRD = 0x18; /* SCK, MOSI outputs */ q = SPSR; q = SPDR; /* the read of the status register and of the data register is needed to clear the interrupt which tells the user that the data transfer is complete */ PORTC &= 0xfb; /* /CS is low */ SPDR = byteword; /* put the byte into data register */ while(!(SPSR & 0x80)); /* wait for /DRDY to go low */ PORTC |= 0x4; /* /CS high */ Read(int amount, int reglength)

Rev. C | Page 37 of 44 int q; SPCR = 0x3f; SPCR = 0x7f; /* clear the interrupt */ DDRD = 0x10; /* MOSI output, MISO input, SCK output */ while(PORTC & 0x10); /* wait for /DRDY to go low */ PORTC & 0xfb ; /* /CS is low */ for(b=0;b<reglength;b++) SPDR = 0; while(!(SPSR & 0x80)); /* wait until port ready before reading */ *datapointer++=SPDR; /* read SPDR into store array via datapointer */ PORTC|=4; /* /CS is high */

variable is used to correct that of the primary channel.

  • PID
  • RANGE SETTING
  • CALIBRATION
  • LINEARIZATION
  • OUTPUT CONTROL
  • SERIAL COMMUNICATION
  • HART PROTOCOL VCC COM VCC BOOST REF OUT1 REF OUT2 REF IN AD421 C1 C2 C3 COM LOOP RTN COMP DRIVE 4.7μF 0.01μF 0.1μF2.2μF DN25D 1kΩ 1000pF 0.01μF 0.01μF 0.0033μF ISOLATION BARRIER SENSORS RTD mV Ω TC MAIN TRANSMITTER ASSEMBLY 4mA TO 20mA 01166-028

Figure 28. Smart Transmitter Using the AD7705

Rev. C | Page 43 of 44 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7705BN −40°C to +85°C 16-Lead PDIP N-16 AD7705BNZ1 −40°C to +85°C 16-Lead PDIP N-16 AD7705BR −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BR-REEL −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BR-REEL7 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BRZ1 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BRZ-REEL1 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BRZ-REEL71 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7705BRU −40°C to +85°C 16-Lead TSSOP RU-16 AD7705BRU-REEL −40°C to +85°C 16-Lead TSSOP RU-16 AD7705BRU-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16 AD7705BRUZ1 −40°C to +85°C 16-Lead TSSOP RU-16 AD7705BRUZ-REEL1 −40°C to +85°C 16-Lead TSSOP RU-16 AD7705BRUZ-REEL71 −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BN −40°C to +85°C 16-Lead PDIP N-16 AD7706BNZ1 −40°C to +85°C 16-Lead PDIP N-16 AD7706BR −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BR-REEL −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BR-REEL7 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BRZ1 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BRZ-REEL1 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BRZ-REEL71 −40°C to +85°C 16-Lead SOIC_W RW-16 AD7706BRU −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BRU-REEL −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BRU-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BRUZ1 −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BRUZ-REEL1 −40°C to +85°C 16-Lead TSSOP RU-16 AD7706BRUZ-REEL71 −40°C to +85°C 16-Lead TSSOP RU-16 EVAL-AD7705EB Evaluation Board EVAL-AD7706EB Evaluation Board 1 Z = Pb-free part.

Rev. C | Page 44 of 44 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. C01166-0-5/06(C)