AD7703 AD | Alldatasheet
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REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC2MOS 20-Bit A/D Converter AD7703 © Analog Devices, Inc., 1996 Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
0.0003% Linearity Error 20-Bit No Missed Codes On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 to +2.5 V or +2.5 V Analog Input Range 4 kSPS Output Data Rate Flexible Serial Interface Ultralow Power
APPLICATIONS
Industrial Process Control Weigh Scales Portable Instrumentation Remote Data Acquisition FUNCTIONAL BLOCK DIAGRAM 5DGND AV DD DV DD AV SS DV SS SC1 SC2 7 64 17 AGND A IN VREF 10 CALIBRATION SRAM CALIBRATION MICROCONTROLLER CAL BP/UP SLEEP CLOCK GENERATOR SERIAL INTERFACE LOGIC SDATA SCLK 3 2 1 16 18 CLKIN CLKOUT MODE CS DRDY AD7703 ANALOG MODULATOR 6-POLE GAUSSIAN LOW-PASS DIGITAL FILTER 20-BIT CHARGE BALANCE A/D CONVERTER PRODUCT HIGHLIGHTS 1. The AD7703 offers 20-bit resolution coupled with outstanding 0.0003% accuracy. 2. No missing codes ensures true, usable, 20-bit dynamic range, removing the need for programmable gain and level-setting circuitry. 3. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero and gain error. External circuits can also be included in the calibration loop to remove system offsets and gain errors. 4. A flexible synchronization allows the AD7703 to interface directly to the serial ports of industry standard microcontrollers and DSP processors. 5. Low operating power consumption and an ultralow power standby mode make the AD7703 ideal for loop powered remote sensing applications, or battery-powered portable instruments. GENERAL DESCRIPTION The AD7703 is a 20-bit ADC which uses a sigma delta conver- sion technique. The analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. The modulator output is processed by an on-chip digital filter with a six-pole Gaussian response, which updates the output data register with 20-bit binary words at word rates up to 4 kHz. The sampling rate, filter corner fre- quency and output word rate are set by a master clock input that may be supplied externally, or by an on-chip gate oscillator. The inherent linearity of the ADC is excellent, and endpoint accuracy is ensured by self-calibration of zero and full scale which may be initiated at any time. The self-calibration scheme can also be extended to null system offset and gain errors in the input channel. The output data is accessed through a serial port, which has two synchronous modes suitable for interfacing to shift registers or the serial ports of industry standard microcontrollers. CMOS construction ensures low power dissipation, and a power down mode reduces the idle power consumption to only 10 mW.
REV. D–2– AD7703–SPECIFICATIONS Parameter A/S Versions 2 B Version2 C Version2 Units Test Conditions/Comments STATIC PERFORMANCE Resolution 20 20 20 Bits Integral Nonlinearity, T MIN to TMAX ± 0.0015 ± 0.0007 ± 0.0003 % FSR typ +25°C ± 0.003 ± 0.0015 ± 0.0008 % FSR max TMIN to TMAX ± 0.003 ± 0.0015 ± 0.0012 % FSR max Differential Nonlinearity, TMIN to TMAX ± 0.5 ± 0.5 ± 0.5 LSB typ Guaranteed No Missing Codes Positive Full-Scale Error 3 ± 4 ± 4 ± 4 LSB typ ± 16 ± 16 ± 16 LSB max Full-Scale Drift 4 ± 19/± 37 ± 19 ± 19 LSB typ Unipolar Offset Error 3 ± 4 ± 4 ± 4 LSB typ ± 16 ± 16 ± 16 LSB max Unipolar Offset Drift 4 ± 26 ± 26 ± 26 LSB typ Temp Range: 0 °C to +70°C ± 67 +48/–400 ± 67 ± 67 LSB typ Specified Temp Range Bipolar Zero Error 3 ± 4 ± 4 ± 4 LSB typ ± 16 ± 16 ± 16 LSB max Bipolar Zero Drift 4 ± 13 ± 13 ± 13 LSB typ Temp Range: 0 °C to +70°C ± 34 +24/–200 ± 34 ± 34 LSB typ Specified Temp Range Bipolar Negative Full-Scale Errors 3 ± 8 ± 8 ± 8 LSB typ ± 32 ± 32 ± 32 LSB max Bipolar Negative Full-Scale Drift 4 ± 10/± 20 ± 10 ± 10 LSB typ Noise (Referred to Output) 1.6 1.6 1.6 LSB rms typ DYNAMIC PERFORMANCE Sampling Frequency, f S fCLKIN/256 f CLKIN/256 f CLKIN/256 Hz Output Update Rate, f OUT fCLKIN/1024 f CLKIN/1024 f CLKIN/1024 Hz Filter Corner Frequency, f –3 dB fCLKIN/409,600 f CLKIN/409,600 f CLKIN/409,600 Hz Settling Time to ± 0.0007% FS 507904/f CLKIN 507904/fCLKIN 507904/fCLKIN sec For Full-Scale Input Step SYSTEM CALIBRATION Positive Full-Scale Calibration Range V REF + 0.1 V REF + 0.1 V REF + 0.1 V max System Calibration Applies to Positive Full-Scale Overrange V REF + 0.1 V REF + 0.1 V REF + 0.1 V max Unipolar and Bipolar Ranges. Negative Full-Scale Overrange –(V REF + 0.1) –(V REF + 0.1) –(V REF + 0.1) V max After Calibration, if A IN > VREF, Maximum Offset Calibration Ranges 5, 6 the Device Will Output All 1s. Unipolar Input Range –(V REF + 0.1) –(V REF + 0.1) –(V REF + 0.1) V max If A IN < 0 (Unipolar) or –V REF Input Span 7 0.8 VREF 0.8 VREF 0.8 VREF V min Output all 0s 2 VREF + 0.2 2 V REF + 0.2 2 V REF + 0.2 V max ANALOG INPUT Unipolar Input Range 0 to +2.5 0 to +2.5 0 to +2.5 Volts Bipolar Input Range ± 2.5 ± 2.5 ± 2.5 Volts Input Capacitance 20 20 20 pF typ Input Bias Current 1 1 1 1 nA typ LOGIC INPUTS All Inputs except CLKIN VINL, Input Low Voltage 0.8 0.8 0.8 V max VINH, Input High Voltage 2.0 2.0 2.0 V min CLKIN VINL, Input Low Voltage 0.8 0.8 0.8 V max VINH, Input High Voltage 3.5 3.5 3.5 V min IIN, Input Current 10 10 10 µA max LOGIC OUTPUTS VOL, Output Low Voltage 0.4 0.4 0.4 V max I SINK = 1.6 mA VOH, Output High Voltage DV DD –1 DV DD –1 DV DD –1 V min I SOURCE = 100 µA Floating State Leakage Current ± 10 ± 10 ± 10 µA max Floating State Output Capacitance 9 9 9 pF typ POWER REQUIREMENTS Power Supply Voltages Digital Positive Supply (DV DD) 4.5/AV DD 4.5/AVDD 4.5/AVDD V min/V max Calibration Memory Retention Power Supply Voltage 2.0 2.0 2.0 V min (TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; V REF = +2.5 V; fCLKIN = 4.096 MHz; BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 k V1 with 1 nF to AGND at A IN unless otherwise noted.)
Parameter A/S Versions 2 B Version2 C Version2 Units Test Conditions/Comments STATIC PERFORMANCE DC Power Supply Currents 8 Analog Positive Supply (AI DD) 3.2 3.2 3.2 mA max Typically 2 mA Digital Positive Supply (DI DD) 1.5 1.5 1.5 mA max Typically 1 mA Analog Negative Supply (AI SS) 3.2 3.2 3.2 mA max Typically 2 mA Digital Negative Supply (DI SS) 0.1 0.1 0.1 mA max Typically 0.03 mA Power Supply Rejection 9 Positive Supplies 70 70 70 dB typ Negative Supplies 75 75 75 dB typ Power Dissipation Normal Operation 40 40 40 mW rnax SLEEP = Logic 1, Typically 25 mW Standby Operations 10 SLEEP = Logic 0, A, B, C 20 20 20 µW max Typically 10 µW S4 0 4 0 4 0 µW max NOTES 1The AIN pin presents a very high impedance dynamic load which varies with clock frequency. A ceramic 1 nF capacitor from the A IN to AGND is necessary. Source resistance should be 750 Ω or less. 2Temperature Ranges are as follows: A, B, C Versions: –40 °C to +85°C; S Version: –55 °C to +125 °C. 3Applies after calibration at the temperature of interest. Full-Scale Error applies for both unipolar and bipolar input ranges. 4Total drift over the specified temperature range after calibration at power-up at +25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5In unipolar mode the offset can have a negative value (–V REF) such that the unipolar mode can mimic bipolar mode operation. 6The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF + 0.1). 8All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Operating Temperature Range NOTES *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Linearity Temperature Error Package Model Range (% FSR) Options* AD7703AN –40 °C to +85°C 0.003 N-20 AD7703BN –40 °C to +85°C 0.0015 N-20 AD7703CN –40 °C to +85°C 0.0012 N-20 AD7703AR –40 °C to +85°C 0.003 R-20 AD7703BR –40 °C to +85°C 0.0015 R-20 AD7703CR –40 °C to +85°C 0.0012 R-20 AD7703AQ –40 °C to +85°C 0.003 Q-20 AD7703BQ –40 °C to +85°C 0.0015 Q-20 AD7703CQ –40 °C to +85°C 0.0012 Q-20 AD7703SQ –55 °C to +125°C 0.003 Q-20 *N = Plastic DIP; R = SOIC; Q = Cerdip. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –3– AD7703 REV. D
–6– REV. D PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1 MODE Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB com- ing first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency for f CLKIN/4 and 25% duty cycle. 2 CLKOUT Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. 3 CLKIN Clock Input for External Clock. 4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. 5 DGND Digital Ground. Ground reference for all digital signals. 6D V SS Digital Negative Supply, –5 V nominal. 7A V SS Analog Negative Supply, –5 V nominal. 8 AGND Analog Ground. Ground reference for all analog signals. IN Analog Input. 10 V REF Voltage Reference Input, +2.5 V nominal. This determines the value of positive full-scale in the unipolar mode and of both positive and negative full-scale in the Bipolar Mode. 11 SLEEP Sleep mode pin. When this pin is taken low, the AD7703 goes into a low-power mode with typically 10 µW power consumption. 12 BP/ UP Bipolar/Unipolar mode pin. When this pin is Low, the AD7703 is configured for a unipolar input range going from AGND to VREF. When Pin 12 is High, the AD7703 is configured for a bipolar input range, ± VREF. 13 CAL Calibration mode pin. When CAL is taken High for more than 4 cycles, the AD7703 is reset and performs a calibration cycle when CAL is brought Low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7703s. 14 AV DD Analog Positive Supply, +5 V nominal. 15 DV DD Digital Positive Supply, +5 V nominal. 16 CS Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format deter- mined by the state of the MODE pin. 18 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans- mission of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 SCLK Serial Clock Input/Output. The SCLK pin in configured as an input or output, dependent on the type of se- rial data transmission that has been selected by the MODE pin. When configured as an output in the Syn- chronous Self-Clocking mode, it has a frequency of f CLKIN/4 and a duty cycle of 25%. 20 SDATA Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word. Table I. Bit Weight Table (2.5 V Reference Voltage) UNIPOLAR MODE BIPOLAR MODE mV LSBs % FS ppm FS LSBs % FS ppm FS PIN CONFIGURATION DIP, Cerdip, SOIC MODE SC1 DGND CLKOUT CLKIN AGND DV SS AV SS A IN VREF SDATA SCLK SC2 CAL AV DD DV DD DRDY CS BP/UP SLEEP TOP VIEW (Not to Scale) AD7703
1.0 MHz 50 pF 50 pF
2.0 MHz 20 pF 20 pF
2.000 MHz 30 pF 30 pF
3.579 MHz 20 pF 20 pF
4.096 MHz None None
for the unipolar and bipolar modes are shown in Table I. no missing codes performance. Figure 12. Typical Connections for System Calibration which minimize offset and gain error to typically ± 4 LSBs.
- In bipolar mode it is determined by dividing the span by
219 since the inputs applied represent only half the total codes. are two system calibration modes. voltage must remain stable throughout the calibration step. REF value for the full-scale point.
–10– REV. D Initiating Calibration Table III illustrates the calibration modes available in the AD7703. Not shown in the table is the function of the BP/ UP pin which determines whether the converter has been calibrated to measure bipolar or unipolar signals. A calibration step is initiated by bringing the CAL pin high for at least 4 CLKIN cycles and then bringing it low again. The states of SC1 and SC2 along with the BP/ UP pin will determine the type of calibration to be performed. All three signals should be stable before the CAL pin is taken positive. The SC1 and SC2 inputs are latched when CAL goes high. The BP/ UP input is not latched and therefore must remain in a fixed state throughout the calibration and measurement cycles. Any time the state of the BP/ UP is changed, a new calibration cycle must be performed to enable the AD7703 to function properly in the new mode. When a calibration step is initiated, the DRDY signal will go high and remain high until the step is finished. Table III shows the number of clock cycles each calibration requires. Once a calibration step is initiated it must finish before a new calibra- tion step can be executed. In the two step system calibration mode, the offset calibration step must be initiated before initiat- ing the gain calibration step. Table IV. Output Code Size After Calibration
1 LSB
CAL MODE ZERO-SCALE GAIN FACTOR UNIPOLAR BIPOLAR Self-Cal V AGND VREF (VREF ±VAGND ) 1048576 2(VREF ±VAGND ) 1048576 System Cal S OFF SGAIN (SGAIN ±SOFF ) 1048576 2(SGAIN ±SOFF ) 1048576 Table III. Calibration Truth Table CAL SC1 SC2 CAL TYPE ZERO-SCALE CAL FULL-SCALE CAL SEQUENCE CALIBRATION TIME 0 0 Self-Cal V AGND VREF One Step 3,145,655 Clock Cycles 1 1 System Offset A IN _ 1st Step 1,052,599 Clock Cycles 0 1 System Gain _ A IN 2nd Step 1,068,813 Clock Cycles 1 0 System Offset A IN VREF One Step 2,117,389 Clock Cycles NOTE DRDY remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes DRDY falls as the device begins to settle. When self-calibration is completed, DRDY falls and the output port is updated with a data word that represents the analog input signal. When a system calibration step is completed, DRDY will fall and the output port will be updated with the appropriate data value (all 0s for the zero-scale point and all 1s for the full-scale point). In the system calibration mode, the digital filter must settle before the output code will represent the value of the analog input signal. Tables IV and V indicate the output code size and output coding of the AD7703 in its various modes. In these tables, S OFF is the measured system offset in volts and S GAIN is the measured system gain at the full-scale point in volts. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 V REF and a maximum value of 2 (VREF + 0.1 V). The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. In unipolar mode, the system calibration modes can handle a maximum offset of 0.2 V REF and a minimum offset of –(V REF + 0.1 V). Thus the AD7703 in the unipolar mode can be calibrated to mimic bipolar operation.
higher temperatures, higher CLKIN rates are recommended. leakage currents so that it is significantly less than offset drift. the specified temperature range. ity are not significantly affected by temperature changes. Figure 13. Typical Bipolar Offset vs. Temperature after restrictions limit the amount of offset which can be calibrated. points of the transfer function to exceed the overrange points. the transfer function exceeds the input overrange limit. (approximately 768 ms with a 4.096 MHz clock). See Table III. the SC1 and SC2 inputs, in accordance with Table III. cal offset due to temperature changes after calibration at 25 °C.
attenuation to reduce a larger input voltage range. Figure 14. Equivalent Input Circuit and Input Attenuator 10 pF sample capacitor. The value of t is equal to 62/fCLKIN. imum allowable source resistance, R S(MAX) for an error of V E. can be calibrated in system calibration schemes. no external stray capacitance. or in parallel with a noise current source. temperature in degrees Kelvin ( °C + 273). the spectrum, and most broadband noise is filtered. sampling frequency (f CLKIN/256).
REV. D –13– Therefore, the two analog supplies should be individually decoupled to AGND using 100 nF ceramic capacitors to provide power supply noise rejection at these frequencies. The two digital supplies should similarly be decoupled to DGND. The positive digital supply (DV DD) must never exceed the positive analog supply (AV DD) by more than 0.3 V. Power supply sequencing is therefore important. If separate analog and digital supplies are used, care must be taken to ensure that the analog supply is powered up first. It is also important that power is applied to the AD7703 before signals at VREF, AIN or the logic input pins in order to avoid any possibility of latch-up. If separate supplies are used for the AD7703 and the system digital circuitry, then the AD7703 should be powered up first. A typical scheme for powering the AD7703 from a single set of ± 5 V rails is shown Figure 7. In this circuit AV DD and DVDD are brought along separate tracks from the same +5 V supply. Thus, there is no possibility of the digital supply coming up before the analog supply. SLEEP MODE The low power standby mode is initiated by taking the SLEEP input low, which shuts down all analog and digital circuits and reduces power consumption to 10 µW. When coming out of SLEEP mode it is sometimes possible (when using a crystal to generate CLKIN, for example) to lose the calibration coeffi- cients. Therefore, it is advisable as a safeguard to always do a calibration cycle after coming out of SLEEP mode. DIGITAL INTERFACE The AD7703’s serial communications port allows easy interfacing to industry standard microprocessors. Two different modes of operation are available, optimized for different types of interface. VOLTAGE REFERENCE CONNECTIONS The voltage applied to the V REF pin defines the analog input range. The specified reference voltage is 2.5 V, but the AD7703 will operate with reference voltages from 1 V to 3 V with little degradation in performance. The reference input presents exactly the same dynamic load as the analog input, but in the case of the reference input, source resistance and long settling time introduce gain errors rather than offset errors. Fortunately, most precision references have sufficiently low output impedance and wide enough bandwidth to settle to the required accuracy within 62 clock cycles. The digital filter of the AD7703 removes noise from the refer- ence input, just as it does with noise at the analog input, and the same limitations apply regarding lack of noise rejection at integer multiples of the sampling frequency. Note that the refer- ence should be chosen to minimize noise below 10 Hz. The AD7703 typically exhibits 1.6 LSB rms noise in its measure- ments. This specification assumes a clean reference. Many monolithic bandgap references are available which can supply the 2.5 V needed for the AD7703. However, some of these are not specified for noise especially in the 0.1 Hz to 10 Hz band- width. If the reference noise in this bandwidth is excessive, it can degrade the performance of the AD7703. Recommended references are the AD580 and the LT1019. Both of these 2.5 V references typically have less than 10 mV p-p noise in the 0.1 Hz to 10 Hz band. POWER SUPPLIES AND GROUNDING AGND is the ground reference voltage for the AD7703, and is completely independent of DGND. Any noise riding on the AGND input with respect to the system analog ground will cause conversion errors. AGND should therefore be used as the system ground and also as the ground for the analog input and the reference voltage. The analog and digital power supplies to the AD7703 are independent and separately pinned out, to minimize coupling between analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the sampling frequency.
and eight periods of 64 clock pulses are for digital computation. edge of SCLK and are valid on the rising edge of SCLK.
72 CLKIN CYCLES
64 CLKIN
1024 CLKIN CYCLES
Figure 15. Timing Diagram for SSC Data Transmission Mode Figure 16. SSC Mode Showing Data Timing Relative to SCLK
change on the falling edge of an externally supplied SCLK. word continues to be transmitted and the new data is lost. loaded into the output register. the 4000 series or 74C families is recommended. Figure 17. Timing Diagram for the SEC Mode
–16– REV. D C1477b–2–9/96PRINTED IN U.S.A. MECHANICAL INFORMATION Dimensions shown in inches and (mm) 20-Pin Plastic DIP (Suffix N) 20-Pin Cerdip (Suffix Q) 20-Lead SOIC (Suffix R)