AD7701_17 AD | Alldatasheet
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REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD7701 LC2MOS 16-Bit A/D Converter
FEATURES
0.0015% Linearity Error On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or /H115502.5 V Analog Input Range 4 kSPS Output Data Rate Flexible Serial Interface Ultralow Power
APPLICATIONS
Industrial Process Control Weigh Scales Portable Instrumentation Remote Data Acquisition FUNCTIONAL BLOCK DIAGRAM 14 15 7 64 1 7 AVDD DVDD AVSS DVSS SC1 SC2 13CALIBRATION SRAM 16-BIT A/D CONVERTER ANALOG MODULATOR CAL SLEEP11 CLOCK GENERATOR SERIAL INTERFACE LOGIC SDATA SCLK 3 2 1 18 CLKIN CLKOUT MODE DRDY 6-POLE GAUSSIAN LOW-PASS DIGITAL FILTER AD7701 5DGND AGND AIN VREF BP/UP12 CS CALIBRATION MICROCONTROLLER GENERAL DESCRIPTION The AD7701 is a 16-bit ADC that uses a sigma-delta conversion technique. The analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. The modulator output is processed by an on-chip digital filter with a six-pole Gaussian response, which updates the output data register with 16-bit binary words at word rates up to 4 kHz. The sampling rate, filter corner frequency, and output word rate are set by a master clock input that may be supplied externally, or by a crystal controlled on-chip clock oscillator. The inherent linearity of the ADC is excellent and endpoint accuracy is ensured by self-calibration of zero and full scale, which may be initiated at any time. The self-calibration scheme can also be extended to null system offset and gain errors in the input channel. The output data is accessed through a flexible serial port, which has an asynchronous mode compatible with UARTs and two synchronous modes suitable for interfacing to shift registers or the serial ports of industry-standard microcontrollers. CMOS construction ensures low power dissipation, and a power- down mode reduces the idle power consumption to only 10 µW. PRODUCT HIGHLIGHTS 1. The AD7701 offers 16-bit resolution coupled with outstand- ing 0.0015% accuracy. 2. No missing codes ensures true, usable, 16-bit dynamic range, removing the need for programmable gain and level-setting circuitry. 3. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero and gain error. External circuits can also be included in the calibration loop to remove system offsets and gain errors. 4. A flexible synchronous/asynchronous interface allows the AD7701 to interface directly to UARTs or to the serial ports of industry-standard microcontrollers. 5. Low operating power consumption and an ultralow power standby mode make the AD7701 ideal for loop-powered remote sensing applications, or battery-powered portable instruments.
AD7701* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes
- AN-368: Evaluation Board for the AD7701/AD7703 Sigma- Delta ADCs
- AN-375: ADM2xxL Family for RS-232 Communications
- AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma- Delta ADC Data Sheet
- AD7701: LC2MOS 16-Bit A/D Converter Data Sheet TOOLS AND SIMULATIONS
- Sigma-Delta ADC Tutorial REFERENCE MATERIALS Technical Articles
- Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
- MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
- AD7701 Material Declaration
- PCN-PDN Information
- Quality And Reliability
- Symbols and Footprints DISCUSSIONS View all AD7701 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
REV. E–2– AD7701–SPECIFICATIONS Parameter A, S Version 2 B, T Version2 Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 16 Bits Integral Nonlinearity TMIN to TMAX ± 0.0007 % FSR typ ± 0.003 ± 0.0015 % FSR max Differential Nonlinearity TMIN to TMAX ± 0.125 ± 0.125 LSB typ Guaranteed No Missing Codes ± 0.5 ± 0.5 LSB max Positive Full-Scale Error 3 ± 0.13 ± 0.13 LSB typ ± 0.5 ± 0.5 LSB max Full-Scale Drift 4 ± 1.2 (± 2.3 S Version) ± 1.2 (± 2.3 T Version) LSB typ Unipolar Offset Error 3 ± 0.25 ± 0.25 LSB typ ± 1 ± 1 LSB max Unipolar Offset Drift 4 ± 1.6 (+3/–25 S Version) ± 1.6 (+3/–25 T Version) LSB typ Bipolar Zero Error 3 ± 0.25 ± 0.25 LSB typ ± 1 ± 1 LSB max Bipolar Negative Full-Scale Error 3 ± 0.5 ± 0.5 LSB typ ± 2 ± 2 LSB max Bipolar Negative Full-Scale Drift 4 ± 0.6 (± 1.2 S Version) ± 0.6 (± 1.2 T Version) LSB typ Noise (Referred to Output) 0.1 0.1 LSB rms typ DYNAMIC PERFORMANCE Sampling Frequency, f S fCLKIN/256 f CLKIN/256 Hz Output Update Rate, f OUT fCLKIN/1024 f CLKIN/1024 Hz Filter Corner Frequency, f –3 dB fCLKIN/409,600 f CLKIN/409,600 Hz Settling Time to ± 0.0007% FS 507904/f CLKIN 507904/fCLKIN sec For Full-Scale Input Step SYSTEM CALIBRATION Applies to unipolar and Positive Full-Scale Overrange V REF + 0.1 V REF + 0.1 V max bipolar ranges. After cali- Positive Full-Scale Overrange V REF + 0.1 V REF + 0.1 V max bration, if A IN > VREF, the Negative Full-Scale Overrange –(V REF + 0.1) –(V REF + 0.1) V max device will output all 1s. Maximum Offset Calibration Range 5, 6 If AIN < 0 (unipolar) or Unipolar Input Range –(V REF + 0.1) –(V REF + 0.1) V max –V REF (bipolar), the device Input Span7 0.8 VREF 0.8 VREF V min 2 VREF + 0.2 2 V REF + 0.2 V max ANALOG INPUT Unipolar Input Range 0 to 2.5 0 to 2.5 V Bipolar Input Range ± 2.5 ± 2.5 V Input Capacitance 10 10 pF typ Input Bias Current 1 11 nA typ LOGIC INPUTS All Inputs Except CLKIN VINL, Input Low Voltage 0.8 0.8 V max VINH, Input High Voltage 2.0 2.0 V min CLKIN VINL, Input Low Voltage 0.8 0.8 V max VINH, Input High Voltage 3.5 3.5 V min IIN, Input Current 10 10 µA max LOGIC OUTPUTS VOL, Output Low Voltage 0.4 0.4 V max I SINK = 1.6 mA VOH, Output High Voltage DV DD – 1 DV DD – 1 V min I SOURCE = 100 µA Floating State Leakage Current ± 10 ± 10 µA max Floating State Output Capacitance 9 9 pF typ (TA = 25/H11543C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; V REF = +2.5 V; fCLKIN = 4.096 MHz; Bipolar Mode: MODE = +5 V; A IN Source Resistance = 1k/H90241 with 1 nF to AGND at A IN; unless otherwise noted.)
REV. E AD7701 –3– Parameter A, S Version 2 B, T Version2 Unit Test Conditions/Comments POWER REQUIREMENTS 8 Power Supply Voltages Analog Positive Supply (AV DD) 4.5/5.5 4.5/5.5 V min/V max Digital Positive Supply (DV DD) 4.5/AVDD 4.5/AVDD V min/V max Analog Negative Supply (AV SS) –4.5/–5.5 –4.5/–5.5 V min/V max Digital Negative Supply (DV SS) –4.5/–5.5 –4.5/–5.5 V min/V max Calibration Memory Retention Power Supply Voltage 2.0 2.0 V min DC Power Supply Currents 8 Analog Positive Supply (AI DD) 2.7 2.7 mA max Typically 2 mA Digital Positive Supply (DI DD)2 2 mA max Typically 1 mA Analog Negative Supply (AI SS) 2.7 2.7 mA max Typically 2 mA Digital Negative Supply (DI SS) 0.1 0.1 mA max Typically 0.03 mA Power Supply Rejection 9 Positive Supplies 70 70 dB typ Negative Supplies 75 75 dB typ Power Dissipation Normal Operation 37 37 mW max SLEEP = Logic 1, Typically 25 mW Standby Operation 10 20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0, Typically 10 µW NOTES 1The AIN pin presents a very high impedance dynamic load that varies with clock frequency. 2Temperature ranges are as follows: A, B Versions: –40 °C to +85°C; S, T Versions: –55 °C to +125 °C. 3Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges. 4Total drift over the specified temperature range since calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5In Unipolar mode, the offset can have a negative value (–V REF) such that the Unipolar mode can mimic Bipolar mode operation. 6The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the differen ce between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF +0.1). 8All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice.
REV. E–4– AD7701 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted.) DD + 0.3 V Analog Input Operating Temperature Range NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. PDIP, CERDIP, SOIC MODE SC1 DGND CLKOUT CLKIN AGND DVSS AVSS AIN VREF SDA T A SCLK SC2 CAL AVDD DVDD DRDY CS BP/UP SLEEP TOP VIEW (Not to Scale) AD7701 SSOP MODE SC1 DGND CLKOUT CLKIN AGND DVSS AVSS AIN VREF SDA T A SCLK SC2 CAL AVDD DVDD DRDY CS BP/UP SLEEP TOP VIEW (Not to Scale) AD7701 NC NC NC NC NC NC NC NC NC = NO CONNECT PIN CONFIGURATIONS CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7701 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Linearity Package Model Range Error (% FSR) Options * AD7701AN –40 °C to +85°C 0.003 N-20 AD7701BN –40 °C to +85°C 0.0015 N-20 AD7701AR –40 °C to +85°C 0.003 R-20 AD7701BR –40 °C to +85°C 0.0015 R-20 AD7701ARS –40 °C to +85°C 0.003 RS-28 AD7701AQ –40 °C to +85°C 0.003 Q-20 AD7701BQ –40 °C to +85°C 0.0015 Q-20 AD7701SQ –55 °C to +125°C 0.003 Q-20 AD7701TQ –55 °C to +125°C 0.0015 Q-20 *N = PDIP; Q = CERDIP; R = SOIC; RS = SSOP.
REV. E AD7701 –5– PIN FUNCTION DESCRIPTIONS Pin No. PDIP, CERDIP, SOIC SSOP Mnemonic Description 11 MODE Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the Asynchronous Communications (AC) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes, each with one start bit and two stop bits. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency of f CLKlN/4 and 25% duty cycle.
22 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between
CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. 33 CLKIN Clock Input for External Clock. 4, 17 4, 25 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. 55 DGND Digital Ground. Ground reference for all digital signals. 68 D V SS Digital Negative Supply, –5 V Nominal. 6, 7, 9, 11, NC No Connect. 18, 21, 22, 23 71 0 A V SS Analog Negative Supply, –5 V Nominal. 81 2 AGND Analog Ground. Ground reference for all analog signals. 91 3 A IN Analog Input. 10 14 V REF Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar mode and of both positive and negative full scale in Bipolar mode. 11 15 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7701 goes into a low power mode with typically 10 µW power consumption. 12 16 BP/ UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a uni- polar input range going from AGND to V REF. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ±VREF. 13 17 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7701 is reset and performs a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7701s. 14 19 AV DD Analog Positive Supply, +5 V Nominal. 15 20 DV DD Digital Positive Supply, +5 V Nominal. 16 24 CS Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format determined by the state of the MODE pin. 18 26 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after transmission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 27 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, depen- dent on the type of serial data transmission that has been selected by the MODE pin. When configured as an output in the Synchronous Self-Clocking mode, it has a fre- quency of fCLKIN/4 and a duty cycle of 25%. 20 28 SDATA Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial word. The transmission format is determined by the state of the MODE pin.
REV. E–6– AD7701 TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V /H11550 10%; AVSS = DVSS = –5 V /H11550 10%; AGND = DGND = O V; f CLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV DD; unless otherwise noted.) Limit at TMIN, TMAX Limit at TMIN, TMAX Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments fCLKIN 3, 4 200 200 kHz min Master Clock Frequency: Internal Gate Oscillator. 55 MHz max Typically 4.096 MHz. 200 200 kHz min Master Clock Frequency: Externally Supplied.
55 MHz max
5 50 50 ns max Digital Output Rise Time. Typically 20 ns. tf 5 50 50 ns max Digital Output Fall Time. Typically 20 ns. t1 00 ns min SC1, SC2 to CAL High Setup Time. t2 50 50 ns min SC1, SC2 Hold Time after CAL Goes High. 6 1000 1000 ns min SLEEP High to CLKIN High Setup Time. SSC MODE 7 3/fCLKIN 3/fCLKIN ns max Data Access Time ( CS Low to Data Valid). t5 100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ). t6 250 250 ns min MSB Data Setup Time. Typically 380 ns. t7 300 300 ns max SCLK High Pulsewidth. Typically 240 ns. t8 790 790 ns max SCLK Low Pulsewidth. Typically 730 ns. 8 l/fCLKIN +200 l/f CLKIN +200 ns max SCLK Rising Edge to Hi-Z Delay (l/f CLKIN + 100 ns typ). t10 8, 9 (4/fCLKIN) +200 (4/f CLKIN) +200 ns max CS High to Hi-Z Delay. SEC MODE fSCLK 55 MHz Serial Clock Input Frequency. t11 35 35 ns min SCLK Input High Pulsewidth. t12 160 160 ns min SCLK Low Pulsewidth. t13 7, 10 160 160 ns max Data Access Time ( CS Low to Data Valid). Typically 80 ns. t14 11 150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns. t15 8 250 250 ns max CS High to Hi-Z Delay. t16 8 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns. AC MODE t17 40 40 ns min CS Setup Time. Typically 20 ns. t18 180 180 ns max Data Delay Time. Typically 90 ns. t19 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns. NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 1 to 6. 3CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present i n this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7701 is production tested with f CLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. 5Specified using 10% and 90% points on waveform of interest. 6In order to synchronize several AD7701s together using the SLEEP pin, this specification must be met. 7t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 8t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The mea sured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quote d in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitance. 9If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to h igh impedance. 10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than four CLKIN cycles plus 160 ns after CS goes low. 11SDATA is clocked out on the falling edge of the SCLK input. Specifications subject to change without notice.
Figure 12. AD7701 Step Response synchronously or asynchronously. and output data rate required by the application.
- Inputs are voltages at code transitions.
tion to reduce a larger input voltage range. be taken to ensure that the source impedance is sufficiently low. Figure 13. Equivalent Input Circuit and Input Attenuator AD7701 allows 62 clock periods for the input voltage to settle. VO is the final settled value. VIN is the value of the input signal. R is the value of the input source resistance. C is the 10 pF sample capacitor. can be calibrated in system calibration schemes. k is Boltzmann’s constant (1.38 × 10–23 J/K). T is temperature in degrees Kelvin ( °C + 273). passes unattenuated to the output. elN and eOUT are rms noise terms referred to the input. fC is the filter –3 dB corner frequency (f CLKIN/409600). fS is the sampling frequency (f CLKIN/256).
00 Self-Calibration AGND V REF One Step 3,145,655 Clock Cycles
11 System Offset A IN First Step 1,052,599 Clock Cycles
01 System Gain A IN Second Step 1,068,813 Clock Cycles
10 System Offset A IN VREF One Step 2,117,389 Clock Cycles
modes, DRDY falls as the device begins to settle. scale is calibrated to the system reference. lution. The practical limit is the noise floor of the AD7701. input voltage is (–VREF – 100 mV). (approximately 768 ms, with a 4.096 MHz clock). See Table III. the SC1 and SC2 inputs, in accordance with Table III. stabilized before calibration is initiated. analog supply is powered up first. are brought along separate tracks from the same 5 V supply. Figure 7. The on-chip digital filtering of the AD7701 further into the conversion process.
10 V supply, using an op amp to provide a half supply refer-
Figure 17. Single-Supply Operation cycles) before accessing the output data. edge of SCLK and are valid on the rising edge of SCLK.
72 CLKIN CYCLES
64 CLKIN CYCLES
1024 CLKIN CYCLES
Figure 18. Timing Diagram for SSC Data Transmission Mode
microprocessors such as the COPS series, 68HC11, and 68HC05. change on the falling edge of an externally supplied SCLK. old data-word continues to be transmitted and the new data is lost. the AD7701 will continue transmission with the same data bit. is loaded into the output register.
72 CLKIN
Figure 19. SSC Mode Showing Data Timing Relative to SCLK Figure 20. Timing Diagram for the SEC Mode
such as the 8051 and TMS70X2. as in Figure 21. The SDATA output will then go three-state. DB0 to DB7 are transmitted in the same format as the first byte. matic safeguard does not exist. of the 4000 series or 74C families is recommended. the digital system clock via CLKIN. Figure 21. Timing Diagram for Asynchronous Communications Mode
REV. E AD7701 –17– OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] (N-20) Dimensions shown in inches and (millimeters) 1 10 0.985 (25.02) 0.965 (24.51) 0.945 (24.00) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) SEATING PLANE MAX 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) BSC 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095-AE 20-Lead Standard Small Outline Package [SOIC] Wide Body (R-20) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AC 0.75 (0.0295) 0.25 (0.0098) 20 11 101 0.32 (0.0126) 0.23 (0.0091) 8/H11543 0/H11543 /H11547 45/H11543 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) COPLANARITY 0.10 20-Lead Ceramic Dual In-Line Pacakage [CERDIP] (Q-20) Dimensions shown in inches and (millimeters) 11 0 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 1.060 (26.92) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8/H11543 4/H11543 0/H11543 0.05 MIN 1.85 1.75 1.65
2.00 MAX
0.38
0.22 SEATING
0.65 BSC 0.10 COPLANARITY 28 15 141 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 COMPLIANT TO JEDEC STANDARDS MO-150AH
REV. E–18– AD7701
Revision History
3/03—Data Sheet changed from REV. D to REV. E.
–19–
C01162–0–3/03(E) PRINTED IN U.S.A. –20–