AD7625BCPZ

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16-Bit, 6 MSPS, PulSAR Differential ADC Data Sheet AD7625 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Throughput: 6 MSPS SNR: 93 dB INL: ±0.45 LSB typical, ±1 LSB maximum DNL: ±0.3 LSB typical, ±0.5 LSB maximum Power dissipation: 135 mW 32-lead LFCSP (5 mm × 5 mm) SAR architecture No latency/no pipeline delay 16-bit resolution with no missing codes Zero error: ±1.5 LSB Differential input voltage: ±4.096 V Serial LVDS interface Self-clocked mode Echoed-clock mode Can use LVDS or CMOS for conversion control (CNV signal) Reference options Internal: 4.096 V External (1.2 V) buffered to 4.096 V External: 4.096 V

APPLICATIONS

High dynamic range telecommunications Receivers Digital imaging systems High speed data acquisition Spectrum analysis Test equipment FUNCTIONAL BLOCK DIAGRAM AD7625 CLOCK LOGIC SERIAL LVDS IN– IN+ REFIN REF VCM SAR CNV+, CNV– VIO D+, D– DCO+, DCO– CLK+, CLK– 1.2V BAND GAP CAP DAC 07652-001 Figure 1. GENERAL DESCRIPTION The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive approximation register (SAR) based architecture analog-to-digital converter (ADC). SAR architecture allows unmatched perfor- mance both in noise (93 dB SNR) and in linearity (1 LSB). The AD7625 contains a high speed, 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV± rising edge, it samples the voltage difference between the IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or echoed-clock serial interface, reducing external hardware connections. The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with operation specified from −40°C to +85°C. Table 1. Fast PulSAR® ADC Selection

18 AD7643 AD7641 AD7960

AD7625* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD7625 Evaluation Kit DOCUMENTATION Data Sheet
• AD7625: 16-Bit, 6MSPS, PulSAR Differential ADC Data Sheet User Guides
• UG-745: Evaluating the AD7625/AD7626 16-Bit, 6 MSPS/

10 MSPS PulSAR Differential ADC

• CN0080
• CN0307 REFERENCE MATERIALS Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD7625 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD7625 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

10/15—Rev. A to Rev. B Added Aperture Delay Parameter and Current Drain Parameter, Changes to CLK± Period Parameter and Endnote 2, Table 3 ... 5 7/12—Rev. 0 to Rev. A Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) .... 22 1/09—Revision 0: Initial Version

Rev. B | Page 3 of 24 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −V REF +V REF V Operating Input Voltage VIN+, VIN− to GND −0.1 VREF + 0.1 V Common-Mode Input Range VREF/2 − 0.05 V REF/2 V REF/2 + 0.05 V Common-Mode Rejection Ratio f IN = 1 MHz 60 dB Input Current Midscale input 77 μA THROUGHPUT Complete Cycle 166 ns Throughput Rate 0.1 6 MSPS DC ACCURACY Integral Linearity Error −1 ±0.45 +1 LSB No Missing Codes 16 Bits Differential Linearity Error −0.5 ±0.3 +0.5 LSB Transition Noise 0.6 LSB Zero Error TMIN to TMAX −4 ±1.5 +4 LSB Zero Error Drift 0.5 ppm/°C Gain Error TMIN to TMAX 8 20 LSB Gain Error Drift 0.4 ppm/°C Power Supply Sensitivity1 VDD1 = 5 V ± 5% 0.4 LSB VDD2 = 2.5 V ± 5% 0.2 LSB AC ACCURACY External Reference fIN = 20 kHz Dynamic Range 92.5 93.2 dB Signal-to-Noise Ratio 92 93 dB Spurious-Free Dynamic Range 106 dB Total Harmonic Distortion −105.5 dB Signal-to-(Noise + Distortion) 91.5 92 dB Internal Reference fIN = 20 kHz Dynamic Range 92.5 93.2 dB Signal-to-Noise Ratio 91.5 92.9 dB Spurious-Free Dynamic Range 106 dB Total Harmonic Distortion −105.5 dB Signal-to-(Noise + Distortion) 91 92.5 dB −3 dB Input Bandwidth 100 MHz Aperture Delay 1.5 ns Aperture Jitter 0.25 ps rms INTERNAL REFERENCE Output Voltage REFIN @ 25°C 1.2 V Temperature Drift −40°C to +85°C ±15 ppm/°C REFERENCE BUFFER REFIN Input Voltage Range 1.2 V REF Output Voltage Range 4.076 4.096 4.116 V Line Regulation VDD1 ± 5%, VDD2 ± 5% 5 mV EXTERNAL REFERENCE Voltage Range REF 4.096 V Current Drain 6 MSPS 590 μA

Rev. B | Page 4 of 24 Parameter Test Conditions/Comments Min Typ Max Unit VCM PIN @ 25°C Output Voltage REF/2 V Output Impedance 4 5 6 kΩ LVDS I/O (ANSI-644) Data Format Serial LVDS twos complement Differential Output Voltage, VOD R L = 100 Ω 200 350 454 mV Common-Mode Output Voltage, VOCM2 R L = 100 Ω 850 1250 1375 mV Differential Input Voltage, VID 100 650 mV Common-Mode Input Voltage, VICM 800 1575 mV POWER SUPPLIES Specified Performance VDD1 4.75 5 5.25 V VDD2 2.37 2.5 2.63 V VIO 2.37 2.5 2.63 V Operating Currents Static—Not Converting VDD1 4.5 7.8 mA VDD2 17 22.7 mA VIO Self-clocked mode and echoed- clock mode 11 13 mA With Internal Reference 6 MSPS throughput VDD1 11 15.4 mA VDD2 21.5 28.3 mA VIO Self-clocked mode and echoed- clock mode 13.5 16 mA Without Internal Reference 6 MSPS throughput VDD1 9 12.1 mA VDD2 21 26 mA VIO Self-clocked mode and echoed- clock mode 13.5 16 mA Power Dissipation3 Static—Not Converting 95 130 mW With Internal Reference 6 MSPS throughput 145 190 mW Without Internal Reference 6 MSPS throughput 135 165 mW Energy per Conversion 6 MSPS throughput 22 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 Using an external reference. 2 The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV. 3 Power dissipation is for the AD7625 device only. In self-clocked interface mode, 9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 18 mW is dissipated in two 100 Ω terminators.

Rev. B | Page 5 of 24 TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Time Between Conversions1 t CYC 166 10,000 ns Acquisition Time tACQ 40 ns CNV± High Time tCNVH 10 40 ns CNV± to D± (MSB) Delay tMSB 145 ns CNV± to Last CLK± (LSB) Delay tCLKL 110 ns CLK± Period2 t CLK (tCYC − tMSB + tCLKL)/n 4 3.33 ns CLK± Frequency fCLK 250 300 MHz CLK± to DCO± Delay (Echoed-Clock Mode) tDCO 0 4 7 ns DCO± to D± Delay (Echoed-Clock Mode) tD 0 1 ns CLK± to D± Delay tCLKD 0 4 7 ns 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18.

1 See the Analog Inputs section. 3 Transient currents of up to 100 mA do not cause SCR latch-up. soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance

1. CONNECT THE EXPOSED PAD TO THE GROUND

PLANE OF THE PCB USING MULTIPLE VIAS.

1 GND

2 IN+

3 IN–

4 VCM

5 VDD1

6 VDD1

7 VDD2

Table 6. Pin Function Descriptions 1 VDD1 P Analog 5 V Supply. Decouple th e 5 V supply with a 100 nF capacitor. supply this pin first and then be traced to the other VDD2 pins (Pin 7 and Pin 18). 3 CAP1 AO Connect this pin to a 10 nF capacitor. and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280. reference (connected to REF), this pin is a no connect and does not require any capacitor. EN1 = 0, EN0 = 0: Illegal state. connected to the REFIN pin is required. connected to the REF pin is required. EN1 = 1, EN0 = 1: Enable internal reference and reference buffer. 7 VDD2 P Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor. CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. 10, 11 D−, D+ DO LVDS Data Outputs. The conver sion data is output serially on these pins. 12 VIO P Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor. 13 GND P Ground. Return path for the 100 nF capacitor connected to Pin 12. 14, 15 DCO−, DCO+ DO LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected. edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+. 16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. 18 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. present on the REF pin, which can be useful for driving the common mode of the input amplifiers. 22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. 23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−.

Rev. B | Page 8 of 24 Pin No. Mnemonic Type 1 Description 25, 26, 28 CAP2 AO Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF , low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). 27 GND P Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. 29, 30, 32 REF AI/O Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN input), the 4.096 V system reference is produced at this pin. When using an external reference, such as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect all three REF pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND). 31 GND P Ground. Return path for the 10 μF capacitor connected to Pin 29, Pin 30, and Pin 32. EP Exposed Pad The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. See the Exposed Pad section for more information. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power.

Rev. B | Page 12 of 24 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of an 80 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− at frequency fS. CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. Pf S is the power at frequency fS in the ADC output. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) Error Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is meas- ured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINAD dB − 1.76)/6.02] Gain Error The first transition (from 100 … 000 to 100 …001) should occur at a level ½ LSB above nominal negative full scale (−4.0959375 V for the ±4.096 V range). The last transition (from 011 … 110 to 011 … 111) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.0959375 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is N p-p INVLSB 2(V)  Power Supply Rejection Ratio (PSRR) V ariations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Reference Voltage T emperature Coefficient The reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V REF) meas- ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as 610 C 25 ((C ppm/      ) T – T ( ) ( V ) Min V – ) Max V) ( TCV MINMAXREF REFREF REF where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = −40°C. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Zero Error Zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.

Figure 18. ADC Simplified Schematic of 93 dB SNR, ±0.45 LSB INL, and ±0.3 LSB DNL. on-chip reference and on-chip reference buffer. and CNV− pins can be applied using a CMOS or LVDS source. connected to the two comparator inputs. of this process, the control logic generates the ADC output code. signaling (LVDS) to enable high data transfer rates. AD7625 to transfer data to the digital host. the Digital Interface section.

1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION. 2 CREF IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL. FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 IS AN ILLEGAL STATE). 4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS. 5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR. 6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. Figure 22. Typical Application Diagram

controlled by the EN1 and EN0 pins (see Table 8). Table 8. Voltage Reference Options1 reference buffer (both are enabled). internal reference buffer enabled. The internal reference is disabled. 1 EN1 = 0 and EN0 = 0 is an illegal state. THE REF AND REFIN PINS EXTERNALLY. AND ENABLES THE INTERNAL REFERENCE BUFFER. TO CREATE A 4.096V REFERENCE FOR THE ADC. Figure 25. Voltage Reference Options

rising edge of the CNV signal. digital hosts (FPGA, shift register, microprocessor, and so on). each AD7625 and the digital host. must be returned low (≤tCNVH maximum) for valid operation. tional CNV± pulses are ignored during the conversion phase. driven to 0s. Set CLK± to idle low between CLK± bursts. Figure 29. Echoed-Clock Interface Mode Timing Diagram

each AD7625 device and the digital host. CNVH maximum) for valid operation. tional CNV± pulses are ignored during the conversion phase. the header and should be used as the gating device for CLK±. lost. Set CLK± to idle high between bursts of 18 CLK± pulses. Figure 30. Self-Clocked Interface Mode Timing Diagram

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 2 The EVAL-SDP-CH1Z board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the FMC designator.

Rev. B | Page 23 of 24 NOTES

Rev. B | Page 24 of 24 NOTES ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07652-0-10/15(B)