AD7621ASTZRL1

AD7621 AD | Alldatasheet

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Technical content

16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC AD7621 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.

FEATURES

3 MSPS (wideband warp and warp mode)

2 MSPS (normal mode)

1.25 MSPS (impulse mode)

2.048 V internal reference

Differential input range: ±VREF (VREF up to 2.5 V) INL: ±2 LSB maximum, ±1 LSB typical 16-bit resolution with no missing codes SINAD: 89 dB typical @ 100 kHz THD: −101 dB typical @ 100 kHz No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

2.5 V single-supply operation

Power dissipation: 65 mW typical @ 3 MSPS 48-lead LQFP and 48-lead LFCSP_VQ packages Speed upgrade of the AD7677

APPLICATIONS

High speed data acquisition Digital signal processing Communications Instrumentation Spectrum analysis ATE FUNCTIONAL BLOCK DIAGRAM 04565-001 CONTROL LOGIC AND CALIBRATION CIRCUITRY CLOCK AD7621 DGNDDVDD AVDD AGND REF REFGND IN+ IN– PD RESET CNVST PDBUF REFBUFIN WARP IMPULSE PDREF REF TEMP D[15:0] BUSY RD CS OB/2C OGND OVDD BYTESWAP SER/PAR REF AMP SERIAL PORT PARALLEL INTERFACE SWITCHED CAP DAC Figure 1. Table 1. PulSAR Selection specified from −40°C to +85°C. The AD7621 has no missing 16-bit code. arrangement compatible with 2.5 V , 3.3 V , or 5 V logic. Serial or Parallel Interface.

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

5/05 — Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −VREF VREF V Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD1 V Analog Input CMRR fIN = 100 kHz 55 dB Input Current 3 MSPS throughput 25 μA Input Impedance2 THROUGHPUT SPEED Complete Cycle Wideband warp, warp modes 333 ns Throughput Rate Wideband warp, warp modes 0.001 3 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 500 ns Throughput Rate Normal mode 0 2 MSPS Complete Cycle Impulse mode 800 ns Throughput Rate Impulse mode 0 1.25 MSPS DC ACCURACY All modes Integral Linearity Error3 VREF = 2.048 V, PDREF = high −2 ±1 +2 LSB4 No Missing Codes VREF = 2.048 V, PDREF = high 16 Bits Differential Linearity Error VREF = 2.048 V, PDREF = high −1 +2 LSB Transition Noise VREF = 2.5 V 0.69 LSB Transition Noise VREF = 2.048 V 0.82 LSB Zero Error, TMIN to TMAX5 −30 +30 LSB Zero Error Temperature Drift ±1 ppm/°C Gain Error, TMIN to TMAX5 −0.38 +0.38 % of FSR Gain Error Temperature Drift ±2 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±3 LSB AC ACCURACY Dynamic Range fIN = 20 kHz, VREF = 2.5 V 90.5 dB6 Signal-to-Noise fIN = 20 kHz, VREF = 2.5 V 88 90 dB fIN = 20 kHz, VREF = 2.048 V 86 88 dB fIN = 100 kHz, VREF = 2.5 V 89.2 dB Spurious-Free Dynamic Range fIN = 20 kHz 103 dB fIN = 100 kHz 101 dB Total Harmonic Distortion fIN = 20 kHz –102 dB fIN = 100 kHz −100 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 2.5 V 87.5 89.8 dB fIN = 20 kHz, VREF = 2.048 V 87.5 dB fIN = 100 kHz, VREF = 2.5 V 89 dB –3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 50 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift –40°C to +85°C ±7 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V

Rev. 0 | Page 4 of 32 Parameter Conditions Min Typ Max Unit Turn-On Settling Time CREF = 10 μF 5 ms REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V REFBUFIN Output Resistance 6.33 kΩ EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 1.8 2.048 AVDD V Current Drain 3 MSPS throughput 250 μA REFERENCE BUFFER PDREF = high, PDBUF = low REFBUFIN Input Voltage Range 1.05 1.2 1.30 V TEMPERATURE PIN Voltage Output @ 25°C 273 mV Temperature Sensitivity 0.85 mV/°C Output Resistance 4.7 kΩ DIGITAL INPUTS Logic Levels VIL –0.3 +0.6 V VIH 1.7 5.25 V IIL –1 +1 μA IIH –1 +1 μA DIGITAL OUTPUTS Data Format7 Pipeline Delay8 VOL ISINK = 500 μA 0.4 V VOH ISOURCE = –500 μA OVDD − 0.3 V POWER SUPPLIES Specified Performance AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V OVDD 2.309 3.6 V Operating Current10 3 MSPS throughput AVDD11 With internal reference 25.2 mA DVDD 3.6 mA OVDD 1 mA Power Dissipation11 With Internal Reference10 3 MSPS throughput 70 86 mW Without Internal Reference10 3 MSPS throughput 65 80 mW With Internal Reference 12 1.25 MSPS throughput 42 55 mW Without Internal Reference12 1.25 MSPS throughput 37 50 mW In Power-Down Mode13 PD = high 600 μW TEMPERATURE RANGE14 Specified Performance TMIN to TMAX –40 +85 °C 1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF. 2 See the Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV. 5 See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 16-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In warp mode. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 In impulse mode. Tested in parallel reading mode. 13 With all digital inputs forced to OVDD. 14 Consult factory for extended temperature range.

Rev. 0 | Page 5 of 32 TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (Refer to Figure 31 and Figure 32) Convert Pulse Width t1 15 701 ns Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3 t2 333/500/800 ns CNVST Low to BUSY High Delay t3 23 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 283/430/560 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 283/430/560 ns Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t8 50/70/50 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay4 t38 10 ns BUSY High Time from RESET Low4 t39 600 ns PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35) CNVST Low to DATA Valid Delay t10 283/430/560 ns (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay t11 2 ns Bus Access Request to DATA Valid t12 20 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay5 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 12/137/263 ns SYNC Asserted to SCLK First Edge Delay t18 0.5 ns Internal SCLK Period6 t19 8 12 ns Internal SCLK High6 t20 2 ns Internal SCLK Low6 t21 3 ns SDOUT Valid Setup Time6 t22 1 ns SDOUT Valid Hold Time6 t23 0 ns SCLK Last Edge to SYNC Delay6 t24 0 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns BUSY High in Master Serial Read after Convert6 t28 See Table 4 CNVST Low to SYNC Asserted Delay (All Modes) t29 275/400/500 ns SYNC Deasserted to BUSY Low Delay t30 13 ns

Rev. 0 | Page 7 of 32 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs/Outputs IN+1, IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND AVDD + 0.3 V to AGND − 0.3 V Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD –0.3 V to +2.7 V OVDD –0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD to OVDD +2.8 V to −3.8 V OVDD to DVDD2 ≤ +0.3 V if DVDD < 2.3 V Digital Inputs −0.3 V to +5.5 V PDREF, PDBUF3 ±20 mA Internal Power Dissipation4 700 mW Internal Power Dissipation5 2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C 1 See the Analog Inputs section. 2 See the Power Supply section. 3 See the Voltage Reference Input section.

4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,

θJC = 30°C/W. 5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discha rge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1, 41, 42 AGND P Analog Power Ground Pin. 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. when low, the MSB is inverted resulting in a twos complement output from its internal shift register. minimum conversion rate must be applied in order to guarantee full specified accuracy. maintained independent of the minimum conversion rate. the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. 11, 12 D[2:3] DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. 13 D4 DI/O When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. (master ) or external (slave) serial data clock. When EXT/INT = low: master mode. The internal serial clock is selected on SCLK output. by CS, connected to the SCLK input.

Rev. 0 | Page 9 of 32 Pin No. Mnemonic Type 1 Description 14 D5 DI/O When SER/PAR = low this output is used as Bit 5 of the parallel port data output bus. or INVSYNC When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 DI/O When SER/PAR = low this output is used as Bit 6 of the parallel port data output bus. or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal. 16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus. or RDC When SER/PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is read during current conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result is read after conversion. or SDIN Serial Data In. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). 19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D8 DO When SER/PAR = low this output is used as Bit 8 of the parallel port data output bus. or SDOUT When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode (EXT/INT = low). SDOUT is valid on both edges of SCLK. In slave mode (EXT/INT = high): When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D9 DI/O Parallel Port Data Output Bus Bit 9. When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus. or SCLK Serial Clock. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 DO When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus. or SYNC When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. 24 D11 DO Parallel Port Data Output Bus Bit 11. When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus. or RDERROR Read Error. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. 30 DGND P Digital Power Ground. 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.

Rev. 0 | Page 10 of 32 Pin No. Mnemonic Type 1 Description 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. 33 RESET DI Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. 34 PD DI Power-Down Input. When high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 AGND P Analog Power Ground Pin. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. 38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. 46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

Rev. 0 | Page 11 of 32 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive full- scale. The point used as negative full-scale occurs ½ LSB before the first code transition. Positive full-scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full-scale (−2.0479688 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSBs below the nominal full-scale (2.0479531 V for the ±2.048 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7621 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage T emperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V REF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as MINMAXREF REFREF REF 10) T – T ( ) 25 ( V ) ( V – ) ( V) ( TCV ×× °= ° CC ppm/ MinMax where: VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C

Figure 21. ADC Simplified Schematic modes to optimize performances according to the applications. samples per second (3 MSPS). capacitors which are connected to the two comparator inputs. comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. output code and brings BUSY output low. suitable to specific applications. where both high accuracy and fast sample rate are required.

Rev. 0 | Page 16 of 32 TRANSFER FUNCTIONS Using the OB/2C digital input, the AD7621 offers two output codings: straight binary and twos complement. The LSB size with VREF = 2.048 V is 2 × VREF/65536, which is 62.5 μV . Refer to Figure 22 and Table 7 for the ideal transfer characteristic. 04565-025 000...000 000...001 000...010 111...101 111...110 111...111 ADC CODE (Straight Binary) ANALOG INPUT +FSR–1.5 LSB +FSR–1 LSB–FSR+1 LSB–FSR –FSR+0.5 LSB Figure 22. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages

Description

VREF = 2.048 V Straight Binary Twos Complement FSR −1 LSB +2.047938 V 0xFFFF1 0x7FFF1 FSR − 2 LSB +2.047875 V 0xFFFE 0x7FFE Midscale + 1 LSB +62.5 μV 0x8001 0x0001 Midscale 0 V 0x8000 0x0000 Midscale − 1 LSB −62.5 μV 0x7FFF 0xFFFF −FSR + 1 LSB −2.047938 V 0x0001 0x8001 −FSR −2.048 V 0x00002 0x80002

1 This is also the code for overrange analog input (VIN+ − VIN− above

VREF − VREFGND).

2 This is also the code for underrange analog input (VIN+ − VIN− below

−VREF + VREFGND). 04565-026 RD CS 100nF 100nF AVDD 10μF 100nF AGND DGND DVDD OVDD OGND CNVST BUSY SDOUT SCLK RESETPD REFBUFIN 10Ω D CLOCK AD7621 MICROCONVERTER/ MICROPROCESSOR/ DSP SERIAL PORT DIGITAL INTERFACE SUPPLY (2.5V OR 3.3V) ANALOG SUPPLY (2.5V) OVDDWARP DIGITAL SUPPLY (2.5V) IN+ IN–U2 10Ω NOTE 5 50Ω 50pF NOTE 1 ANALOG INPUT + CC CC 1nF 1nF 10Ω NOTE 1 SER/PAR OB/2C REFGND REF PDBUFPDREF 100nF ANALOG INPUT – NOTE 2 NOTE 2 NOTE 3 NOTE 4 NOTE 3 NOTE 7 NOTE 6 IMPULSE 10μF10μF CREF 10μF 10kΩ 50pF 1. SEE ANALOG INPUT SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10μF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram

• The driver needs to have a THD performance suitable to that of the AD7621. Figure 13 gives the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. Single-to-Differential Driver For applications using unipolar analog signals, a single-ended- to-differential driver, as shown in Figure 27, allows for a differential input into the part. This configuration, when provided an input signal of 0 to VREF, will produce a differential ±VREF with midscale at VREF/2. The one-pole filter using R = 10 Ω and C = 1 nF provides a corner frequency of 16 MHz. If the application can tolerate more noise, the AD8139 differential driver can be used. 04565-030 AD8021 ANALOG INPUT (UNIPOLAR 0V TO 2.048V) AD8021 IN+ IN– AD7621 REF 10μF 10Ω 10Ω 100nF 1nF 1nF 10pF 10pF1kΩ 1kΩ 590Ω 590Ω

Figure 27. Single-Ended-to-Differential Driver Circuit drift internal voltage reference or an external reference. can be used in almost all applications. 2.048 V reference on the REF pin. 7 ppm/°C. This typical drift characteristic is shown in Figure 7. decouple this with a ceramic capacitor greater than 100 nF. Thus, the capacitor provides an RC filter for noise reduction.

Rev. 0 | Page 27 of 32 APPLICATION LAYOUT While the AD7621 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7621 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7621, or as close as possible to the AD7621. If the AD7621 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7621. To prevent coupling noise onto the die, avoid radiating noise, and to reduce feedthrough:

• Do not run digital lines under the device.
• Do run the analog ground plane under the AD7621.
• Do shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths.
• Avoid crossover of digital and analog signals.
• Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7621 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7621, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7621 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. Refer to Figure 23 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7621 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING THE AD7621 PERFORMANCE A recommended layout for the AD7621 is outlined in the documentation of the EV AL-AD7621CB evaluation board for the AD7621. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EV AL- CONTROLBRD3.

9.00 BSC

0.08 MAX

Figure 43. 48-Lead Low Profile Quad Flatpack (LQFP)

0.50 BSC

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

0.25 MIN

Figure 44. 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Rev. 0 | Page 29 of 32 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7621ACP −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621ACPRL −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621ACPZ1 −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621ACPZRL1 −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621AST −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 AD7621ASTRL −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 AD7621ASTZ1 −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 AD7621ASTZRL1 −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 EVAL-AD7621CB2 Evaluation Board EVAL-CONTROLBRD33 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.

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Rev. 0 | Page 32 of 32 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04565–0–5/05(0)