AD7616 (Rev. 0)
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- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 50
Technical content
16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC Data Sheet AD7616 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
16-channel, dual, simultaneously sampled inputs Independently selectable channel input ranges True bipolar: ±10 V, ±5 V, ±2.5 V Single 5 V analog supply and 2.3 V to 3.6 V VDRIVE supply Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance First-order antialiasing analog filter On-chip accurate reference and reference buffer Dual 16-bit successive approximation register (SAR) ADC Throughput rate: 2 × 1 MSPS Oversampling capability with digital filter Flexible sequencer with burst mode Flexible parallel/serial interface SPI/QSPI/MICROWIRE/DSP compatible Optional cyclic redundancy check (CRC) error checking Hardware/software configuration Performance 92 dB SNR at 500 kSPS (2× oversampling) 90.5 dB SNR at 1 MSPS −103 dB THD ±1 LSB INL (typical), ±0.99 LSB DNL (maximum) 8 kV ESD rating on analog input channels On-chip self detect function 80-lead LQFP package
APPLICATIONS
Instrumentation and control systems Data acquisition systems (DASs) GENERAL DESCRIPTION The AD7616 is a 16-bit, DAS that supports dual simultaneous sampling of 16 channels. The AD7616 operates from a single 5 V supply and can accommodate ±10 V , ±5 V, and ±2.5 V true bipolar input signals while sampling at throughput rates up to 1 MSPS per channel pair with 90.5 dB SNR. Higher SNR performance can be achieved with the on-chip oversampling mode (92 dB for an oversampling ratio (OSR) of 2). The input clamp protection circuitry can tolerate voltages up to ±21 V. T h e AD7616 has 1 MΩ analog input impedance, regardless of sampling frequency. The single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The device contains analog input clamp protection, a dual, 16-bit charge redistribution SAR analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7616 is serial peripheral interface (SPI)/QSPI™/DSP/ MICROWIRE compatible FUNCTIONAL BLOCK DIAGRAM Figure 1. 13591-001 RFB1MΩ 1MΩ RFB FIRST- ORDER LPF RFB1MΩ 1MΩ RFB FIRST- ORDER LPF V0A V0AGND RFB1MΩ 1MΩ RFB V7A V7AGND V0B V0BGND V7B V7BGND 9:1 MUX BUSY CONVST CONTROL INPUTS CLK OSC REFINOUT REFSEL SER/PAR SER1W OSR DIGITAL FILTER 2.5V REF REFCAP NOTES 1. MULTIFUNCTION PINS, SUCH AS DB15/OS2, ARE REFERRED TO BY A SINGLE FUNCTION OF THE PIN, FOR EXAMPLE, DB15, WHEN ONLY THAT FUNCTION IS RELEVANT. REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION FOR MORE INFORMATION. SERIAL REGCAP REGCAPD 1.8V DLDO VCC AD7616 9:1 MUX 16-BIT SAR 16-BIT SAR OS2 TO OS0 VDRIVE VCC ALDO 2:1 MUX HW_RNGSEL0, HW_RNGSEL1 CHSEL2 TO CHSEL0 SEQEN FLEXIBLE SEQUENCER BURST RESET AGND DGND DB15 TO DB0 SDOx/SDI PARALLEL FIRST- ORDER LPF RFB1MΩ 1MΩ RFB FIRST- ORDER LPF 1.8V ALDO PARALLEL/ SERIAL INTERFACE CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP
Rev. 0 | Page 2 of 50 TABLE OF CONTENTS
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 3 of 50 SPECIFICATIONS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)1, 2 89 90.5 dB 92 dB 93 dB 88 89.5 dB 85.5 87 dB Signal-to-Noise-and-Distortion (SINAD)1 88.5 90 dB 87.5 89 dB 85 87 dB Dynamic Range 92 dB 90.5 dB 88 d B Total Harmonic Distortion (THD)1 −103 −93.5 dB −100 dB fIN = 1 kHz sine wave unless otherwise noted No oversampling, ±10 V range OSR = 2, ±10 V range,3 fSAMPLE = 500 kSPS OSR = 4, ±10 V range3 No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range N o oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range −97 dB Peak Harmonic or Spurious Noise1 −103 dB Intermodulation Distortion (IMD)1 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −105 dB Third-Order Terms −113 dB Channel to Channel Isolation1 fIN on unselected channels up to 5 kHz −106 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 39 kHz −3 dB , ±5 V/2.5 V range 33 kHz −0.1 dB 5.5 kHz Phase Delay3 ±10 V r ange 4.4 6 μs ±5 V r ange 5 μs ±2.5 V r ange 4.9 μs Phase Delay Drift3 ±10 V r ange ±0.55 5 ns/°C Phase Delay Matching (Dual Simultaneous Pair)3 ±10 V range 4.4 100 ns ±5 V r ange 4.7 ns ±2.5 V range 4.1 ns DC ACCURACY Resolution No missing codes 16 Bits Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB 4 Integral Nonlinearity (INL)1 ±1 ±2 LSB Total Unadjusted Error (TUE) ±10 V range ±6 LSB ±5 V range ±8 LSB ±2.5 V range ±10 LSB Positive Full-Scale Error5 External reference ±10 V range ±5 ±32 LSB ±5 V range ± 4 LSB ±2.5 V range ± 2 LSB Internal reference ±10 V r ange ±5 LSB
Rev. 0 | Page 4 of 50 Parameter Test Conditions/Comments Min Typ Max Unit Positive Full-Scale (PFS) Error Drift3 External reference ±2 ±5 ppm/°C Internal reference ±3 ±10 ppm/°C Positive Full-Scale Error Matching1 ±10 V range 3 11 LSB ±5 V range 4 LSB ±2.5 V range 8 LSB Bipolar Zero Code Error1 ±10 V range ±0.8 ±8 LSB ±5 V range ±1 ±10 LSB ±2.5 V range ±3 ±15 LSB Bipolar Zero Code Error Drift3 ±10 V range ±1.3 ±20.4 μV/°C ±5 V range ±0.9 μV/°C ±2.5 V range ±0.5 μV/°C Bipolar Zero Code Error Matching ±10 V range ±2 ±10 LSB ±5 V range ±3 LSB ±2.5 V range ±3 LSB Negative Full-Scale (NFS) Error1, 5 External reference ±10 V range ±4 ±32 LSB ±5 V range ±3 LSB ±2.5 V range ±6 LSB Internal reference ±10 V range ±3 LSB Negative Full-Scale Error Drift3 External reference ±2 ±5 ppm/°C Internal reference ±4 ppm/°C Negative Full-Scale Error Matching1 ±10 V range 4 12 LSB ±5 V range 4 LSB ±2.5 V range 8 LSB ANALOG INPUT Input Voltage Ranges Software/hardware selectable ±10 V Software/hardware selectable ±5 V Software/hardware selectable ±2.5 V Analog Input Current ±10 V range, see Figure 34 ±10.5 μA ±5 V range, see Figure 34 ±6.5 μA ±2.5 V range, see Figure 34 ±4 μA Input Capacitance6 10 pF Input Impedance See the Analog Input section 0.85 1 MΩ Input Impedance Drift3 25 ppm/°C REFERENCE INPUT/OUTPUT Reference Input Voltage Range See the ADC Transfer Function section 2.495 2.5 2.505 V DC Leakage Current ±1 μA Input Capacitance6 REFSEL = 1 7.5 pF Reference Output Voltage REFINOUT 2.495 2.505 V Reference Temperature Coefficient3 ±2 ±15 ppm/°C LOGIC INPUTS Input Voltage High (VINH) V DRIVE = 2.7 V to 3.6 V 2 V V DRIVE = 2.3 V to 2.7 V 1.7 V Low (VINL) V DRIVE = 2.7 V to 3.6 V 0.8 V V DRIVE = 2.3 V to 2.7 V 0.7 V Input Current (IIN) ±1 μA Input Capacitance (CIN)6 5 pF
Rev. 0 | Page 5 of 50 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC OUTPUTS Output Voltage High (VOH) ISOURCE = 100 μA VDRIVE − 0.2 V Low (VOL) I SINK = 100 μA 0.4 V Floating State Leakage Current ±0.005 ±1 μA Floating State Output Capacitance6 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time Per channel pair 0.5 μs Acquisition Time Per channel pair 0.5 μs Throughput Rate Per channel pair 1 MSPS POWER REQUIREMENTS VCC 4.75 5.25 V VDRIVE 2.3 3.6 V IVCC Normal Mode Static 37 57 mA Operational f SAMPLE = 1 MSPS 42 65 mA Shutdown Mode 28 μA IDRIVE Digital inputs = 0 V or VDRIVE Normal Mode Static 0.3 0.75 mA Operational f SAMPLE = 1 MSPS 7 8 mA Shutdown Mode 50 μA Power Dissipation Normal Mode Static 185 300 mW Operational f SAMPLE = 1 MSPS 230 350 mW Shutdown Mode 0.75 mW 1 See the Terminology section. 2 The user can achieve 93 dB SNR by enabling oversampling. The values are valid for manual mode. In burst mode, values degrade by ~1 dB. 3 Not production tested. Sample tested during initial release to ensure compliance. 5 Positive and negative full-scale error for the internal reference excludes reference errors. 6 Supported by simulation data.
Interface timing tested using a load capacitance of 30 pF, dependent on VDRIVE and load capacitance for serial interface (see Table 14). 1 Not production tested. Sample tested during initial release to ensure compliance. Figure 2. Universal Timing Diagram Across All Interfaces
Figure 3. Reset Timing
1 Dependent on VDRIVE and load capacitance (see Table 14). Figure 6. Serial Timing Diagram
TA = 25°C, unless otherwise noted.
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
PCB thermal design is required. the junction to case thermal resistance. Table 6. Thermal Resistance
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51.
Figure 7. Pin Configuration Table 7. Pin Function Descriptions 1 AI GND V4BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4B. 2 AI V4B Analog Input for Channel 4, ADC B. 3 AI GND V5BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5B. 4 AI V5B Analog Input for Channel 5, ADC B. 5, 16, 29, 72 P AGND Analog Supply Ground Pins. 7 AI V6B Analog Input for Channel 6, ADC B. 8 AI GND V6BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6B. 9 AI V7B Analog Input for Channel 7, ADC B. 10 AI GND V7BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7B. 11 AI GND V7AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7A. 12 AI V7A Analog Input for Channel 7, ADC A. 13 AI GND V6AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6A. 14 AI V6A Analog Input for Channel 6, ADC A. 18 AI GND V5AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5A. 20 AI GND V4AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4A.
Rev. 0 | Page 12 of 50 Pin No. Type1 Mnemonic2 Description 21 AI GND V3AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3A. 22 AI V3A Analog Input for Channel 3, ADC A. 23 AI GND V2AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2A. 24 AI V2A Analog Input for Channel 2, ADC A. 25 AI GND V1AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1A. 26 AI V1A Analog Input for Channel 1, ADC A. 27 AI GND V0AGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0A. 28 AI V0A Analog Input for Channel 0, ADC A. 31 CAP REFCAP Reference Buffer Output Force/Sense Pin. Decouple this pin to AGND using a low effective series resistance (ESR), 10 µF, X5R ceramic capacitor, as close to the REFCAP pin as possible. The voltage on this pin is typically 4.096 V. 32 CAP REFGND Reference Ground pin. Connect this pin to AGND. 33 REF REFINOUT Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for external use when the REFSEL pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REFSEL pin to logic low, and an external reference of 2.5 V can be applied to this input. Decoupling is required on this pin for both the internal and external reference options. Connect a 100 nF, X8R capacitor between the REFINOUT and REFINOUTGND pins, as close to the REFINOUT pin as possible. If using an external reference, connect a 10 kΩ series resistor to this pin to band limit the reference signal. 34 CAP REFINOUTGND Reference Input, Reference Output Ground Pin. 35 DI REFSEL Internal/External Reference Selection Input. REFSEL is a logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFINOUT pin. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. 36 DI RESET Reset Input. Full and partial reset options are available. The type of reset is determined by the length of the RESET pulse. Keeping RESET low places the device into shutdown mode. See the Reset Functionality section for further details. 37 DI SEQEN Channel Sequencer Enable Input (Hardware Mode Only). When SEQEN is tied low, the sequencer is disabled. When SEQEN is high, the sequencer is enabled (with restricted functionality in hardware mode). See the Sequencer section for further details. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. In software mode, this pin must be connected to DGND. 38, 39 DI HW_RNGSEL1, HW_RNGSEL0 Hardware/Software Mode Selection, Hardware Mode Range Select Inputs. Hardware/software mode selection is latched at full reset. Range selection in hardware mode is not latched. HW_RNGSELx = 00: software mode; the AD7616 is configured via the software registers. HW_RNGSELx = 01: hardware mode; analog input range is ±2.5 V. HW_RNGSELx = 10: hardware mode; analog input range is ±5 V. HW_RNGSELx = 11: hardware mode; analog input range is ±10 V. 40 DI SER/PAR Serial/Parallel Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to logic high, the serial interface is selected. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. 41, 42, 43, DO/DI DB0, DB1, DB2, DB3 Parallel Output/Input Data Bit 0 to Data Bit 3. In parallel mode, these pins are output/input parallel data bits, DB7 to DB0. Refer to the Parallel Interface section for further details. In serial mode, these pins must be tied to DGND. 45 DO/DI DB4/SER1W Parallel Output/Input Data Bit 4/Serial Output Selection. In parallel mode, this pin acts as a three-state parallel digital output/input pin. Refer to the Parallel Interface section for further details. In serial mode, this pin determines whether the serial output operates over SDOA and SDOB or just SDOA. When SER1W is low, the serial output operates over SDOA only. When SER1W is high, the serial output operates over both SDOA and SDOB. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure.
Rev. 0 | Page 13 of 50 Pin No. Type1 Mnemonic2 Description 46 DO/DI DB5/CRCEN Parallel Output/Input Data Bit 5/CRC Enable Input. In parallel mode, this pin acts as a three- state parallel digital input/output. While in serial mode, this pin acts as a CRC enable input. The CRCEN signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Digital Interface section for further details. In serial mode, when CRCEN is low, there is no CRC word following the conversion results; when CRCEN is high, an extra CRC word follows the last conversion word configured by CHSELx. See the CRC section for further details. In software mode, this pin must be connected to DGND. 47, 48 DO/DI DB6, DB7 Parallel Output/Input Data Bit 6 and Data Bit 7. When SER/PAR = 0, these pins act as three- state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1 these pins must be tied to DGND. 49 P VDRIVE Logic Power Supply Input. The voltage (2.3 V to 3.6 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface. Decouple this pin with 0.1 µF and 10 µF capacitors in parallel. 50 P DGND Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7616. The DGND pin must connect to the DGND plane of a system. 51 CAP REGGNDD Ground for the Digital Low Dropout (LDO) Regulator Connected to REGCAPD (Pin 52). 52 CAP REGCAPD Decoupling Capacitor Pin for Voltage Output from Internal Digital Regulator. Decouple this output pin separately to REGGNDD using a 10 μF capacitor. The voltage at this pin is 1.89 V typical. 53, 54 DO/DI DB8, DB9 Parallel Output/Input Data Bit 9 and Data Bit 8. When SER/PAR = 0, these pins act as three- state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, these pins must be tied to DGND. 55 DO/DI DB10/SDI Parallel Output/Input Data Bit DB10/Serial Data Input. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In hardware serial mode, tie this pin to DGND. In serial mode, when SER/PAR = 1, this pin acts as the data input of the SPI interface. 56 DO/DI DB11/SDOB Parallel Output/Input Data Bit 11/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, this pin functions as SDOB and outputs serial conversion data. 57 DO/DI DB12/SDOA Parallel Output/Input Data Bit 12/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, this pin functions as SDOA and outputs serial conversion data. 58, 59, 60 DO/DI DB13/OS0, DB14/OS1, DB15/OS2 Parallel Output/Input Data Bit 13, Data Bit 14, and Data Bit 15/Oversampling Ratio Selection. When SER/ PAR = 0, these pins act as three-state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial hardware mode, these pins control the oversampling settings. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. See the Digital Filter section for further details. In software serial mode, these pins must be connected to DGND. 61 DI WR/BURST Write/Burst Mode Enable. In software parallel mode, this pin acts as WR for a parallel interface. In hardware parallel or serial mode, this pin enables BURST mode. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Burst Sequencer section for further information. In software serial mode, connect this pin to DGND. 62 DI SCLK/RD Serial Clock Input/Parallel Data Read Control Input. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the SDOA and SDOB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the SDOA and SDOB serial data outputs. When both CS and RD are logic low in parallel mode, the output bus is enabled. 63 DI CS Chip Select. This active low logic input frames the data transfer. In parallel mode, when both CS and RD are logic low, the DBx output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS frames the serial read transfer and clocks out the MSB of the serial output data.
Rev. 0 | Page 14 of 50 Pin No. Type1 Mnemonic2 Description 64, 65, 66 DI CHSEL0, CHSEL1, CHSEL2 Channel Selection Input 0 to Input 2. In hardware mode, these inputs select the input channels for the next conversion in Channel Group A and Channel Group B. For example, CHSELx = 0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and V1B for the next conversion. In software mode, these pins must be connected to DGND. 67 DO BUSY Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that the conversion process has started. The BUSY output remains high until the conversion process for the current selected channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read. Data must be read after BUSY returns to low. Rising edges on CONVST have no effect while the BUSY signal is high. 68 DI CONVST Conversion Start Input for Channel Group A and Channel Group B. This logic input initiates conversions on the analog input channels. A conversion is initiated when CONVST transitions from low to high for the selected analog input pair. When burst mode and oversampling mode are disabled, every CONVST transition from low to high converts one channel pair. In sequencer mode, when burst mode or oversampling is enabled, a single CONVST transition from low to high is necessary to perform the required number of conversions. 69 CAP REGGND Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system. 70 CAP REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V typical. 73 AI V0B Analog Input for Channel 0, ADC B. 74 AI GND V0BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0B. 75 AI V1B Analog Input for Channel 1, ADC B. 76 AI GND V1BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1B. 77 AI V2B Analog Input for Channel 2, ADC B. 78 AI GND V2BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2B. 79 AI V3B Analog Input for Channel 3, ADC B. 80 AI GND V3BGND Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3B. 1 AI is analog input, GND is ground, P is power supply, REF is reference input/output, DI is digital input, DO is digital output, and CAP is decoupling capacitor pin. 2 Note that throughout this data sheet, multifunction pins, such as SER/PAR, are referred to either by the entire pin name or by a single function of the pin, for example, SER, when only that function is relevant.
Figure 14. Typical INL Error, ±10 V Range Figure 15. Typical INL Error, ±5 V Range Figure 16. Typical DNL Error, ±10 V Range Figure 17. Typical DNL Error, ±5 V Range Figure 18. DC Histogram of Codes at Code Center, ±10 V Range Figure 19. DC Histogram of Codes at Code Center, ±5 V Range
65536 SAMPLES
Figure 20. DC Histogram of Codes at Code Center, ±2.5 V Range Figure 21. NFS Error vs. Temperature Figure 22. PFS Error vs. Temperature Figure 23. PFS/NFS Error vs. Source Resistance Figure 24. NFS/PFS Error Matching vs. Temperature Figure 25. Bipolar Zero Code Error vs. Temperature
Rev. 0 | Page 21 of 50 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Bipolar Zero Code Error Matching Bipolar zero code error matching is the absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale (PFS) Error Positive full-scale error is the deviation of the actual last code transition from the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V − 1½ LSB (4.99977) and 2.5 V − 1½ LSB (2.49989)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Matching Positive full-scale error matching is the absolute difference in positive full-scale error between any two input channels. Negative Full-Scale (NFS) Error Negative full-scale error is the deviation of the first code transition from the ideal first code transition (−10 V + ½ LSB (−2.49996)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Matching Negative full-scale error matching is the absolute difference in negative full-scale error between any two input channels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical SNR for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise Ratio = (6.02N + 1.76) dB Therefore, for a 16-bit converter, the SNR is 98 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to f S/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second- order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the VCC supply of the ADC of frequency, fS. PSRR (dB) = 10log(Pf/PfS) where: Pf is equal to the power at frequency, f, in the ADC output. PfS is equal to the power at frequency, fS, coupled onto the VCC supply.
Rev. 0 | Page 22 of 50 AC Common-Mode Rejection Ratio (AC CMRR) AC CMRR is defined as the ratio of the power in the ADC output at frequency, f, to the power of a sine wave applied to the common-mode voltage of Vxx and VxxGND at frequency, fS. AC CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied. Phase Delay Phase delay is a measure of the absolute time delay between when an input is sampled by the converter and when the result associated with that sample is available to be read back from the ADC, including delay induced by the analog front end of the device. Phase Delay Drift Phase delay drift is the change in group delay per unit temperature across the entire operating temperature of the device. Phase Delay Matching Phase delay matching is the maximum phase delay seen between any simultaneously sampled pair.
supply with a 10 µF capacitor in parallel with a 100 nF capacitor. regulators. The analog LDO (ALDO) typically supplies 1.87 V. capacitor between the REGCAPD and REGCAPDGND pins. DRIVE first, followed by VCC. Hold RESET low until both supplies are stabilized. regulators as shown in Figure 49 and as described in Table 7. Table 10. Functionality Matrix 1 Yes means available; no means not available.
Figure 49. Typical External Connections
Rev. 0 | Page 28 of 50 DEVICE CONFIGURATION OPERATIONAL MODE The mode of operation, hardware mode or software mode, is configured when the AD7616 is released from full reset. The logic level of the HW_RNGSELx pins when the RESET pin transitions from low to high determines the operational mode. The HW_RNGSELx pins are dual function. If HW_RNGSELx = 0b00, the AD7616 enters software mode. Any other combination of the HW_RNGSELx configures the AD7616 to hardware mode and the analog input range is configured as per Table 8. After software mode is configured, the logic level of the HW_RNGSELx signals is ignored. After an operational mode is configured, a full reset via the RESET pin is required to exit the operational mode and to set up an alternative mode. If hardware mode is selected, all further device configuration is via pin control. Access to the on-chip registers is prohibited in hardware mode. In software mode, the interface and reference configuration must be configured via pin control but all further device configuration is via register access only. INTERNAL/EXTERNAL REFERENCE The internal reference is enabled or disabled when the AD7616 is released from a full reset. The logic level of the REFSEL signal when the RESET pin transitions from low to high configures the reference. After the reference is configured, changes to the logic level of the REFSEL signal are ignored. If the REFSEL signal is set to 1, the internal reference is enabled. If REFSEL is set to Logic 0, the internal reference is disabled and an external reference must be supplied to the REFINOUT pin for correct operation of the AD7616. A full reset via the RESET pin is required to exit the operational mode and set up an alternative mode. Connect a 100 nF capacitor between the REFINOUT and REFINOUTGND pins. If using an external reference, place a 10 kΩ band limiting resistor in series between the reference and the REFINOUT pin of the AD7616. DIGITAL INTERFACE The digital interface selection, parallel or serial, is configured when the AD7616 is released from a full reset. The logic level of the SER/PAR signal when the RESET pin transitions from low to high configures the interface. If the SER/PAR signal is set to 0, the parallel interface is enabled. If the SER/PAR signal is set to 1, the serial interface is selected. Additionally, if the serial interface is selected, the SER1W signal is monitored when the RESET pin is released to determine if serial 1-wire or 2-wire mode is selected. After the interface is configured, changes to the logic level of the SER/PA R signal or the SER1W signal (when the serial interface is enabled) are ignored. A full reset via the RESET pin is required to exit the operation mode and set up an alternative mode. HARDWARE MODE If hardware mode is selected, the available functionality is restricted and all functionality is configured via pin control. The logic level of the following signals is checked after a full reset to configure the functionality of the AD7616: CRC, BURST, SEQEN, and OSx. Table 11 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. After the device is configured, a full reset via the RESET pin is required to exit the configuration and set up an alternative configuration. Functionality availability is restricted depending on the interface type selected. See Table 10 for a full list of the functionality available in hardware parallel or serial mode. The CHSELx pins are queried at reset to determine the initial analog input channel pair to acquire for conversion or to configure the initial settings for the sequencer. The channel pair selected for conversion or the hardware sequencer can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge until the BUSY falling edge. The HW_RNGSELx signals control the analog input range for all 16 analog input channels. A logic change on these pins has an immediate effect on the analog input range; however, the typical settling time is approximately 120 µs, in addition to the normal acquisition time requirement. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. Access to the on-chip registers is prohibited in hardware mode.
Table 11. Summary of Latched Hardware Signals1 1 Blank cells in Table 11 mean not applicable. mode selected is dependent on the length of the reset low pulse. requires the RESET pin to be held low for a minimum of 1.2 µs. reconfigured and a conversion can be initiated.
- Sequencer
- Digital filter
- SPI
- Both SAR ADCs The current conversion result is discarded on completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. A dummy conversion is required in software mode after a partial reset. A full reset returns the device to its default power-on state. The following features are configured when the AD7616 is released from full reset:
- Hardware mode or software mode
- Internal/external reference
- Interface type On power-up, the RESET signal can be released as soon as both the VCC and VDRIVE supplies are stable. The logic level of the HW_RNGSELx, REFSEL, SER/PAR and DB4/SER1W pins when the RESET pin is released after a full reset determines the configuration. If hardware mode is selected, the functionality determined by the CRC, BURSTEN, SEQEN, and OSx signals is also latched when the RESET pin transitions from low to high in full reset mode. After the functionality is configured, changes to these signals are ignored. In hardware mode, the analog input range (HW_RNGSELx signals) can be configured during either a full or partial reset or during normal operation, but hardware/software mode selection requires a full reset to reconfigure while this setting is latched. In hardware mode, the CHSELx and HW_RNGSELx pins are queried at release from both a full and a partial reset to perform the following actions:
- Determine the initial analog input channel pair to acquire for conversion.
- Configure the initial settings for the sequencer.
- Select the analog input voltage range.
controlling the on-chip registers. in the different modes of operation and interface modes. Figure 50. AD7616 Configuration at Reset Table 12. Pin Functionality Overview
1-wire or serial 2-wire mode. results from Channel V0B to Channel V7B appear on SDOB. throughput, it is required to use 2-wire mode. configured when the AD7616 is released from full reset. possible to read back conversion results on the serial interface.
32 SCLK cycles using one CS
of using just one SDOx line is that the throughput rate is reduced. channel results are output in the following order: VxA and VxB. Figure 58 shows a 1-wire, serial readback operation. summary of the maximum speed achievable for various conditions. Table 14. SPI Frequency vs. Load Capacitance and VDRIVE Figure 57. Serial Interface, 2-Wire Mode Figure 58. Serial Interface, 1-Wire Mode
address. The subsequent nine bits (Bits[D8:D0]) are ignored. addresses. Figure 60 shows a typical serial read command. Figure 59. Serial Interface Register Write Figure 60. Serial Interface Register Read Table 15. Write Command Message Configuration
1 Register address Data to write
Table 16. Read Command Message Configuration
0 Register address Do not care
The AD7616 features a highly configurable on-chip sequencer. dependent on the mode of operation of the AD7616. paired with any Channel VxB input or diagnostic channel. function and set up an alternative configuration. Table 17. Hardware Mode Sequencer Configuration
0 Sequencer disabled
1 Sequencer enabled
determine the channels selected for conversion in the sequence. complete. See Figure 61 for further details. Table 18. CHSELx Pin Decoding Sequencer sequencer stack registers via the parallel or serial interface. sequencer depth can be set to any length from 1 to 32 layers. register for the depth required. configuration register to 1. Figure 61. Hardware Mode Sequencer Configuration
- Configure the analog input range for the required analog
- Program the sequencer stack registers to select the
- Set the SSRENx bit in the last required sequence step.
- Set the SEQEN bit in the configuration register.
- Provide a dummy CONVST pulse.
- Cycle through CONVST pulses and conversion reads to step
through each element of the sequencer stack. the sequencer stack with the next CONVST pulse. is the case when the burst function is disabled. results are available for readback after the BUSY pin goes low. sequence is dependent on the length of the sequence configured. serial) in the same order as the programmed sequence. tCONV is the typical conversion time. tACQ is typical acquisition time. either serial 1-wire, serial 2-wire, or parallel mode. to 1. The SEQEN pin must also be set to 1 to enable the sequencer. function and set up an alternative configuration. Figure 62. Software Mode Sequencer Configuration
via an extra read command over the serial or parallel interface. Figure 68. CRC Readback for All Modes
converted and the CRC result. Table 19. Register Summary1
2 R/W
remaining 24 layers of the stack are reinitialized to 0x0.
Rev. 0 | Page 41 of 50 ADDRESSING REGISTERS The seven MSBs written to the device are decoded to determine which register is addressed. The seven MSBs consist of the register address (REGADDR), Bits[5:0], and the read/write bit. The register address bits determine which on-chip register is selected. The read/write bit determines if the remaining nine bits of data on the DB10/SDI lines are loaded into the addressed register. If the read/write bit is 1, the bits load into the register addressed by the register select bits. If the read/write bit is 0, the command is seen as a read request. The addressed register data is available to be read during the next read operation. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 to D0 W/R REGADDR[5] REGADDR[4] REGADDR[3] REGADDR[2] REGADDR[1] REGADDR[0] DATA[8:0] Table 20. Bit s Mnemonic Description D15 W/R If a 1 is written to this bit, Bits[D8:D0] of this register are written to the register specified by REGADDR[5:0]. Alternatively, if a 0 is written, the next operation is a read from the designated register. D14 REGADDR[5] If a 1 is written to this bit, the contents of REGADDR[4:0] specifies the 32 sequencer stack registers. Alternatively, if a 0 is written to this bit, a register is selected as defined by REGADDR[4:0]. [D13:D9] REGADDR[4:0] When W/R =1, the contents of REGADDR[4:0] determine register for selection as follows: 00001: reserved. 00010: selects the configuration register. 00011: selects the channel register. 00100: selects Input Range Register A1. 00101: selects Input Range Register A2. 00110: selects Input Range Register B1. 00111: selects Input Range Register B2. 01000: selects the status register When W/R = 0, and REGADDR[4:0] contains 00000, the conversion codes are read. [D8:D0] DATA[8:0] These bits are written into the corresponding register specified by Bits REGADDR[5:0]. See the following sections for detailed descriptions of each register.
mode, oversampling, and CRC options. Table 21. Bit Descriptions for the Configuration Register section for further details. 0 Test passed. The AD7616 has configured itself successfully after power-up. 1 Test failed. An issue was detected during device configuration. A reset is required. 0 Burst mode is disabled. Each channel pair to be converted requires a CNVST pulse.
1 A single CNVST pulse converts every channel pair programmed in the 32-layer
0 The channel sequencer is disabled. 1 The channel sequencer is enabled. 001 Oversampling enabled, OSR = 2. 010 Oversampling enabled, OSR = 4. 011 Oversampling enabled, OSR = 8. 100 Oversampling enabled, OSR = 16. 101 Oversampling enabled, OSR = 32. 110 Oversampling enabled, OSR = 64. 111 Oversampling enabled, OSR = 128. 0 The status register is not read out when reading the conversion result.
1 The status register is read out at the end of all the conversion words (including the
out. The CRC result is included in the last eight bits.
In software manual mode, the channel register selects the input channel or self test channel for the next conversion. Table 22. Bit Descriptions for the Channel Register section for further details. [7:4] CHB Channel selection bits for ADC B channels. Channel A, and Code 0x5555 is output as the conversion code of Channel B.
input ranges (±10 V , ±5 V, or ±2.5 V) for analog input Channel V0B to Channel V7B. Table 23. Bit Descriptions for Input Range Register A1 section for further details.
Table 24. Bit Descriptions for Input Range Register A2 section for further details.
Table 25. Bit Descriptions for Input Range Register B1 section for further details.
Table 26. Bit Descriptions for Input Range Register B2 section for further details.
sequencer stack register, the user can define a pair of analog inputs to sample simultaneously. through Channel V0A and Channel V0B to Channel V7A and Channel V7B. Table 27. Bit Descriptions for Sequencer Stack Registers[0:31] section for further details.
8 SSREN[0:31] Setting this bit to 0 instructs the ADC to move to the next layer of the sequencer
sequencer loops back to the first layer of the stack. Channel A, and Code 0x5555 is output as the conversion code of Channel B. remaining 24 layers of the stack are reinitialized to 0x0.
sequencer mode. Consult the CRC section and Figure 68. Table 28. Bit Descriptions for Status Register
Figure 69. 80-Lead Low Profile Quad Flat Package [LQFP] registered trademarks are the property of their respective owners.