AD7610BSTZ

AD7610_17 AD | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 33

Technical content

16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC Data Sheet AD7610 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Multiple pins/software programmable input ranges:

5 V, 10 V, ±5 V, ±10 V

Pins or serial SPI®-compatible input ranges/mode selection Throughput: 250 kSPS 16-bit resolution with no missing codes INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR) SNR: 94 dB @ 2 kHz iCMOS® process technology

5 V internal reference: typical drift 3 ppm/°C;

On-chip temperature sensor No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation 90 mW @ 250 kSPS 10 mW @ 1 kSPS 48-lead LQFP and LFCSP (7 mm × 7 mm) packages

APPLICATIONS

High speed data acquisition Digital signal processing Instrumentation Spectrum analysis ATE FUNCTIONAL BLOCK DIAGRAM CLOCK AD7610 DGNDDVDD AVDD AGND REF REFGND IN+ PD RESET CNVST PDBUF REFBUFIN PDREF REF TEMP D[15:0] BUSY RD CS OB/2C OGND OVDD BYTESWAP SER/PAR REF AMP SWITCHED CAP DAC VCC VEE BIPOLAR TEN IN– SERIAL CONFIGURATION PORT PARALLEL INTERFACE SERIAL DATAPORT CONTROL LOGIC AND CALIBRATION CIRCUITRY 06395-001 Figure 1. GENERAL DESCRIPTION The AD7610 is a 16-bit charge redistribution successive approxi- mation register (SAR), architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc. ’s iCMOS high voltage process. The device is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. The AD7610 contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the analog input on IN+ with respect to a ground sense, IN−. The AD7610 features four different analog input ranges: 0 V to 5 V , 0 V t o 1 0 V, ±5 V, a n d ±1 0 V. Power consumption is scaled linearly with throughput. The device is available in Pb-free 48-lead, low- profile quad flat package (LQFP) and a lead frame chip-scale (LFCSP_VQ) package. Operation is specified from −40°C to +85°C. Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection

AD7610* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

AD7610 Evaluation Kit DOCUMENTATION Application Notes
AN-1141: Powering a Dual Supply Precision ADC with Switching Regulators
AN-742: Frequency Domain Response of Switched- Capacitor ADCs
AN-931: Understanding PulSAR ADC Support Circuitry
AN-932: Power Supply Sequencing Data Sheet
AD7610: 16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC Data Sheet Technical Books
The Data Conversion Handbook, 2005 REFERENCE MATERIALS Product Selection Guide
SAR ADC & Driver Quick-Match Guide Technical Articles
MS-1779: Nine Often Overlooked ADC Specifications
MS-2210: Designing Power Supplies for High Speed ADC Tutorials
MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design
MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND" DESIGN RESOURCES
AD7610 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints DISCUSSIONS View all AD7610 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. A | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

12/12—Rev. 0 to Rev. A 10/06—Revision 0: Initial V ersion

Rev. A | Page 3 of 32 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V VIN+ − VIN− = 0 V to 10 V −0.1 +10.1 V VIN+ − VIN− = ±5 V −5.1 +5.1 V VIN− to AGND −0.1 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB Input Current VIN = ±5 V, ±10 V @ 250 kSPS 1001 µA Input Impedance See Analog Inputs section THROUGHPUT SPEED Complete Cycle 4 μs Throughput Rate 250 kSPS DC ACCURACY Integral Linearity Error2 −1.5 ±0.75 +1.5 LSB3 No Missing Codes2 16 Bits Differential Linearity Error2 −1 +1.5 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −35 +35 LSB Zero Error Temperature Drift ±1 ppm/°C Bipolar Full-Scale Error −50 +50 LSB Unipolar Full-Scale Error −70 +70 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB AC ACCURACY Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB4 VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB 94 dB VIN = ±10 V, fIN = 2 kHz, −60 dB 94.5 dB Signal-to-Noise Ratio VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz 92 93 dB VIN = ±5 V, ±10 V, fIN = 2 kHz 94 dB VIN = 0 V to 5 V, fIN = 20 kHz 93.5 dB Signal-to-(Noise + Distortion) (SINAD) VIN = ±5 V, fIN = 2 kHz 92.5 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz 93 dB VIN = ±10 V, fIN = 2 kHz 93.5 dB Total Harmonic Distortion fIN = 2 kHz −107 dB Spurious-Free Dynamic Range fIN = 2 kHz 107 dB –3 dB Input Bandwidth VIN = 0 V to 5 V 650 kHz Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 22 µF 10 ms REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V

Rev. A | Page 4 of 32 Parameter Conditions/Comments Min Typ Max Unit EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 250 kSPS throughput 30 µA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels VIL −0.3 +0.6 V VIH 2.1 OVDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format Parallel or serial 16-bit Pipeline Delay5 VOL ISINK = 500 µA 0.4 V VOH ISOURCE = –500 µA OVDD − 0.6 V POWER SUPPLIES Specified Performance AVDD 4.756 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V Operating Current7, 8 @ 250 kSPS throughput AVDD With Internal Reference 8 mA With Internal Reference Disabled 6.3 mA DVDD 3.3 mA OVDD 0.3 mA VCC VCC = 15 V, with internal reference buffer 1.4 mA VCC = 15 V 0.8 mA VEE VEE = −15 V 0.7 mA Power Dissipation @ 250 kSPS throughput With Internal Reference PDREF = PDBUF = low 90 110 mW With Internal Reference Disabled PDREF = PDBUF = high 70 90 mW In Power-Down Mode9 PD = high 10 µW TEMPERATURE RANGE10 Specified Performance TMIN to TMAX −40 +85 °C 1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or VREF – 0.1 V, whichever is larger. 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range.

Rev. A | Page 5 of 32 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 33 and Figure 34) Convert Pulse Width t1 10 ns Time Between Conversions t2 4 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High (Except Master Serial Read After Convert) t4 1.45 μs Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 1.45 μs Acquisition Time t8 380 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 35 and Figure 37) CNVST Low to DATA Valid Delay t10 1.41 μs DATA Valid to BUSY Low Delay t11 20 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES1 (See Figure 39 and Figure 40) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SDCLK Valid Delay1 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 560 ns SYNC Asserted to SDCLK First Edge Delay t18 3 ns Internal SDCLK Period2 t19 30 45 ns Internal SDCLK High2 t20 15 ns Internal SDCLK Low2 t21 10 ns SDOUT Valid Setup Time2 t22 4 ns SDOUT Valid Hold Time2 t23 5 ns SDCLK Last Edge to SYNC Delay2 t24 5 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SDCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns BUSY High in Master Serial Read After Convert2 t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert t29 1.31 μs SYNC Deasserted to BUSY Low Delay t30 25 ns SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1 (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t32 2 18 ns SDIN/SCIN Setup Time t33 5 ns SDIN/SCIN Hold Time t34 5 ns External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2 In serial master read during convert mode. See Table 4 for serial mode read after convert mode.

Rev. A | Page 7 of 32 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs/Outputs IN+, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V REF, REFBUFIN, TEMP , REFGND to AGND AVDD + 0.3 V to AGND − 0.3 V Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD +0.3 V PDREF , PDBUF2 ±20 mA Internal Power Dissipation3 700 mW Internal Power Dissipation4 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 See the Analog Inputs section. 2 See the Voltage Reference Input section.

3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,

θJC = 30°C/W. 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.

FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED

REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 4. Pin Configuration Table 6. Pin Function Descriptions OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. the MSB is inverted resulting in a twos complement output from its internal shift register. connected to the system digital ground ideally at the same potential as AGND and DGND. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. the remaining data bits are high impedance outputs. 11, 12 D[2:3] or DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. external (slave) serial data clock for the AD7610 output data. When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output. connected to the SDCLK input.

Rev. A | Page 9 of 32 Pin No. Mnemonic Type1 Description 14 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 or DI/O In parallel mode, this output is used as Bit 6 of the parallel port data output bus. INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select the read mode. See the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy- chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode). When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. 22 D9 or DI/O In parallel mode, this output is used as Bit 9 of the parallel port data output bus. SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D10 or DO In parallel mode, this output is used as Bit 10 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 24 D11 or DO In parallel mode, this output is used as Bit 11 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7610 is configured through software using the serial configuration register. When HW/SW = high, the AD7610 is configured through dedicated hardware input pins. 26 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section.

Rev. A | Page 10 of 32 Pin No. Mnemonic Type1 Description 27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus. SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus. SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low) the busy time changes according to Table 4. 30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN

0 V to 5 V Low Low

0 V to 10 V Low High

±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). 33 RESET DI Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 34 PD DI2 Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 BIPOLAR DI2 Input Range Select. See description for Pin 30. 37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the internal reference and buffer. See the Reference Decoupling section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. 39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground. 40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI Analog Input. Referenced to IN−. 45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF = low). See the Temperature Sensor section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 49 EPAD3 NC Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered to VEE. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. 3 LFCSP_VQ package only.

Rev. A | Page 15 of 32 TERMINOLOGY Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For an analog-to-digital con- verter with N bits of resolution, the LSB expressed in volts is N INp-p maxV LSB 2 )V( = Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive full- scale. The point used as negative full-scale occurs a ½ LSB before the first code transition. Positive full-scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is meas- ured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Bipolar Zero Error The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Unipolar Offset Error The first transition should occur at a level ½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point. Full-Scale Error The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full-scale. The full- scale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. Closely related is the gain error (also in LSB or % of full-scale range), which does not include the effects of the offset error. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINAD dB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7610 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V REF) meas- ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as 610 C25 ((Cppm/ × )T–T()(V )MinV–)MaxV)(TCV MINMAXREF REFREF REF where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C.

Figure 25. ADC Simplified Schematic digital-to-analog converter (CDAC) architecture. power cycling is not required for reconfiguring the ADC. throughput making it useful for battery powered systems. which can be interfaced to either 5 V , 3.3 V , or 2.5 V digital logic. parallel or serial SPI-compatible interface. to the two comparator inputs. comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. REF/2, VREF/4 through VREF/65536). the ADC output code and brings the BUSY output low.

OB/2C input is a don’t care and should be tied to either high or low. Figure 26. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages 1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). 2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND).

0 TO 5V

Figure 28. AD7610 Simplified Analog Input the part although most op amps’ short circuit current is <100 mA. from the higher voltage ranges. Figure 29, which represents the typical CMRR over frequency. Figure 29. Analog Input CMRR vs. Frequency comprised of serial resistors and the on resistance of the switches. directly driven by a low impedance source without gain error.

For multichannel, multiplexed applications, the driver amplifier and the AD7610 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). For the amplifier, settling at 0.1% to 0.01% is more commonly specified. This differs significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The AD8021 op amp combines ultra- low noise and high gain bandwidth and meets this settling time requirement even when used with gains of up to 13.
The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7610. The noise coming from the driver is filtered by the external 1-pole low-pass filter as shown in Figure 27. The SNR degradation due to the amplifier is ( )  log20 NdBNADC NADC LOSS NefV VSNR where: VNADC is the noise of the ADC, which is: 2010 SNR INp-p NADC V V = f–3dB is the cutoff frequency of the input filter (3.9 MHz). N is the noise factor of the amplifier (+1 in buffer configuration). eN is the equivalent input voltage noise density of the op amp, in nV/√Hz.
The driver needs to have a THD performance suitable to that of the AD7610. Figure 15 shows the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in appli- cations where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. Since the AD7610 uses a large geometry, high voltage input switch, the best linearity performance is obtained when using the amplifier at its maximum full power bandwidth. Gaining the amplifier to make use of the more dynamic range of the ADC results in increased linearity errors. For applications requiring more resolution, the use of an additional amplifier with gain should precede a unity follower driving the AD7610. See Table 8 for a list of recommended op amps.

Table 8. Recommended Driver Amplifiers linearity performance is guaranteed only with an external reference.

The BYTESW AP pin allows a glueless interface to an 8-bit bus. can be used in both master and slave parallel reading modes. Figure 38. 8-Bit and 16-Bit Parallel Interface serial interface when SER/PAR is held high. The AD7610 outputs 16 bits of data, MSB first, on the SDOUT pin. falling edge of the data clock. INVSCLK, RDC, SDOUT, SDCLK and SYNC. Setting RDC = low, allows the read after conversion mode. periods and the host should use an SPI interface.

the software configuration mode. coding, and power-down using the serial configuration register. See Table 9 for details of each bit in the configuration register. SDCLK) is edge sensitive depending on the state of INVSCLK. master and serial slave read during and read after convert modes. Note that at power up, the configuration register is undefined. mode, and twos complemented output. Table 9. Configuration Register Description 6 TEN Input Range Select. See Bit 7, BIPOLAR.

2 OB/2C Output Coding

OB/2C = Low, use twos complement output. OB/2C = High, use straight binary output. Figure 44. Hardware Configuration Timing

Rev. A | Page 30 of 32

APPLICATION INFORMATION

While the AD7610 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facil- itate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7610 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7610, or as close as possible to the AD7610. If the AD7610 is in a system where multiple devices require analog-to-digital ground connect- ions, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7610. To prevent coupling noise onto the die, avoid radiating noise, and to reduce feedthrough:

Do not run digital lines under the device.
Do run the analog ground plane under the AD7610.
Do shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths.
Avoid crossover of digital and analog signals.
Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7610 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7610, and to reduce the magnitude of the supply spikes. Decoupled ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7610 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. See Figure 27 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7610 has four different ground pins: REFGND, AGND, DGND, and OGND.
REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference.
AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane.
DGND must be tied to the analog or digital ground plane depending on the configuration.
OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING PERFORMANCE A recommended layout for the AD7610 is outlined in the EV AL- AD7610EDZ evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the E VA L-CED1Z.

Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]

0.80 MAX

0.65 TYP

5.50 REF

0.20 REF

0.02 NOM

0.60 MAX

0.25 MIN

Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the ED designators.

Summary

16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC 23-Feb-2017

Description