AD760

AD760 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 13

Technical content

a 16/18-Bit Self-Calibrating Serial/Byte DACPORT AD760

FEATURES

±0.2 LSB (±0.00031%) Typ Peak DNL and INL ±0.5 LSB (±0.00076%) Typ Unipolar Offset, Bipolar Zero 17-Bit Monotonicity Guaranteed 18-Bit Resolution (in Serial Mode) Complete 16/18-Bit D/A Function On-Chip Output Amplifier On-Chip Buried Zener Voltage Reference Microprocessor Compatible Serial or Byte Input Double Buffered Latches Asynchronous Clear Function Serial Output Pin Facilitates Daisy Chaining Pin Strappable Unipolar or Bipolar Output Low THD+N: 0.005% MUX Output Control on Power-Up and Supply Glitches +10V REF 10k SOUT SPAN/ BIP OFF V OUT9.95k LDAC REF IN REF OUT HBE SER CLR 10k AD760 UNI/ BIP CLR OR LBE MUX OUT MUX IN AGND SIN OR DB0 DB2 DB7CS MSB/ LSB OR DB1 SERIAL OR MAIN DAC CONTROL LOGIC RAM CALIBRATION SEQUENCER CALOK –V EE +VCC +VLL DGNDCAL 1 2 3 5 64 16/18-BIT INPUT REGISTER 13 7 CALIBRATION DAC 16/18-BIT DAC LATCH Typical Integral Nonlinearity DACPORT is a registered trademark of Analog Devices, Inc. 0.75 0.25 –0.25 –0.75 0 16384 32768 49152 65535 INPUT CODE – Decimal RELATIVE ACCURACY – LSB VOUT = –10V TO +10V R L = 2kΩ C L = 1000pF MUX output in a predetermined state by means of a digital and analog power supply detection circuit. T his is particularly use- ful for robotic and industrial control applications. The AD760 is available in a 28-pin, 600 mil cerdip package. The AQ version is specified from –40°C to +85°C. PRODUCT DESCRIPTION The AD760 is a complete 16/18-bit self-calibrating monolithic DAC (DACPORT®) with onboard voltage reference, double buffered latches and output amplifier. It is manufactured on Analog Devices’ BiMOS II process. This process allows the fab- rication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. Self-calibration is initiated by simply pulsing the CAL pin low. The CALOK pin indicates when calibration has been success- fully completed. The output multiplexer (MUXOUT) can be used to send the output to the bottom of the output range during calibration. Data can be loaded into the AD760 as straight binary, serial data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data can be used and the serial mode input format is pin selectable, to be MSB or LSB first. This is made possible by three digital input pins which have dual functions (Pins 12, 13, and 14). In byte mode the user can similarly define whether the high byte or low byte is loaded first. The serial output (S OUT) pin allows the user to daisy chain several AD760s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required in a multiple DAC application. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. The asynchronous CLR function can be configured to clear the output to minus full-scale or midscale depending on the state of Pin 17 when CLR is strobed. The AD760 also powers up with the Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

TRANSFER FUNCTION CHARACTERISTICS 2 With Calibration @ T CAL 3; –40°C T CAL +85°C Integral Nonlinearity ±0.2 ±0.75 16-Bit LSB Differential Nonlinearity ±0.2 ±0.5 16-Bit LSB Monotonicity 17 18 Bits Unipolar Offset ±0.5 ±1 16-Bit LSB Bipolar Zero Error ±0.5 ±1 16-Bit LSB Without Calibration Integral Nonlinearity ±2 16-Bit LSB TMIN to TMAX ±4 16-Bit LSB Integral Nonlinearity Drift 0.015 16-Bit LSB/°C Differential Nonlinearity ±2 16-Bit LSB TMIN to TMAX ±4 16-Bit LSB Differential Nonlinearity Drift 0.015 16-Bit LSB/°C Monotonicity Over Temperature 14 Bits Unipolar Offset ±2.5 mV Unipolar Offset Drift (T MIN to TMAX) 3 ppm/°C Bipolar Zero Error ±10 mV Bipolar Zero Error Drift (T MIN to TMAX) 5 ppm/°C Gain Error4, 5 ±0.125 % of FSR Gain Drift5 (TMIN to TMAX) 25 ppm/°C DAC Gain Error6 ±0.08 % of FSR DAC Gain Drift6 (TMIN to TMAX) 10 ppm/°C INPUT RESISTANCE REFIN 7 10 13 k SPAN/BIP OFF 7 10 13 k REFERENCE OUTPUT Voltage 9.99 10.00 10.01 V Drift 25 ppm/°C External Current 7 24 mA Capacitive Load 1000 pF Short Circuit Current 25 mA Long-Term Stability 50 ppm/1000 Hrs OUTPUT CHARACTERISTICS 2 Output Voltage Range Unipolar Configuration 0 +10 V Bipolar Configuration –10 +10 V Output Current 5 mA Capacitive Load 1000 pF Short Circuit Current 25 mA MUXOUT Resistance 0.9 7 k DIGITAL INPUTS (T MIN to TMAX) VIH (Logic “1”) 2.0 VLL V VIL (Logic “0”) 0 0.8 V IIH (VIH = VLL) ±10 µA IIL (VIL = 0 V) ±10 µA DIGITAL OUTPUT (T MIN to TMAX) VOH (IOH = –0.6 mA) 2.4 V VOL (IOL = 1.6 mA) 0.4 V POWER SUPPLIES Voltage VCC 8 +14.25 +15.75 V VEE 8 –15.75 –14.25 V VLL +4.75 +5.25 V Current (No Load) ICC +18 +21 mA IEE –21 –18 mA ILL @ VIH, VIL = 5.0 V, 0 V 2 3 mA @ VIH, VIL = 2.4 V, 0.4 V 3 7.5 mA Power Supply Sensitivity with V OUT = 10 V 1 ppm/% Power Dissipation (Static, No Load) 600 725 mW TEMPERATURE RANGE Specified Performance (A) –40 +85 °C AD760–SPECIFICATIONS –2– (@ TA = +25°C, V CC = +15 V, VEE = –15 V, V LL = + 5 V, unless otherwise noted) REV. B

–3– NOTES full-scale range and is 10 V in unipolar mode and 20 V in bipolar mode. 2Characteristics are guaranteed at V OUT Pin (23). 3TCAL is the calibration temperature. 4Gain Error is measured with a fixed 50 resistor as shown in Figure 5a and Figure 6a. 5Gain Error and gain drift are measured with the internal reference. The internal reference is the main contributor to the gain drift. If lower drift is required, the AD760 can be used with a precision external reference such as the AD587, AD586 or AD688. 6DAC Gain Error is measured without the on-chip voltage reference. It represents the performance that can be obtained with an external precision reference. 7External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD760. 8Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS Parameter Limit Units Test Conditions/Comments Output Settling Time 13 µs max 20 V Step, T A = +25°C (Time to +0.0008% FS, with 8 µs typ 20 V Step, T A = +25°C 2 k , 1000 pF Load) 10 µs typ 20 V Step 6 µs typ 10 V Step, T A = +25°C 8 µs typ 10 V Step 2.5 µs typ 1 LSB Step MUXOUT Recovery Time Recovery time is referenced to the rising edge of CALOK, (Time to +0.0008% FS, with when MUXOUT switches from MUX IN to VOUT. 100 pF Load) MUX IN = VOUT prior to calibration. 2 µs typ MUX IN, VOUT = –10 V to +10 V Total Harmonic Distortion + Noise A, S Grade 0.005 % max 0 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25°C A, S Grade 0.03 % max –20 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25°C A, S Grade 3.0 % max –60 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25°C Signal-to-Noise Ratio 94 dB min T A = +25°C, byte load Digital-to-Analog Glitch Impulse 15 nV-s typ DAC alternately loaded with 8000 H and 7FFFH MUXOUT Glitch Impulse 30 nV-s typ 100 pF Load. MUX IN = VOUT = negative full scale Digital Feedthrough 2 nV-s typ DAC alternately loaded with 0000 H and FFFFH. CS high Output Noise Voltage Density (1 kHz–1 MHz) 120 nV/ Hz typ Measured at V OUT, 20 V span, excludes internal reference Reference Noise (1 kHz–1 MHz) 125 nV/ Hz typ Measured at REF OUT Specifications are subject to change without notice. With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. (T MIN < TA < TMAX, VCC = +15 V, VEE = –15 V, V LL = +5 V, tested at VOUT except where noted.) REV. B

in Figure 2 shows the circuit components needed for calibration. tional to the applied digital word, ranging from 0 mA to 2 mA. the MAIN DAC, for use during calibration. rors (DNL errors) associated with the upper 6 bits (64 codes). the summing amplifier to produce the corrected output voltage. Figure 2. Functional Block Diagram DAC is set to the code just below the code to be calibrated. has in effect been sampled at the code to be calibrated. stored in RAM and the process is repeated for the next code. also referred to as relative accuracy. loaded after offset error has been adjusted out. measured with all 0s loaded in the DAC. called the bipolar zero error. OUT pin. This noise is digital feedthrough.

the second rank register from the first rank register. Figure 8. Output Characteristics is useful when applying the AD760. lowing section for using the output multiplexer. be reflected in the DAC output immediately. to be set to the uncalibrated state. tied low. For 18-bit operation Pin 12 must be tied high. will shift the data out through S OUT and into the next DAC. all of the DACs are to be updated simultaneously.

–12– AD760 One feature that the AD760 incorporates to help the user layout is that the analog pins (V CC, VEE, REF OUT, REF IN, SPAN/ BIP OFFSET, VOUT, MUXOUT, MUXIN and AGND) are adja- cent to help isolate analog signals from digital signals. SUPPLY DECOUPLING The AD760 power supplies should be well filtered, well regu- lated, and free from high frequency noise. Switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. A 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor provides ad- equate decoupling. V CC and VEE should be bypassed to analog ground, while VLL should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD760, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD760 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. GROUNDING The AD760 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the “high quality” ground reference point for the device. Any exter- nal loads on the output of the AD760 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground. If a single AD760 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD760. If multiple AD760s are used or the AD760 shares ana- log supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground. REV. B

Rev. B | Page 13 of 13 OUTLINE DIMENSIONS CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 11 4 0.610 (15.49) 0.500 (12.70) 0.005 (0.13) MIN 0.100 (2.54) MAX 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) SEATING PLANE 0.225(5.72) MAX 1.490 (37.85) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) MIN 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 15° PIN 1 030106-A Figure 15. 28-Lead Ceramic Dual In-Line Package [CERDIP]

REVISION HISTORY

9/2018—Rev. A to Rev. B Changes to Gain Error Parameter and DAC Gain Error ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D17226-0-9/18(B)