AD7520 AD | Alldatasheet
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Technical content
g ANALOG CMOS 10&12-Bit Monolithic
FEATURES
AD7520: 10 Bit Resolution il AD7521: 12 Bit Resolution : Linearity: 8, 9 and 10 Bit pe 8G ss mamas Nonlinearity Tempco: 2ppm of FSR/°C . ay Low Power Dissipation: 20mW a 7 Current Settling Time: 500ns 5. “ye fl ie . 7 °Y Feedthrough Error: 1/2LSB @ 100kHz a =k TTL/DTL/CMOS Compatible fer aed (q & —] Te IF be aren Il ST . Bi z.. GENERAL DESCRIPTION FUNCTIONAL DIAGRAM The AD7520 (AD7521) is a low cost, monolithic 10-bit (12-bit) multiplying digital-to-analog converter packaged in Vacs O ARK wa AX a 16-pin (18-pin) DIP. The devices use advanced CMOS and thin film technologies providing up to 10-bit accuracy with 20k 20k 20k TTL/DTL/CMOS compatibility. The AD7520 (AD7521) operates from +5V to +15V supply p P pe psn and dissipates only 20mW, including the ladder network. si SiO SiO i Typical AD7520 (AD7521) applications include: digital/ ' 1 lourz analog multiplication, CRT character generation, program- a J lout: mable power supplies, digitally controlled gain circuits, etc. ! | V TT sox ' ' ' ! Rreepeack 6 6. 4 } BIT 1 (MSB) BIT 2 BIT3 BIT N (LSB)
ORDERING INFORMATION
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) Nonlinearity Temperature Range AD7520: N=10 -25°C to +35°C | -55°C to +125°C AD7521: N=12 “om (enie AD7520)N | AD7520)D ‘AD7520SD_—_ Logic: A switch is closed to ours for its AD7521JN AD7521JD AD7521SD digital input in a “HIGH” state. AD7520KN AD7520KD AD7520TD 7 0.1% (9-Bit) ADIS21KD ADIS21TD PIN CONFIGURATION — ToP VIEW 0.05% (10-Bit) AD7520LN AD7520LD AD7520UD AD7520 ADTS21 AD7521LN AD7521LD AD7521UD oun EE] ® [76] Preeooack oun (7 [78) Freeosack: ‘oun GY [15] Ver four [2 Veer (N ono Fig) Vo (4 ono [ [38] Yoo «1 ar 1 sa) [| Fa} ar wasy ort aso LS [35] ovr 2 ase ar? el Fi] airs a2 (B [a] ora PACKAGE IDENTIFICATION nated Haj errs a3 CE Ear 0 es 4 [22 an Suffix D: Ceramic DIP package we Rr wie ore Suffix N: Plastic DIP package are (® fia) arr > D/A CONVERTERS 299
SPECIFICATION S (Vpp = +15, Vreg = +10V, Ta = +25°C unless otherwise noted) PARAMETER AD7520 AD7521 TEST CONDITIONS DC ACCURACY’ Resolution 10 Bits 12 Bits Nonlinearity (See Figure 5) J, 0.2% of FSR max (8 Bit) * S,T,U: over ~55°C to +125°C S, 0.2% of FSR max (8 Bit) * ~10V<VpppS+10V K, 0.1% of FSR max (9 Bit) * T, 0.1% of FSR max (9 Bit) * L, 0.05% of FSR max (10 Bit) * U, 0.05% of FSR max (10 Bit) * Nonlinearity Tempco 2ppm of FSR/°C max * -10V<VpppS+10V Gain Error’ 0.3% of FSR typ * -10V<Vppp<t10V Gain Error Tempco? 10ppm of FSR/°C max * -10V<VpppSt10V Output Leakage Current (either output) 200nA max . Over specified temperature range Power Supply Rejection 50ppm of FSR%/°C typ . AC ACCURACY To 0.05% of FSR Output Current Settling Time 500ns typ * All digital inputs low to high (See Figure 10) and high to low Feedthrough Error (See Figure 9) 10mV p-p max Veer = 20V p-p, 100kHz All digital inputs low REFERENCE INPUT Input Resistance* 5kQ min . 10kQ typ . 20kQ max _ ANALOG OUTPUT Output Capacitance Igyq1 120pF typ * All digital inputs high (See Figure 8) lourz 37pF typ . All digital inputs high louti 37pF typ . All digital inputs low Iout2 120pF typ * All digital inputs low Output Noise (both outputs) Equivalent to 10k typ . (See Figure 7) Johnson noise 7 DIGITAL INPUTS® Low State Threshold 0.8V max * Over specified temperature range High State Threshold 2.4V min * Over specified temperature range Input Current (low to high state) AA typ . Over specified temperature range Input Coding Binary * See Tables 1 & 2 under Applications POWER REQUIREMENTS - a Power Supply Voltage Range +5V to +15V . Ipp SnA typ * All digital inputs at GND 2mA max . All digital inputs high or low Total Dissipation (Including ladder) __20mW typ * NOTES: ‘Full scale range (FSR) is 10V for unipolar mode and +10V for bipolar mode.
2 Using the internal ReEEDBACK
- Digital input levels shoul not go below ground or exceed the positive supply voltage, otherwise damage may occur. “Ladder and feedback resistor tempco is approximately -150ppm/°C. Specifications subject to change without notice.
300 D/A CONVERTERS
- Do not apply voltages higher than Vpp or less than Figure 2. Supply Current vs. Temperature
- The digital control inputs are zener protected; however,
Figure 4. Output Current Settling
Figure 5. Nonlinearity — iV V V
0 SINEWAVE
oon DAC cransfer function from a best straight line function. aoe ail Normally expressed as a percentage of full scale range. Figure 6. Power Supply Rejection RESOLUTION: Value of the LSB. For example, a unipolar . [Vpgpl- Resolution in no way implies linearity. ter 4 9 input stimulus, i.c., 0 to Full Scale. [| sors | V7 > Vor | mest voltage to the input voltage. V coupling from Vpge to output with all switches OFF. Figure 7. Noise four: sv terminal when all inputs are HIGH.
9 T™]5 sora |
Figure 8. Output Capacitance
302 D/A CONVERTERS
Table 1. Tc V where 10k is the value of the feedback resistor. Figure 15. Unipolar Binary Operation A Logical “0” on the control input steers the switch’s current
- Tie all digital inputs to the AD7520 (AD7521) to GND current into R2 which is equal in magnitude but opposite in
- Adjust the offset trimpot on the output operational effect which halves the resolution but doubles the output
"amplifier for OV ImV at Vou range for changes in the digital input.
- To increase VoUT; Place a resistor R in series with the
- To decrease Vayp, place a resistor R in series with Veep: 1. Make Vagp approximately +10V.
(R = 0 to $002) 2. Tic all digital inputs to +15V (Logic “1”).
- Adjust amplifier #2 offset trimpot for OV 1mV at
DIGITAL INPUT ANALOG OUTPUT 4. Tie MSB (Bit 1) to +15V, all other bits to ground. 0111111111 -Vapp (1'2 ~ 210) Gain adjustment is the same as for unipolar operation. Table 1. Code Table — Unipolar Binary Operation trun Ef 07520 [ wm reg & >
304 D/A CONVERTERS
With the AD7520 connected in its normal multiplying configu- Dimensions shown in inches and (mm). gain is 1024. With all bits ON, the gain is 1 (41 LSB).
3 Tae ieee ees
Figure 25. Analog/Digital Divider