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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
- AD7520, 10-Bit Resolution; 8-Bit Linearity
- AD7521, 12-Bit Resolution; 10-Bit Linearity
- Low Nonlinearity Tempco at 2ppm of FSR/ oC
- TTL/CMOS Compatible
- Full Input Static Protection
Ordering Information
(INL, DNL) TEMP. RANGE (oC) PACKAGE PKG. NO. AD7520JN 0.2% (8-Bit) 0 to 70 16 Ld PDIP E16.3 AD7521LN 0.05% (10- Bit) 0 to 70 18 Ld PDIP E18.3 Pinouts AD7520 (PDIP) TOP VIEW AD7521 (PDIP) TOP VIEW IOUT1 IOUT2 GND BIT 1 (MSB) BIT 2 BIT 3 BIT 5 BIT 4 RFEEDBACK BIT 10 (LSB) BIT 9 BIT 8 BIT 7 BIT 6 V REF IOUT1 IOUT2 GND BIT 1 (MSB) BIT 2 BIT 3 BIT 5 BIT 4 R FEEDBACK BIT 11 BIT 9 BIT 8 BIT 7 V REF BIT 12 (LSB) BIT 10 BIT 6
AD7520, AD7521 FN3104 Rev.4.00 Page 2 of 10 August 2002 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Ranges Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W)
16 Ld PDIP Package 90 N/A
18 Ld PDIP Package 80 N/A
CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy elec trostatic fields. Keep unused units in conductive foam at all times. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK. 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified PARAMETER TEST CONDITIONS AD7520 AD7521 UNITSMIN TYP MAX MIN TYP MAX SYSTEM PERFORMANCE (Note 2) Resolution 10 10 10 12 12 12 Bits Nonlinearity J (Note 3) (Figure 2) -10V VREF +10V -- 0.2 (8-Bit) -- - % o f FSR L -10V VREF +10V (Figure 2) -- 0.05 (10-Bit) -- 0.05 (10-Bit) % of FSR Nonlinearity Tempco -10V VREF +10V (Notes 3, 4) -- 2- - 2 ppm of FSR/oC Gain Error - 0.3 - - 0.3 - % of FSR Gain Error Tempco - - 10 - - 10 ppm of FSR/oC Output Leakage Current (Either Output) Over the Specified Temperature Range DYNAMIC CHARACTERISTICS Output Current Settling Time To 0.05% of FSR (All Digital Inputs Low To High And High To Low) (Note 4) (Figure 7) Feedthrough Error V REF = 20VP-P, 100kHz All Digital Inputs Low (Note 4) (Figure 6) - - 10 - - 10 mV P-P REFERENCE INPUT Input Resistance All Digital Inputs High IOUT1 at Ground 5 10 20 5 10 20 k ANALOG OUTPUT Output Capacitance I OUT1 All Digital Inputs High (Note 4) (Figure 5) - 200 - - 200 - pF IOUT2 - 7 5- - 7 5- p F IOUT1 All Digital Inputs Low (Note 4) (Figure 5) - 7 5- - 7 5- p F IOUT2 - 200 - - 200 - pF Output Noise Both Outputs (Note 4) (Figure 4) - Equivalent to 10k - - Equivalent to 10k - Johnson Noise DIGITAL INPUTS Low State Threshold, V IL Over the Specified Temperature Range VIN = 0V or +15V High State Threshold, VIH 2.4 - - 2.4 - - V Input Current, IIL, IIH -- 1- - 1 A Input Coding See Tables 1 and 2 Binary/Offset Binary
AD7520, AD7521 FN3104 Rev.4.00 Page 3 of 10 August 2002 Functional Diagram POWER SUPPLY CHARACTERISTICS Power Supply Rejection V+ = 14.5V to 15.5V (Note 3) (Figure 3) FSR/% V+ Power Supply Voltage Range +5 to +15 +5 to +15 V I+ All Digital Inputs at 0V or V+ Excluding Ladder Network - 1- - 1- A All Digital Inputs High or Low Excluding Ladder Network -- 2 -- 2 m A Total Power Dissipation Including the Ladder Network - 20 - - 20 - mW NOTES: 2. Full Scale Range (FSR) is 10V for Unipolar and 10V for Bipolar modes. 3. Using internal feedback resistor R FEEDBACK. 4. Guaranteed by design, or charac terization and not production tested. 5. Accuracy not guaranteed unless outputs at GND potential. 6. Accuracy is tested and guaranteed at V+ = 15V only. Electrical Specifications V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS AD7520 AD7521 UNITSMIN TYP MAX MIN TYP MAX Pin Descriptions AD7520 AD7521 PIN NAME DESCRIPTION 11 I OUT1 Current Out summing junction of the R2R ladder network. 22 I OUT2 Current Out virtual ground, return path for the R2R ladder network. 3 3 GND Digital Ground. Ground potential for digital side of D/A. 4 4 Bits 1(MSB) Most Significant Digital Data Bit. 5 5 Bit 2 Digital Bit 2. 6 6 Bit 3 Digital Bit 3. 7 7 Bit 4 Digital Bit 4. 8 8 Bit 5 Digital Bit 5. 9 9 Bit 6 Digital Bit 6. 10 10 Bit 7 Digital Bit 7. 11 11 Bit 8 Digital Bit 8. 12 12 Bit 9 Digital Bit 9. 13 13 Bit 10 Digital Bit 10 (AD7521). Least Significant Digital Data Bit (AD7520). - 14 Bit 11 Digital Bit 11 (AD7521). - 15 Bit 12 Least Significant Digital Data Bit (AD7521). 14 16 V+ Power Supply +5V to +15V. 15 17 V REF Voltage Reference Input to set the output range. Supplies the R2R resistor ladder. 16 18 R FEEDBACK Feedback resistor used for the current to voltage conversion when using an external Op Amp. 20k GND IOUT2 IOUT1 RFEEDBACKBIT 3BIT 2MSB VREF 10k 10k 10k 10k SPDT NMOS SWITCHES 10k NOTES: Switches shown for Digital Inputs “High”. Resistor values are typical.
AD7520, AD7521 FN3104 Rev.4.00 Page 5 of 10 August 2002
Applications
The circuit configuration for operating the AD7520 in unipolar mode is shown in Figure 8. Similar circuits can be used for AD7521. With positive and negative V REF values the circuit is capable of 2-Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table 1. Zero Offset Adjustment 1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V at VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 2. Monitor V OUT for a -VREF (1-2-N) reading. (N = 8 for AD7520 and N = 10 for AD7521). FIGURE 4. NOISE FIGURE 5. OUTPUT CAPACITANCE FIGURE 6. FEEDTHROUGH ERROR FIGURE 7. OUTPUT CURRENT SETTLING TIME
6 VOUT
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION
- To decrease V OUT, connect a series resistor (0 to 250)
between the reference voltage and the VREF terminal.
- To increase V OUT, connect a series resistor (0 to 250) in
the IOUT1 amplifier feedback loop. Output Value” table for bipolar mode is given in Table 2.
- Adjust V REF to approximately +10V.
- Connect all digital inputs to “Logic 1”.
- Adjust I OUT2 amplifier offset adjust trimpot for 0V 1mV at
- Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic
- Adjust I OUT1 amplifier offset adjust trimpot for 0V 1mV at
- Connect all digital inputs to V+.
- Monitor VOUT for a -VREF (1-2-(N-1) volts reading. (N = 8 for
- To increase V OUT, connect a series resistor of up to 250
- To decrease VOUT, connect a series resister of up to 250
between the reference voltage and the VREF terminal. TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE
0111111111 V REF (2-(N-1))
0000000001 V REF (1-2-(N-1))
0000000000 V REF
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT
AD7520, AD7521 FN3104 Rev.4.00 Page 7 of 10 August 2002 Die Characteristics DIE DIMENSIONS: 101 mils x 103 mils (2565m x 2616m) METALLIZATION: Type: Pure Aluminum Thickness: 101kÅ PASSIVATION: Type: PSG/Nitride PSG: 71.4kÅ Nitride: 81.2kÅ PROCESS: CMOS Metal Gate Metallization Mask Layout AD7520 PIN 3 GND PIN 2 IOUT2 PIN 1 IOUT1 PIN 16 RFEEDBACK PIN 15 V REF PIN 14 NCNCPIN 12 PIN 4 BIT 1 (MSB) PIN 5 BIT 2 PIN 6 BIT 3 PIN 7 BIT 4 PIN 11 BIT 8 PIN 10 BIT 7 PIN 9 BIT 6 PIN 8 BIT 5 BIT 9 PIN 13 BIT 10 (LSB)
AD7520, AD7521 FN3104 Rev.4.00 Page 8 of 10 August 2002 Die Characteristics DIE DIMENSIONS: 101 mils x 103 mils (2565m x 2616m) METALLIZATION: Type: Pure Aluminum Thickness: 101kÅ PASSIVATION: Type: PSG/Nitride PSG: 71.4kÅ Nitride: 81.2kÅ PROCESS: CMOS Metal Gate Metallization Mask Layout AD7521 PIN 3 GND PIN 2 IOUT2 PIN 1 IOUT1 PIN 18 RFEEDBACK PIN 17 V REF PIN 16 PIN 12 PIN 4 BIT 1 (MSB) PIN 5 BIT 2 PIN 6 BIT 3 PIN 7 BIT 4 PIN 11 BIT 8 PIN 10 BIT 7 PIN 9 BIT 6 PIN 8 BIT 5 BIT 9 PIN 13 BIT 10 PIN 14 BIT 11 PIN 15 BIT 12 (LSB)
AD7520, AD7521 FN3104 Rev.4.00 Page 9 of 10 August 2002 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93
FN3104 Rev.4.00 Page 10 of 10 August 2002 AD7520, AD7521 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.845 0.880 21.47 22.35 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 8 1 8 9 Rev. 0 12/93