AD7511DI AD | Alldatasheet
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Latch-Proof Foti ae ee Htetysuy at h ai Overvoltage-Proof: +25V verre on eal Nid a Low Roy: 752 ir heey A oes 7 i ees Low Dissipation: 3mW Dee Pee 3 = TTL/CMOS Direct Interface j GE fj Fla aseais ey (| Wee) Silicon-Nitride Passivated JE ia AEE 4 . Penh | Monolithic Dielectrically-Isolated CMO'S es jg ny sey Bos Ee 7238 Ut eae l 37/44" ie H Spoons 1 " Lar” ae? Coe 3 i — Pet tp hd ‘a i is (or noon tS lS hs GENERAL DESCRIPTION ORDERING INFORMATION The AD7510D1, AD7511DI and AD7512DI are a family of as © °
5 A , ‘ o Plastic ‘eramic perating
latch proof dielectrically isolated CMOS switches featuring tint ean cea overvoltage protection up to £25V above “he power supplies. Henge These benefits are obtained without sacrificing the low “ON” ADTSIODIIN resistance (75Q) or low leakage current (400pA), the main AD7510DIKN features of an analog switch AD7511DUJN Oto +70°C AD7511DIKN The AD7510DI and AD7511DI consist of four independent Ore abIKN SPST analog switches packaged in a 16-pir DIP. They differ ADTSIODD only in that the digital control logic is inverted. The AD7512D1 AD7510DIKD i SPDT switel ckaged in a 144 ADISUIDID | jo Se has two independent SPDT switches packaged in a 14-pin DIP. peeeaenet 25°C to 485°C Very low power dissipation, overvoltage protection and TTL/ AD7512D1JD CMOS direct interfacing are achieved by combining a unique AD7512DIKD circuit design and a dielectrically isolated CMOS process. Ap7510DIsD Silicon nitride passivation ensures long term stability while ey | —ss°cw vi2s°c monolithic construction provides reliability. AD7512DISD AD7512DITD PIN CONFIGURATIONS AorsNO1 (ror view Avrer201 CONTROL LOGIC vel * ys ved * as AD7510DI; Switch “ON” for Address “HIGH” ono [2] r D> bi] ot ono P] rooted ours AD7511DI: Switch “ON” for Address “LOW” rere a “EP El = AD7512D1: Address “HIGH” makes $1 to Out 1 and $3 to a2 [aps bia] 02 aps Ep Out 2 aE sha] = no[E] ¢f[>o Sofi] our 2 as[eby De, os ne [E] fa] s3 NC | al ‘oo Ne CE] L | voo[z] [e] voo[8] > bs] 0+ SWITCHES AND MULTIPLEXERS 545
SPECIFICATIONS (Vpp = +15V, Vss = —15V unless otherwise noted) COMMERCIAL VERSIONS (J, K) PARAMETER MODEL — VERSION 425°C Qt +70°C(N)_——- TEST CONDITIONS -25°C to +85°C (D) ANALOG SWITCH Ron’ All IK 75Q typ, 1002 max 175Q max -10V < Vp < +10V Ron VS Vp (Vs) All kK 20% typ Ing = 1.0mA Ron Drift All TK +0.5%/°C typ ~ R, Match All JK 1% typ. ‘ON = = RON Drift a Vp = 0, Ipg = 1.0mA Match Alt JK 0.01%/°C typ Ip (gs) OFF! All LK 0.5nA typ, 5nA max 500nA max Vp = -10V, Vs = +10V and Vp = +10V, Vg = -10V Tp Usdon® All LK TOnA max ° Vs = Vp = +10V Vs = Vp = -10V lout’ AD7512DI_ J, K 15nA max 1590nA max Vs1 = Vour = £10V, Vgp = F10V and Vg = Voyr = £10V, Vey = F10V DIGITAL CONTROL, TTT Vin! All JK 0.8V max Vinu’ All J 3.0V min All K 2.6 min Gy All J.K 3pF typ tn All IK 10nA max Vin = Yop Ine All JK 10nA max Vin = 9 DYNAMIC CHARACTERISTICS ton AD7510D1_ J, K 180ns typ AD7S5LIDI J,K 350ns typ noe 0 + torr AD7S10DI__ J, K 350ns typ Vuy = 0 t0 43.0V AD7511DI_ J, K 180ns typ “TRANSITION AD7S512DI— J, K 300ns typ Gy (Cp OFF All TK 8pF typ - Cg (Cp ON All JK 17pF typ ps (Cs_our) All JK 1pF typ Vp (Vg) = OV Cop (Css) All JK 0.5pF typ Cour AD7512DI J, K 17pF typ All LK 30pC ty Measured at $ or D terminal Ons j peop G_ = 1000pF, Vay = 0 to 3V, Vp (Vs) = +10V to -10V POWER SUPPLY Ipn! All JK SOOHA max D . les" All UK 100UA max All digital inputs = Vann DI : : Iget ‘All LK 100HA max All digital inputs = Vpyy, NOTES * 100% tested. 2 Guaranteed, not production tested. 2A pullup resistor, typically 1-2k® is required to make: “J” versions TTL compatible Specifications subject to change without notice.
546 SWITCHES AND MULTIPLEXERS
MILITARY VERSIONS (S, T) PARAMETER MODEL VERSION 425°C 55°C to +125°C TEST CONDITIONS ANALOG SWITCH ~ Ron' All $,T 1002 max 175Q max -10V < Vy <+10V Ipg = ImA I Ip Us)orr All ST 3nA max 200nA max Vp = -10V, Vg = +10V and Vp = +10V, Vs = -10V Ip son* All 8,7 10 - Vs = Vp = +10V and Vs = Vp = -10V lout! AD7512D1_— ST 9nA max 600nA max Vs = Vour = £10V Vep = F10V and Vso = Vour = t10V Vg, = F10V DIGITAL CONTROL - Vinu' All s,T 0.38V max Venn” AD7510DI_S 2.4V min AD7511DI_T. 2.4V min AD7512D1 T 2.4V min AD7511DI s 3.0V min AD7512D1 Ss 3.0V min ne min Inn All ST TOnA max Vin = Yop In’ All 8,7 10nA max Vin = 0 DYNAMIC ” CHARACTERISTICS ton? AD7S10DI_ S$, T 1.0us max Vin = 0 to #3V AD7511DI s,T 1.0p's max torr” AD7510DI_ S$, T 1.0us max AD7511D1 8, T 1.0us max tERANSITION” AD7512D1_— $, T 1.0us max POWER SUPPLY - pn! All s,T 80CHA max All digital inputs = Vayyy sg All 8, 800HA max bp, All 37 — SO0HA max All digital inputs = Vay —_ Isc? All $s, T 500A max NOTES: ” * 100% tested. ? Guaranteed, not production tested. >A pullup resistor, typically 1-2kS is required to make AD7511DISD and AD7512DISD TTL compatible. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Vgg to GND 2.0 eee eee ee ATV Up v0 #70°C. eee eee ee. 670MW or Vgg-25V Operating Temperature Switch Current (Ipg, Surge) - yey CAUTION: The digital control inputs are zener protected; Power Dissipation (Package) under high electrostatic fields. Keep unused units in conductive 14 & 16 pin Ceramic Dip foam et all times. Prior to pulling the devices from the conduc- Upto +75. Cos posse e eee eeesesss+ 450mW | tive foam, ground the foam to deplete any accumulated charge. SWITCHES AND MULTIPLEXERS 547
0 Vp "15
rm, | _teve . CONTROL SHIFTER! INPUT DFIVER RI (ins C) os He 1 cat ) 2 i) -———0 v,5-15v NOTE: CIRCLED DEVICES IN SEPARATE ISOLATED POCKETS. Figure i. Typical Output Switch Circuitry of AD7510DI Series CMOS devices make excellent analog switches; however, An equivalent circuit of the output switch element in Figure 2 problems with overvoltage and latch-up phenomenum neces- shows that, indeed, the 1kQ limiting resistors are in series sitated protection circuitry. These protection circuits, with the back-gates of the P- and N-channel output devices— however, either caused degradation of important switch not in series with the signal path between the $ and D parameters such as RON or leakage, or provided only limited terminals. protection in the event of overvoltage. In some applications it is possible to turn on a parasitic NPN The AD7510DI series switches utilize a dielectrically-isolated (drain co back-gate to source of the N-channel) transistor, CMOS fabrication process to eliminate the four-layer substrate causing device destruction under certain conditions. This found in junction-isolated CMOS, thus providing latch-free case will only manifest itself when a negative overvoltage operation. (and not a positive overvoltage) exists with another voltage source on the other side of the switch. Current limitation A typical switch channel is shown in Figure 1, The output through external resistors (2002) or current limiting devices switching element is comprised of device aumbers 4 and 5. (outpu: of op amps) will prevent damage to the device. Operation is as follows: for an “ON” switch, (in+) is Vpp and (in-) is Vgg from the driver circuits. Device numbers 1 and 2 are “OFF” and number 3 is “ON.” Hence, the back- Yoo gates of the P- and N-channel output devices (numbers 4 and “ey 5) are tied together and floating. (The circled devices are located in separate dielectrically isolated pockets.) Floating 1k the output switch back-gates with the signe] input increases ~---]__- the effective threshold voltage for an applied analog signal, Tope aH thus providing a flatter RON versus Vg response. so : * + oD For an “OFF” switch, device number 3 is “OFF,” and the P CHANNEL back-gates of devices 4 and 5 are tied through 1kQ resistors N- CHANNEL (R1 and R2) to the respective supply voltages through the TO SRANNEL “ON” devices 1 and 2. H La 1 1 ont nt If a voltage is applied to the $ or D termine] which exceeds b---}----3 Vpp or Vg, the S- or D-to-back-gate diode is forward biased; 1k however, R1 and R2 provide current limitig action. Consequently, without external current | miting resistance we (or increased RON), the AD7510DI series switches provide: 1. Latch-proof operation Figure 2. AD7510DI Series Output Switch 2. Overvoltage protection 25V beyond th: Vgg and Vpp Diode Equivalent Circuit supply voltage
548 SWITCHES AND MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS Fon (th ‘transition (ns) PRP EC aL mer I LS SSS} Ne SSEEEES | =P BERR fp SS 120-1000 8 6 4 2 oO 2 4 6 & 10 Ww ary 2 3 4 6 AT DIFFERENT SUPPLIES Vp (Vs) (Vb Vin (VP Ron as a Function of Vp (Vs) tTSANSITION @ @ Function of Digital Input Voltage Ron (2) tow. torr (ns) 200 wool ADsi201 Vop = 18V a Sees ee ee Lt SSSeeerSees DEPRES [ee Per OL. = [| Ron as a Function of Vp (Vs) ton, toFF as a Function of Temperature
300 Vsg -15V_ Vs5 = -15V_
[I es a cl . ae ww | toutes | | att eg a ce ores, || | Seo oL. ‘Vs (V) Ta CC) Is, Uplogr vs Vs tTRANSITION as a Function of Temperature SWITCHES AND MULTIPLEXERS 549
TYPICAL SWITCHING CHARACTERISTICS AD7510DI, AD7511DI 0.5us/DIV 0.5yus/DIV vow ISS ‘ow IESE Vs vs ‘ow SRR EBSI ‘on IPERS Se eee Se eee Switching Waveforms for Vp = -10V Switching Waveforms for Vp = +10V 0.5us/DIV 0.5us/DIV “i ¥ ee ee LT a Vs 7, \\s vow S/S ‘on IRE Se ee ee Se ee eee Switching Waveforms for Vp = Open Switching Waveforms for Vp = OV AD7510DI, AD7511D1 TEST CIRCUIT roams mtr ot—eve ! 1 Ys - score {No eam { i t 4 | > [} nn J TT Veg GND Vo (-15V) (+15V)
550 SWITCHES AND MULTIPLEXERS
el TT, TYPICAL SWITCHING CHARACTERISTICS AD751201 0.5us/DIV 0.5us/DIV Sow IPP Sow IPS Vs Vs ‘vow SP ‘vow i i ee eee Switching Waveforms for Switching Waveforms for Vgq = -10V, Veo = #10V, Ry = 1k Vsq = +10V, Veo = -10V, Ry = 0.5us/DIV 0.5us/DIV fe eee eee Fe Ole m v Sow — tot Som ptt} tt ee Se evo (O.5V/DIV) nim (0.S/DIV) | SE se | Switching Waverorms for Switching Waveforms for Vgq and Veo = 9V, Ry = © Vsq and Vgp = Open, Ry = 1k AD7512D1 TEST CURCUIT | ren | I Vs1 vot} >- o i _¢ Your
1 Theva RL
| SCOPE +> = 10MO/7pF I a --4 a oar oar Vss GND Vpp (-15V) (+18V) SWITCHES AND MULTIPLEXERS 551
RON: Ohmic resistance between terminals D and S. OUTLINE DIMENSIONS RON Drift Difference between the RON drift of any Dimensions shown in inches and (mm). Match: two switches. RON Match: Difference between the RON of any two 14-PIN CERAMIC DIP switches. - — Ip (is)orr: Current at terminals D or S. This is a leakage | sahen current when the switch is “OFF.” i i aye Ip (Is)ON: Leakage current that flows from the closed | Nom suson switch into the body. (This leakage will eg | Sons show up as the difference between the 1 a+ current If) going into the switch and the ro TE - outgoing current Ig.) ~o f st PT Vp (Vs): Analog voltage on terminal D (S). oe ow 3008102095 Cs (CD): Capacitance between terminal $ (D) and i l! aq. 4T j_ +} ground. (This capacitance is specified joene Gowws baa eaa) pen for the switch open and closed.) Leno no ssn WY BOF om Noren cps: Capacitance between terninals D and S. AD7512D1 (This will determine the switch isolation over frequency.) 14-PIN PLASTIC DIP Cpp (Css: Capacitance between terminals D (S) of any two switches. (This will determine the cross yo coupling between switches vs, frequency.) aoe ton: Delay time between the 50% points of the [ts digital input and switch ON” condition. [oY Siete ) gxeom toFF: Delay time between the 50% points of the i te digital input and switch ‘OFF” condition. wae 4 1 =e transition Delay time when switching from one address y i E as 7 | = state to another. a LF soz VINL: Threshold voltage for the low state. Torte Soe wae) | See VINH: Threshold voltage for the high state. Meno mo TOENIFIED GY DOT On NOTCH INL (INH): Input current of the digital input. AD7512D1 CIN: Input capacitance to ground of the digital input. 16-PIN CERAMIC DIP Vpp: Most positive voltage supply. Vss: Most negative voltage supply. oben Ipp: Positive supply current. ye Igg: Negative supply current. Lo gros eucos, BONDING DIAGRAMS (TOP VIEW) otal — is) eae ee goensy — a2 wson onsizen oxecm AD751201 oe] § ead no wRNTEED WY OT OR MOTE ‘oO AD7510D1, AD7511D1 | 4 8 6b 8 oo 16-PIN PLASTIC DIP Oo 0500 oo oO as AD7510D1, AD7511D/_ r= r ile Ae eae od shana = oo ob Oo a Cab wo, | DETEED oY DOT ON TEN $m mp | AD7510D1, AD7511D1