AD75089

75089_1.PDF

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• Manufacturer or author: Joyce Arivella
• PDF pages: 8

Technical content

FEATURES FUNCTIONAL BLOCK DIAGRAM Eight Complete Voltage Output DACs On-Chip Voltage Reference Yaerour_Ynerw On-Chip Data Latches with Readback Feature Ty? wv Output Voltage Range: +5 V EE: ANALOG <0 V, Compact 44-Pin PLCC Package oer 4 > is ‘SUPPLY oo i | vi APPLICATIONS ono 4 —ANALOS ern Automatic Test Equipment V7 re Pas Instrumentation Ver, Avionics robots aero Te], Process Control onh ae ta pw bas Vac - PRODUCT DESCRIPTION De ona The AD75089 DACPORT® contains eight complete 12-bit, volt- 08 or-> FE Ez TO] age output digital-to-analog converters in one monolithic IC. It Pe ba by Yours thus offers the highest density 12-bit D/A function available. ws Sa} § Vacre Each DAC offers flexibility, accuracy and good dynamic perfor- op ena 2 Yours mance. The R-2R structure is fabricated from thin-film resistors v2 pa AVE OEEGHT yrers that are laser-trimmed to achieve guaranteed monotonicity over Ln end ‘SHOWN AD75089 g Veer the full operating temperature range. DAC-to-DAC matching a 9 Yours performance is specified. ¥ Vacs foure ~ The output amplifier combines the best features of bipolar and y, ? rer MOS devices to achieve good dynamic performance and low off- —_ joann 6 nr X your set. Settling time is under 10 1s, and each output can drive a Fe [eer oac) van 2 mA, 500 pF load. Short circuit protection allows indefinite Ly Youre shorts to Voc; Vpps Vss; and GND. Yoo +5 V LOGIC SUPPLY © Vacro Digital circuitry is implemented in CMOS logic. The fast, low { vana. __—crmorioae—] power, digital interface allows this DACPORT to interface with = "™” heed vesuss. most microprocessors through a single 12-bit wide bus. A read- b-6-5-0-6-0-0 back feature allows the internal DAC registers to be read back BD CE WR A2 A1 AO RST through the digital port as 12-bit words. When disabled, the on-chij Sati . . . . ° we chip application resistors and output amplifier. The chip may ~ __ readback drivers are placed in a high impedance mode. be operated from the internal reference or an external reference. A RESET control pin is provided to allow simultaneous asyn- The high performance and functional completeness of this chronous reset of all DAC data latches, causing the DAC out- DACPORT result from their fabrication oy Analog Devices’ Puts to go to the negative extreme of their range. BiMOS II process. This epitaxial BICMOS process features The analog portion of the DACPORT consists of eight DAC bipolar transistors for precise analog circuitry, CMOS transistors cells, eight output amplifiers, a voltage reference, a control for dense logic and analog Sovtches, laser-trimmed thin-film amplifier and switches. Each DAC cell is an inverting R-2R resistors and double-level metal interconnects. type. The output current from each DAC is switched to the DACPORT is a registered trademark of Analog Devices, Inc. — —_REV.O Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD75089 SPECIFICATIONS (Weg = +5 V, Vop = +12 V, Vso = —12 V, Vecrin = +5.000 V, all Veer pins — connected to Analog Ground, T, = +25°C unless otherwise noted.) Paranier Ui - RESOLUTION ee ANALOG OUTPUT Voltage Range, Voyr max to Voy min +5 Volts Output Current (Each Channel, Source or Sink) 2 mA Load Capacitance (Each Channel) 500 pF Short Circuit Current (Each Channel) 25 50 mA ACCURACY Gain Error, Including Internal Reference 15 +8 15 LSB Integral Linearity Error -1 +12 1 LSB Integral Linearity Error, Tyr to Tmax +1 LSB Differential Linearity Error -3/4 +04 3/4 LSB Differential Linearity Error, Tym to Tax +12 LSB Gain Error Drift +10 ppm of FSR/°C Offset Drift +7 ppm of FSR/°C Noise, 0.1 to 2 MHz Bandwidth 200 nV rms REFERENCE INPUT Input Resistance 10 MQ ~ Voltage Range +5.5/-3.0 Volts REFERENCE OUTPUT Output Voltage 4.95 5.05 Volts Temperature Coefficient +15 ppm/*C POWER REQUIREMENTS Voc 4.5 5.0 5.5 Volts lee 0.1 5 mA Vpp> Vss +114 +12.0 +12.6 Volts Ipp 16 28 mA ~ Iys -28 =15 mA Total Power 350 mW ANALOG GROUND CURRENT! PER EACH OF 8 CHANNELS pA MATCHING PERFORMANCE Gain® -5 +25 5 LSB Offset? -4 +2 4 LSB CROSSTALK Analog (DC)* —90 dB Digital (Transient)* —60 «B ~ DYNAMIC PERFORMANCE (R,; = 5 kQ, C, = 500 pF) Slew Rate 3.0 Vins Settling Time to +1/2 LSB Vour max to Voy min or Vour min to Vour max 8 ps POWER SUPPLY GAIN SENSITIVITY 1.4 V < Vpp = 12.6V +8 +25 ppm/% of Vpp -12.6 V < Vss S 11.4 V +8 +25 ppm/% of Ves, a REV n

‘Analog ground current is the code dependent current flowing in each of the Veer pins. Gain matching error is the largest difference in gain error between any two DACs in one package. 30Offset matching error is the largest difference in offset values between any two DACs in one package. See Definitions of Specifications section. Reference level for timing measurements = 1.5 V. See definitions of specifications later on in this data sheet. Specifications subject to change without notice. Figure 1. Write Timing Diagram Figure 2. Readback Timing Diagram

Vos tO AGND 2... cece eee eee eee eee es 718 Vt00V reliability. recommended to avoid performance degradation or loss of functionality. Figure 3. Recommended Circuit Schematic

PIN CONFIGURATION PIN DESCRIPTIONS “ 44a PLCC Pachnge a

1 Veer Reference Input

pesede BEEES 2 Vaurour 5 V Reference Output Sr Pree OS SSS 3 VaErGND Reference Ground nogaalaaiclalmlca 4 Voor Analog Output 3 LD

5 Vagrs Analog Return 3

Youre Ee} FI Vos 6 Vere Analog Return 2 Youn Ly Bel Vnerr 7 Vourz Analog Output 2 Vrers Le} Fed Your 8 Voun: Analog Output 1 Yrero fe fal aawo 9 Veer Analog Return 1 Your [eg aD75069 pal 2 10 v, Return 0 Ves [2] ‘TOP IEW [34] at RETO Analog Ped (Not to Seale) FB] Ao 1L Vouro Analog Output 0 ied El ce 12 Vss —12 V Analog Power Supply va Flic 1B Vpp +12 V Analog Power Supply wae fa Ea am 4 DGND Digital Ground on Ee El ner 15 Voc +5 V Logic Power Supply

16 IOGND Bus Interface Ground

v [el elles ee es eT es) eal zl] 7 Du Data Bus Bit 11 (MSB) g8R5RSsRB85 8 18 DIO Data Bus Bit 10

19 D9 Data Bus Bit 9

20 Ds Data Bus Bit 8

21 D7 Data Bus Bit 7

DEFINITIONS OF SPECIFICATIONS 22 D6 Data Bus Bit 6 INTEGRAL LINEARITY ERROR: Integral linearity error is 23 Ds Data Bus Bit 5 the maximum devistion of the actual DAC output from the 4 D4 Data Bus Bit 4 ideal analog output (a straight line drawn from —full scale to 25 D3 Data Bus Bit 3 + full scale) for any digital input code. 26 D2 Data Bus Bit 2 ~ MONOTONICITY: A DAC is said to be monotonic if the out- 27 DI Data Bus Bit 1 put either increases or remains constant for increasing digital 28 Do Data Bus Bit 0 (LSB) inputs such that the output will always be a nondecreasing func- 29 RST Reset Input; Active High tion of input. The AD75089 is monotonic over its full operating 30 WR Write Input; Active Low Temperate rage x | Chip Enable Input; Active Low . . ip put; ive DIFFERENTIAL LINEARITY ERROR: Monotonic behavior 33 A0 ‘Address Input Bit 0 (LSB) requires that the differential linearity error be less than 1 LSB 34 Al Address Input Bit 1 over the temperature range of interest. Differential nonlinearity 35 rv) ‘Address Input Bit 2 (MSB) is the measure of the variation in analog value, normalized to 36 AGND ‘Analog Ground _/ fall scale, associated with a 1 LSB change in digital input code. 37, v, ‘Analog Output 7 naren OUT? For example, for a 10 V output span, a change of 1 LSB in digi- 3 v ‘Analog Return 7 tal input code should result in a 2.44 mV change in the analog 39 anak ‘Analog Return 6 output (1 LSB = 10 V/4096 = 2.44 mV). If in actual use, how- 45 vo ‘Analog Output 6 ever, a 1 LSB change in the input code results in a change of 4 vou ‘Analog Output 5 only 0.61 mV (1/4 LSB) in analog output, the differential non- 2 vo ‘Analog Return 5 linearity error would be —1.83 mV, or —3/4 LSB. a vor ‘Analog Return 4 GAIN ERROR: DAC gain error is a measure of the difference 4 Vours Analog Output 4 between the output span of an ideal DAC and an actual device. ETTLING TIME: Settling time is the time required for the CROSSTALK: Crosstalk is the change in an output caused by a sutpur to reach and resain within a specified ervr band about change in one or more of the other inputs or outputs. Analog or io final vane, meamnred frm the digi! Inpat rensiion drops aring from change in load Curren. Digital or anseat crosstalk is produced by capacitive coupling from the data inputs or from other changing DAC outputs. FULL-SCALE RANGE: FSR is 10 V for the +5 V range. TRANSISTOR COUNT ~ The AD75089 contains 5,225 transistors. REV A -5-

BINARY CODE TABLE Voltage Reference The AD75089 is designed to operate from a reference voltage of ww Offset Binary Nominal Analog Output +5 V. The internal reference can serve the entire chip. If supe- Value in DAC Latch | Voltage, Vere = +5.000 V rior tolerance, PSRR, or temperature performance are needed, MSB LSB external devices, such as the ADS86, may be used. M1111 1111 +4.9976 V Output Considerations 1000 0000 0000 0.0000 V Each DAC output can source or sink +2 mA of current to an 0000 0000 0000 —5.0000 V external load. Short-circuit protection limits load current to a maximum of 40 mA per channel. Load capacitance of up to ANALOG CIRCUIT CONSIDERATIONS 500 pF can be accommodated with no effect on stability. designated AGND, Vasro-Vrer7> Vreronp> , ani ; ate ewi DGND. The AGND pin is the ground reference point for the ith a fixed 5 V reference and all bits switched from 1 to 0 and device. Vazronn is the ground reference point for the on-chip . voltage reference. Varro through Vpet; are the 8 ground return pins for the 8 DACs and their output amplifiers. The 10 analog wo} TET TT YT YT ground pins should be connected radially to the analog ground 100 | | [ ] \\wrearmecone | point in the system. The external reference and any external "| _ loads should also be returned to the analog ground point. To 5.0 Pio ke Nes! minimize crosstalk, all paths to the single analog ground point zo TTT TN i must be short and direct. LT Tete | ty ‘The IOGND and DGND pins should be connected to the digi- “TT TL_TE_LLEL tal ground point in the circuit. These pins return current from “108 | | |_| []rosmecoma | | the bus interface and logic portions, respectively, of the 180 gone AD75089 circuitry to ground. woe LL TT TT Analog and digital grounds should be connected at one point in © 10 20, 30 40 50 60 70 80 90 the system. If there is a possibility that this connection may be “ = broken or otherwise disconnected, then two diodes should be Figure 4. Settling Time; Full-Scale Output Change Ns! connected in inverse parallel between the analog and digital ground pins of the AD75089 to limit the maximum ground volt- Crosstalk age difference. Crosstalk is a spurious signal on one DAC output caused by a Power Supplies, Sequencing and Decoupling change in one or more of the other DACs. Crosstalk can be The AD75089 requires three power supplies for proper opera- induced by capacitive, thermal, or load-current induced feed- tion. Voc powers the logic portions of the device and requires through. Figure 5 shows typical crosstalk. The upper trace of +5 volts. Vpp and Vsg power the remaining portions of the cir- the left photo shows DAC 6 switching from —5.0 V to +5.0 v cuitry and require +12 V and —12 V, respectively. and ak ACD, vane jower trace shows brief spikes in the Al junction-isolated parts powered from multiple supplies inpot data, The longer disturbances are redthr ae soalog feeds Cc Fequire proper attention to supply sequencing. Because BIMOS —hrough from DAC 6’s output. The loads of both DACs are TI uses junction isolation, parasitic diodes exist between Vop 5k in parallel with 500 pF. The right photo shows the detail and vos and bewween Vas and ae reatally decent dioas of the falling edge of DAC 6 (large trace) and the effect on reverse-biased to preven ve watch DAC 7 (middle trace) under the conditions. up. This means that Vpp must always be greater than (Voc — ‘ ) un same tons, 0.5 V) and Vss must always be less than (DGND + 0.5 V). os —_ —— External Schottky (e.g., 1N5818) or silicon (e.g., 1N4001) | diodes may be used for protection when system supply sequenc- ae \\ ing cannot be guaranteed. One diode should be connected | i \\ between Vpp and Voc, with the anode connected to Voc. A second diode should connect DGND and Ves, with the anode . tied to Vgs. i iN Decoupling capacitors should be used on all power supply pins. [_ Good engineering practice dictates that the bypass capacitors be — located as near as possible to the package pins. Recommended J values are 4.7 F tantalum and 0.1 uF ceramic from Vpp and Figure 5. Output Crosstalk Vss to analog ground, and 0.1 4F from Voc to digital ground. . -6- REV.0

DIGITAL INTERFACING This circuit takes advantage of the high input impedance of ~ __ Towrite to the chip, apply the desired address, and then take Vari and the fact that a CMOS gate’s output looks like a Chip Enable (CE) and Write (WR) low. Typically, CE is tied to _ resistance connected to either of the gate’s power supply pins. the system address decoder, and WR connects to the system The gate’s Vp is supplied by the AD75089’s Reference Out- write strobe. put, and its Vs terminal should be connected to Analog If the data is changed while CE and WR are low, the DAC reg- Ground. Resetting the AD75089 will also reset the S-R flip-flop ister is transparent, and it will follow the input data —«‘f0Fmed by the two cross-coupled gates, forcing Vassrms and all eight DAC outputs to ground. The flip-flop is set by a low- Readback . . going pulse applied to node B, driving the high impedance To read data back from the chip, apply the desired address, and Vs. pin to the gate’s supply voltage of Varrour- Address then take Chip Enable (CE) and Read (RD) low. Typically, CE decoding will ensure that the flip-flop’s output remains low until is tied to the system address decoder, and RD connects to the all eight DACs have been updated. system read strobe. oe This circuit can latch up if the logic-1 voltages applied to nodes If the address is changed while CE and RD are low, the data A or B exceed Vazrour by more than 300 mV. Simple resistor output will follow the selected address after a delay of tan. dividers can be used as shown in Figure 6b to protect against Data Reset this possibility. To reset all data latches asynchronously, take Reset (RST) high. na This clears all data latches and causes the DAC outputs to go to FROM SYSTEM TO CMOS GATES IN y the negative end of their output range, i.e., —5 V. DIGITAL LOGIE oa MOonnamNo®)

APPLICATIONS

Asserting RESET clears all AD75089’s DAC registers and forces Figure 6b. Protecting Against Vpp (Digital Logic) the DAC outputs to —5 V. In some cases a reset to 0 V is pref- > Vaerour erable. The circuit in Figure 6a will force all DAC outputs to 0 V following a reset. Offsetting Output Ranges ‘The functional block diagram in Figure 3 implies that the fhm om fd y AD75089’s output ranges can be offset by driving the various v oF ta 7000, aotr Vaer Pins. Unfortunately, the actual internal circuitry differs wr wr Vnerour 1 from the simplified arrangement in the figure, and the gain seen (AD75089 ReseT from a Vper “input” to the associated DAC output is actually “ code-dependent. A nonzero voltage applied to a Vagy terminal RESET 1D; [ » will offset the companion Voy by an amount that changes with c Zs the applied DAC code. Offsetting the AD75089’s output ranges by driving the Vger pins is NOT recommended. External —~ amplifiers with the appropriate gain and level shifting circuitry Ea [ should be used if output spans other than —5 V to +5 V are DECODE 7 required. ANALOG ~ noun \\/ Figure 6a. Circuitry to Reset All AD75089 DAC Outputs toov Y ervn 7

Dimensions shown in inches and (mm). ~ (P-44A) +1 fr-0.02 0.009 mo ; d Pmt 3 i ry 4 (WENTIFER E a) 2 C 3) ° : vorwee : | 5 pe Ju) qo 5 0.500 (14.08) : : w= | 5 erm ; ; Soma qeenn eo [3 fo ~~ 00 17489) Wax 80 oy, q c E z Ea