AD74115 AD | Alldatasheet
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 103
Technical content
Single-Channel, Software Configurable Input and Output Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Single-channel software configurable input and output ►Multiple configurable modes to a single pin ►Voltage input ►Current input ►Voltage output ►Current output ►Digital input ►Digital output ►2-wire, 3-wire, or 4-wire RTD measurements ►Thermocouple measurement ►Overvoltage tolerant on screw terminal facing pins, powered or unpowered ►Auxiliary high voltage sense pins ►10 ppm/°C reference temperature coefficient ►16-bit, Σ-∆ ADC with optional 50 Hz and 60 Hz rejection ►14-bit monotonic DAC ►Unipolar and bipolar capability ►On-chip diagnostics including open-circuit and short-circuit de- tection ►Internal temperature sensor, ±5°C accuracy ►SPI-compatible ►Wide power supply range ►Programmable power control ►Temperature range: −40°C to +105°C ►48-lead LFCSP
APPLICATIONS
►Isolated industrial control systems ►Process control ►Factory automation ►Building control systems FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram input and output (GPIO) pins to support higher speed data rates. unipolar capability is required.
analog.com Rev. 0 | 2 of 103 Software Configurable Input and Output
REVISION HISTORY
1/2023—Revision 0: Initial Version
for AVDD and AVSS must be considered when setting supply voltages. Table 1. Voltage Output
Table 1. Voltage Output (Continued)
0 V to 12 V Range 405 nV/√Hz Measured at 1 kHz, midscale output
1 Guaranteed by design and characterization. per the recommended configuration. Note that the headroom specification for AVDD must be considered when setting supply voltages. Table 2. Current Output (IOUT)
Table 2. Current Output (IOUT) (Continued) 1 RSENSE accuracy directly impacts the TUE and gain error. 2 Guaranteed by design and characterization. recommended configuration. Note that the required input range for AVDD and AVSS must be considered when setting the supply voltages. Table 3. Voltage Input 1 Guaranteed by design and characterization.
Table 4. Current Input Externally Powered 1 RSENSE accuracy directly impacts the TUE and gain error. 2 Guaranteed by design and characterization. recommended configuration. Note that the headroom specification for AVDD must be considered when setting supply voltages. Table 5. Current Input Loop Powered
Table 5. Current Input Loop Powered (Continued) 1 RSENSE accuracy directly impacts the TUE and gain error. 2 Guaranteed by design and characterization. Table 6. Resistance 2-Wire Measurement 1 Guaranteed by design and characterization.
Table 7. 3-Wire RTD Measurement 1 Guaranteed by design and characterization. Table 8. 4-Wire RTD Measurement
Table 8. 4-Wire RTD Measurement (Continued) 1 Guaranteed by design and characterization. Table 9. Digital Input Logic
Table 9. Digital Input Logic (Continued) 1 Guaranteed by design and characterization. recommended configuration. Note that the headroom specification for AVDD must be considered when setting supply voltages. Table 10. Digital Input Loop Powered 1 Guaranteed by design and characterization.
Table 11. Digital Outputs (Sourcing and Sinking)
Table 11. Digital Outputs (Sourcing and Sinking) (Continued) 1 Guaranteed by design and characterization.
recommended configuration. Note that the required input range for AVDD and AVSS must be considered when setting the supply voltages. Table 12. ADC Specifications
10 SPS 50 Hz and 60 Hz rejection enabled
20 SPS 50 Hz and 60 Hz rejection enabled
0 V to +12 V, ±12V Typically used to measure the voltage across the I/OP to I/ON screw
Table 12. ADC Specifications (Continued) 1 Guaranteed by design and characterization; not production tested. Table 13. General Specifications Output Noise1 18 µV p-p 0.1 Hz to 10 Hz bandwidth.
Table 13. General Specifications (Continued)
1 Guaranteed by design and characterization. 2 If the charge pump is enabled, connect the CP_OUT pin to AVSS and ensure that there is no other source on AVSS.
+5.5 V, SDO CLOAD = 30 pF, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. Table 14. SPI Timing Specifications 1 All input signals are specified with tR= tF= 5 ns (10% to 90% of the voltage on the DVCC pin (VDVCC)) and timed from a voltage level of VDVCC/2. 2 Guaranteed by design and characterization; not production tested. 3 Charge pump voltage decays while in reset. Figure 2. SPI Timing Diagram
+5.5 V, PPC_CTRL CLOAD = 30 pF, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. Table 15. OWSI Timing Specifications 1 All input signals are specified with tR= fall time tF = 5 ns (10% to 90% of the voltage on the DVCC pin (VDVCC)) and timed from a voltage level of VDVCC/2. 2 Guaranteed by design and characterization; not production tested. Figure 3. OWSI Timing Diagram for a Successful Transmission Refer to the One-Wire Serial Interface section for more information.
TA = 25°C unless otherwise noted. Table 16. Absolute Maximum Ratings
2 It is important to manage the power dissipation of the AD74115 to ensure that
shutdown function to avoid damage to the AD74115. ing conditions for extended periods may affect product reliability. Table 17. Thermal Resistance
1 Based on simulated data using a JEDEC 2S2P thermal test board with a 5 × 5
specification JESD-51 for details.
2 Measured at the exposed paddle surface with the cold plate in direct contact
with the package top surface. sitive devices in and ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 18. AD74115, 48-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 4. Pin Configuration Table 19. Pin Function Description 2 REFOUT1 Internal 2.5 V Reference Output. The REFOUT pin must be connected to the REFIN pin to use the internal reference. 3 REFIN 2.5 V Reference Input. 4, 5, 36 RESERVED Do Not Connect (DNC). by SPI writes to the AD74115 and passed to the ADP1034 through this interface. 7 ADC_RDY Active Low, Open-Drain Output. This pin asserts when a new sequence of ADC conversion results is ready to be read. Connect this pin to a pull-up resistor to the DVCC pin. 8 RESET Hardware Reset Pin. Active low input. This pin resets the AD74115 to the power-on state. when this pin is asserted. Connect this pin to the DVCC pin via a pull-up resistor. 10 SCLK Serial Interface Clock. 11 SDI Serial Interface Data In. 12 SDO Serial Interface Data Out. 13 SYNC Serial Interface Frame Synchronization Pin. Active low input. 14 DVCC1 Digital Supply. Decouple this pin with the recommended capacitor listed in Table 35. connect the AVSS pin to the CP_OUT pin.
- Do not use this pin externally.
20 GPIO_A General-Purpose Input and Output Pin A. This pin can monitor the digital input comparator result. 21 GPIO_B General-Purpose Input and Output Pin B. This pin can control the external digital output circuit. 22 GPIO_C General-Purpose Input and Output Pin C. This pin can control the internal digital output circuit. 23 GPIO_D General-Purpose Input and Output Pin D. 24 AGND_SENSE Analog Ground Sense. Tie this pin to the I/ON screw terminal.
25 AVDD1 Positive Analog Supply
Table 19. Pin Function Description (Continued) 26 AVSS1 Negative Analog Supply. 27 SENSE_EXT2 High Voltage Sense Pin.
28 SENSE_EXT1 High Voltage Sense Pin
side of RSENSE through the off-chip filter. screw terminal side of RSENSE. RSENSE through the off-chip filter. 33 VIOUT Voltage or Current Force Pin. VIOUT provides a voltage or a current to the I/OP screw terminal. 34 CCOMP Compensation Capacitor Pin. CCOMP allows the AD74115 to drive high capacitive loads in the voltage output use case. Connect the capacitor between the CCOMP pin and the I/O screw terminal. measurement voltage range is 0 V to 2.5 V. For best performance, use an antialiasing filter on this pin. 38 DO_SRC_DGATE Smart Diode Gate Drive Pin. 39 DO_SRC_GATE Sourcing Digital Output Gate Drive. 41 DO_SRC_INT Internal Sourcing Digital Output. 42 DO_VDD1 Positive Supply for Digital Output Circuit. 43 DO_SNK_SNS Sinking Digital Output Sense. 44 DO_SNK_GATE Sinking Digital Output Gate Drive. 45 DO_SNK_INT Internal Sinking Digital Output. 48 ALDO1V81 1.8 V Analog LDO Output. Do not use ALDO1V8 externally. Exposed Pad Exposed Pad. Connect the exposed pad to the AVSS pin. 1 Connect the recommended decoupling capacitors shown in Table 35.
Figure 27. Function of Current Leakage Compensation
analog.com Rev. 0 | 29 of 103 ADC Offset Error For unipolar input ranges, ADC offset error is the deviation in LSBs from the zero-scale code (0x0000) when inputs are shorted, 0 V. For bipolar input ranges, ADC offset error is the deviation in LSBs from the midscale code (0x8000) when inputs are shorted, 0 V. ADC Gain Error Gain error applies to both unipolar and bipolar ranges. Gain error is a measure of the span error of the ADC. For input ranges, gain error is defined as the full-scale error minus the zero-scale error. The error is expressed in ppm FSR. DAC Offset Error Offset error is the deviation of the analog output from the ideal zero-scale output when the DAC output register is loaded with 0x0. The offset error is expressed in mV. DAC Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal midscale output of 0 V when the DAC output register is loaded with 0x2000. This error applies only to bipolar output ranges. DAC Gain Error Gain error is a measure of the span error of the DAC. This error is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. Total Unadjusted Error (TUE) TUE is the maximum deviation of the output from the ideal. TUE includes INL, offset, and gain error.
Figure 28. Detailed Functional Block Diagram The channel is configured by writing to the configuration registers. tional block diagram of the AD74115. withstand overvoltage scenarios such as miswire and surge events. the input and output terminals. ensure error free communications in noisy environments.
analog.com Rev. 0 | 31 of 103 analog supply, and VDVCC, which is the digital supply. See Table 13 for the voltage range of the three external supplies and the associated conditions. Powering on the AD74115 When powering up the AD74115, apply ground connections first. After power-up, the user must wait for the device power-up time (see Table 13) before any transaction to the device can take place. Upon initial power-up or a device reset of the AD74115, the output channel is disabled and placed in a high impedance state by default. Charge Pump The AD74115 has an internal charge pump that can be enabled to provide AVSS, the negative voltage supply. When only unipolar ca- pability is required, the charge pump can eliminate the requirement for the external AVSS supply voltage. Enable the charge pump using the CPUMP_EN bit. For correct operation, the charge pump requires an external capacitor (CPUMP fly capacitor) between the CPUMP_N pin and CPUMP_P pin. Externally connect the CP_OUT pin to AVSS. If using the charge pump, take care not to apply an external supply to the AVSS pin. When the charge pump is enabled, the ±12V bipolar output range is disabled. Reference The AD74115 can operate with either an external or an internal reference. The reference input requires 2.5 V for the AD74115 to function correctly. The reference voltage is internally buffered before being applied to the DAC and the ADC. If using the internal reference, the REFIN pin must be tied to the REFOUT pin. DEVICE FUNCTIONS The following sections describe the various programmable device functions of the AD74115 with block diagrams and guidelines on how to interpret the ADC results if converting with the default set- tings. These functions are programmed within the CH_FUNC_SET- UP register. Each device function is configured with default measurement set- tings. However, users can adjust these settings as required within the register map. High Impedance High impedance is the default function upon power-up or after a device reset. If a channel is held in high impedance for an extended time, such as when the analog input and output functions are not in use, it is recommended to enable a sinking burnout current of 1 μA. Enable the burnout current by programming the following bits in the I_BURNOUT_CONFIG register: ►BRN_VIOUT_EN to 1 ►BRN_VIOUT_POL to 0 ►BRN_VIOUT_CURR to 100 binary Interpreting ADC Data In high impedance mode, the ADC, by default, measures the voltage across the screw terminals (I/OP to I/ON) in a 0 V to 12 V range. Use the following equation to calculate the ADC measure- ment result: VADC = (ADC_CODE/65,536) × Voltage Range where: VADC is the measured voltage in volts. ADC_CODE is the value of the ADC_RESULT1 register. Voltage Range is the measurement range of the ADC and is 12 V. Voltage Output The voltage output amplifier can generate unipolar or bipolar voltag- es in the 0 V to +12 V and ±12 V ranges, respectively. Each range has 14 bits of resolution. The voltage on the low-side of the RSENSE is sensed on the SENSEL pin via a 2 kΩ resistor, which closes the feedback loop and maintains stability. In voltage output mode, the output range is set to 0 V to 12 V by default. To select bipolar mode, use the following sequence: ►Write 0x2000 to the DAC_CODE register to ensure 0 V output. ►Set the VOUT_RANGE bit in the OUTPUT_CONFIG register to 1 for bipolar outputs. ►Select the voltage output use case in the CH_FUNC bits, CH_FUNC_SETUP register. Figure 29 shows the current, voltage, and measurement paths of the voltage output mode.
Figure 29. Voltage Output Mode Configuration cuit error is flagged for that channel, and the ALERT pin asserts. current indicates that the AD74115 is sinking the current. ADC_CODE is the value of the ADC_RESULT1 register. Voltage Range is the full span of the ADC range, which is 5 V. RSENSE is the RSENSE resistor, which is 100 Ω.
VADC is the measured voltage in volts. ADC_CODE is the value of the ADC_RESULT1 register. Voltage Range is the measurement range of the ADC and is 12 V. measurement paths of the voltage input mode. Figure 31. Voltage Input Mode Configuration
power dissipated on the AD74115 device. ANALOG_IO_SC bit in the ALERT_STATUS register. I R SE NS E is the measured current in amps. ADC_CODE is the value of the ADC_RESULT1 register. Voltage Range is the full span of the ADC range and is 2.5 V. RSENSE is the sense resistor, which is set to 100 Ω. measurement paths of the current input, loop powered mode. Figure 33. Current Input, Loop Powered Mode Configuration
analog.com Rev. 0 | 39 of 103 How to Configure a 3-Wire RTD Measurement for Pt1000 RTD The following is an example of how to configure a 3-wire RTD measurement for the Pt1000 RTD: ►Select 3-wire or 4-wire resistance measurement in the CH_FUNC_SETUP register. ►Set CONV1_MUX to SENSELF to SENSE_EXT1 and CONV1_RANGE to 0 V to 12 V in the ADC_CONFIG register. ►Set RTD_CURRENT to 500 μA and RTD_MODE_SEL to 3-wire RTD mode in the RTD3W4W_CONFIG register. ►Set CONV1_EN and CONV_SEQ to start continuous conver- sions in the ADC_CONV_CTRL register. Open-Circuit Detection An open-circuit detect feature is available on the leads of the 3-wire RTD. The combination of excitation current and RTD and lead resistances generates voltages on the SENSEH and SENSE_EXT1 pins. If the voltage on either of these pins exceeds the open-circuit detect voltage (shown in Table 7), an open-circuit signal is asserted in the ALERT_STATUS register. Interpreting ADC Data In 3-wire RTD mode, configure the 16-bit, Σ-Δ ADC to measure the voltage from SENSELF to SENSE_EXT1. When a conversion is carried out, the ADC code reflects the ratio between RRTD and RREF. When using unipolar ADC ranges, use the ADC code to calculate the RTD resistance with the following equation: R RTD = ADC_CODE +5 65,536 × ADC_GAIN × R REF + 0.2 where: RRTD is the calculated RTD resistance in ohms. ADC_CODE is the code of the ADC_RESULT1 register. RREF has a value of 2100 Ω (the combined value of the SENSEH and RSENSE resistors). ADC_GAIN is the gain of the ADC in the selected ADC range. When using the 0 V to 0.625 V range (Pt100), the ADC_GAIN is 4. When using the 0 V to 12 V range (Pt1000), the ADC_GAIN is 1/4.8. When using bipolar ADC ranges, use the ADC code to calculate the RTD resistance with the following equation: R RTD = ADC_CODE ‐ 32,763 32,768 × ADC_GAIN × R REF + 0.2 where: RRTD is the calculated RTD resistance in ohms. ADC_CODE is the code of the ADC_RESULT1 register. RREF has a value of 2100 Ω (the combined value of the SENSEH and RSENSE resistors). ADC_GAIN is the gain of the ADC in the selected ADC range. When using the ±104 mV range (Cu10), the ADC_GAIN is 24. 4-Wire RTD Measurements 4-wire RTD measurements are supported with the AD74115. Use the CH_FUNC_SETUP register to configure the channel in 3-wire or 4-wire RTD mode. Configure the RTD_MODE_SEL bit for 4-wire RTD measurements in the RTD3W4W_CONFIG register. Figure 37 shows a simplified configuration of 4-wire RTD method. An excitation current, I1 is sourced to a single lead of the RTD via SENSEH. The fourth lead is connected to ground. There is no current flow in second and third leads of the RTD that are connected to SENSE_EXT2 and SENSE_EXT1, respectively; therefore, these pins are used to sense the voltage directly across the RTD. The full-scale range of the ADC is determined by the voltage across RREF, guaranteeing a fully ratiometric measurement. The excitation current applied to the RTD terminal can be pro- gramed to one of four values between 250 µA to 1 mA using the RTD_CURRENT bits in the RTD3W4W_CONFIG register. See Table 7 for the full list of excitation currents. Select the excitation current according to the RTD in use. Take care that the voltage generated on the SENSEHF pin (I1 × (RREF + RRTD)) is less than VAVCC. The SENSEHF pin voltage provides the positive reference to the ADC and must not exceed the value of VAVCC. The measurement range can be configured in the ADC_CONFIG register using the CONV1_RANGE bits. Select the best range to suit the RTD in use.
Figure 37. 4-Wire RTD Measurement Configuration CONV1_RANGE to 0 V to 0.625 V in the ADC_CONFIG register. RTD mode in the RTD3W4W_CONFIG register. sions in the ADC_CONV_CTRL register. dition on either T1 or Tl 4 (see Figure 37). RRTD is the calculated RTD resistance in ohms. ADC_CODE is the code of the ADC_RESULT1 register. ADC_GAIN is the gain of the ADC in the selected ADC range. When using the 0 V to 0.625 V range (Pt100), the ADC_GAIN is 4. RRTD is the calculated RTD resistance in ohms. ADC_CODE is the code of the ADC_RESULT1 register. ADC_GAIN is the gain of the ADC in the selected ADC range. When using the ±104 mV range (Cu10), the ADC_GAIN is 24. the input buffer if high speed digital input data rates are required. See Table 9 for buffered and unbuffered data rates. rator output, see the Debounce Function section.
analog.com Rev. 0 | 42 of 103 Digital Input Threshold Setting The digital input thresholds are set by an internal DAC. The refer- ence to this DAC is driven by either the VAVDD or the reference voltage, VREFIN. This reference is configured by writing to the DIN_THRESH_MODE bit within the DIN_CONFIG2 register. The specific threshold levels are programmed using the COMP_THRESH bits in the DIN_CONFIG2 register. There are sev- en bits available to configure the threshold, and the maximum programmable code is Decimal 98. The following equation shows the relationship between the pro- grammed code in the COMP_THRESH bits and the corresponding threshold voltage when the DAC reference is set to AVDD: V THRE SH AV DD = V AV DD × C od e − 48 where: VTHRESH (AVDD) is the comparator threshold expressed in volts. VAVDD is the AVDD supply value in volts. Code is the decimal code loaded to the COMP_THRESH bits. The following equation shows the relationship between the pro- grammed code in the COMP_THRESH bits and the corresponding threshold voltage when the DAC reference is set to VREFIN. VTHRESH (FIXED VOLTAGE) = VREFIN × (Code – 38)/5 where: VTHRESH (FIXED VOLTAGE) is the comparator threshold expressed in volts. VREFIN is the reference voltage. Code is the decimal code loaded to the COMP_THRESH bits. Digital Input Current Sink The AD74115 includes a programmable current sink. The current sink is programmed via the DIN_RANGE bit and the DIN_SINK bits within the DIN_CONFIG1 register. This current sink programmabili- ty enables compatibility with Type I, Type II, and Type III of the IEC 61131-2. Program the current sink and the threshold voltages to enable compatibility with Type I and Type III of the IEC 61131-2. For Type I and Type III, it is recommended to program the bits in the DIN_CONFIG1 and DIN_CONFIG2 registers as follows: ►DIN_RANGE bit: 0x0 ►DIN_SINK bits: 0x14 ►DIN_THRESH_MODE bit: 0x1 ►COMP_THRESH bits: 0x37 Programming these bits results in a typical current sink of 2.4 mA and a rising voltage trip point of typically 8.5 V. For Type II, it is recommended to program the DIN_CONFIG1 and DIN_CONFIG2 registers as follows: ►DIN_RANGE bit: 0x1 ►DIN_SINK bits: 0x1D ►DIN_THRESH_MODE bit: 0x1 ►COMP_THRESH bits: 0x37 Programming these bits result in a typical current sink of 6.96 mA and a rising voltage trip point of 8 V. Open-Circuit and Short-Circuit Detection The AD74115 has open-circuit and short-circuit detection capabili- ties and can be configured to be compatible with IEC 61131-3D. To use the open-circuit and short-circuit detection functions, enable the current sink by using the DIN_RANGE bit. Set the current using the DIN_SINK bits. To enable the open-circuit diagnostic, use the DIN_OC_DET_EN bit. An open circuit is detected if the input current is less than 0.35 mA. To enable the short-circuit diagnostic, use the DIN_SC_DET_EN bit. When the DIN_SC_DET_EN bit is set, an additional 4 mA of current sink is enabled. A short-circuit fault is triggered if the 4 mA sink limit is exceeded. Once an open-circuit or short-circuit fault is triggered, the appropri- ate bit is set in the ALERT_STATUS register, and the ALERT pin is asserted. For Type 3D diagnostics, it is recommended to program the DIN_CONFIG1 and DIN_CONFIG2 registers bits as follows: ►DIN_RANGE bit: 0x0 ►DIN_SINK bits: 0xF ►DIN_OC_DET_EN bit: 0x1 ►DIN_SC_DET_EN bit: 0x1 ►DIN_THRESH_MODE bit: 0x1 ►COMP_THRESH bits: 0x37 Programming these bits results in a typical current sink of 1.8 mA and a rising voltage trip point of typically 8.5 V. An open-circuit detection is triggered when sinking currents are less than 220 µA. A short-circuit detection is triggered when sinking currents are greater than typically 6.2 mA. Digital Input Inverter The debounced comparator signal can pass directly to the DIN_COMP_OUT register. Alternatively, the signal can be inverted before being sent to the DIN_COMP_OUT register. To enable this inverter, set the INV_DIN_COMP_OUT bit in the DIN_CONFIG1 register. Digital Input Counter A counter is available in the digital input modes, and the counter allows the user to count the debounced digital input edges. The
the COUNT_EN bit is set to 0. comparator. Table 9 shows the specified data rate. the DIN_UNBUF_EN bit in the DIN_CONFIG2 register. vals and passed to a user-programmable debounce block. Table 20. Digital Input Programmable Debounce Times
00 Bypass
Table 20. Digital Input Programmable Debounce Times (Continued) Figure 39 shows an example of Debounce Mode 0 in operation. begins to count up the duration of the signal at the new state.
Figure 39. Digital Input Debounce Mode 0 Timing Example
analog.com Rev. 0 | 47 of 103 Interpreting ADC Data The ADC is not required for digital input operation. However, the ADC is available for voltage and current measurements when the digital input, loop powered mode is enabled. In digital input, loop powered mode, the ADC, by default, measures the voltage across the I/OP to I/ON screw terminals in a 0 V to 12 V range. Use the ADC measurement result to calculate this voltage by using the following equation: VADC = (ADC_CODE/65,536) × Voltage Range where: VADC is the measured voltage in volts. ADC_CODE is the value of the ADC_RESULT1 register. Voltage Range is 12 V, the measurement range of the ADC. Digital Output The AD74115 supports sourcing and sinking digital outputs. An internal digital output function is available for sourcing or sinking up to 100 mA continuous current. For currents higher than 100 mA, use the external digital output function. A push-pull feature is also available that combines both the source and sink capabilities to provide high speed, high voltage switching. When the digital output functionality is enabled, the recommended configuration of the CH_FUNC_SETUP register is to set it to high impedance. Sourcing and Sinking Currents Greater Than 100 mA The external sourcing digital output operates with an external, P-channel field effect transistor (PFET), and the sinking digital output operates with external N-channel FET (NFET). Push-pull mode uses both PFET and NFET. Choose the FET types to suit the application requirements. Determine the absolute current value by the RSET and short-circuit voltage values. Short-circuit voltages are indicated in the Table 11. Configure the digital output using the DO_EXT_CONFIG register: ►Select source, sink, or push-pull capability by using the DO_EXT_MODE bits. ►Select the source of the data for the digital output circuit using the DO_EXT_SRC_SEL bit. The digital output data can be pro- vided by the SPI (via the DO_DATA_EXT bit) or by the GPIO_B pin for direct hardware control of the circuits. ►Configure the short-circuit timers using the DO_EXT_T1 and DO_EXT_T2 bits. See the Short-Circuit Protection section for more information on short-circuit functionality. Note that T1 short- circuit limits are not available in push-pull mode Once the configuration settings are applied, provide stimulus to turn on the selected external FET. For SPI control, a new write is re- quired to the DO_EXT_CONFIG register, to set the DO_DATA_EXT bit. Setting the DO_DATA_EXT to 1 turns on the selected external FET. In push-pull mode, set the bit to 0 to drive a low on the output and to 1 to drive a high on the output. For GPIO control, configure the GPIO_B pin to control the digital output circuit by writing 0x0004 to the GPIO_CONFIG1 register. Drive the GPIO_B pin high to turn on the FET. In push-pull mode, set the GPIO_B pin low for a low on the output and high for a high on the output. If changing from one digital output function to another, first disable the digital output function before changing to the new mode (set DO_EXT_MODE to digital output external disable). Figure 42 shows the current and voltage paths of the sourcing digital output mode with the external FET. Figure 43 shows the current and voltage paths of the sinking digital output mode with the external FETs.
VDO_VDD). This typical configuration is shown in Figure 42. power dissipation in this scenario is <50 mW. nal source with a smart diode in the DO_EXT_CONFIG register. Figure 44. Smart Diode Configuration for Current Sourcing with an External FET
Figure 47. Digital Output Programmable Short-Circuit Control current in the digital output circuit. ADC_CONV_CTRL register to guarantee measurement accuracy.
- Consider the additional enabled diagnostics when calculating
the current being sourced or sinked by the digital output circuit. calculating conversion times. AD74115. Write 1 to clear each bit in the ALERT_STATUS register. user to configure the device with a minimal set of commands. Table 21. Register Defaults Based on Channel Function Selection
Table 21. Register Defaults Based on Channel Function Selection (Continued)
Take care when switching from one channel function to another. changing to another function. register before transitioning to the new channel function. output stage powers up to 0 V. Refer to the Voltage Output section. wait 200 μs before updating the DAC code. are described in the Using Channel Functions section. the measurements available for Conversion 2. range control that can be configured in the ADC_CONFIG register. idle mode, and conversions are stopped. bled diagnostic until a command is written to stop the conversions. the ADC_CONV_CTRL register to idle mode or power-down mode. the continuous conversions after making the appropriate changes. AG_RESULTn registers and the ADC_RDY pin is asserted. Table 22. Selection Options for ADC Conversion 1
00 SENSELF to AGND_SENSE Voltage measurement across the I/OP and I/ON screw terminals
01 SENSEHF to SENSELF Voltage measurement across the RSENSE resistor
11 SENSELF to SENSE_EXT1 Voltage measurement across SENSE_EXT1 and SENSELF for 3-wire RTD measurement
Table 23. Selection Options for ADC Conversion 2
00 SENSE_EXT1 to AGND_SENSEEnables single-ended monitor of SENSE_EXT1 pin
01 SENSE_EXT2 to AGND_SENSEEnables single-ended monitor of SENSE_EXT2 pin
10 SENSE_EXT2 to SENSE_EXT1Enables differential measurements
11 AGND to AGND Diagnostic
can be used for a number of functions.
- An appropriate antialiasing filter can be added to the pin being
VMIN is the minimum input voltage of the selected ADC range. VADC is the measured voltage in volts. ADC_CODE is value of the ADC_RESULT2 register. Voltage Range is the selected measurement range of the ADC. the 4-Wire RTD Measurements section for more details. measuring voltages with the on-board ADC. Table 24. Ideal Output Code to Input Voltage Relationship
0 V to +12 V 0 V +6 V 12 V – 1 LSB
1 1 LSB = (Full Scale – Zero Scale)/65,536. Table 25. Ideal Output Code to Input Current Relationship 1 1 LSB = (Full Scale – Zero Scale)/65,536.
when the ADC is continuously converting on a single channel. Table 27. Peak-to-Peak Noise in LSBs per Voltage Range and Output Data Rate (Inputs Shorted)
scaled to be measurable within the ADC range. required to calculate the diagnostic value. age range is the ADC measurement range and is 2.5 V. Table 28. User-Selectable Diagnostics1
architecture is inherently monotonic and linear. option is to load a code to the DAC from the DAC_CODE register. the DAC code is loaded to the DAC. for each of the available output ranges. Table 29. Ideal DAC Input Code to Output Relationship
via the OUTPUT_CONFIG register. to zero-scale) DAC update that is available on the AD74115. TIVE value and does not ramp to the end code. Table 30. Programmable Slew Times for a Zero-Scale to Full-Scale Code Update 1 These are theoretical values. The final slew rate is limited by the CLOAD value.
analog.com Rev. 0 | 63 of 103 Driving Inductive Loads It is recommended to use the digital slew rate control when driving inductive loads greater than approximately 4 mH. Controlling the output slew rate minimizes ringing when stepping the output current by minimizing the current rate of change (di/dt). See the IOUT typical performance of the settling time with an inductive load with and without the slew rate enabled in the Figure 11. RESET FUNCTION After the AD74115 is reset, all registers are reset to the default state, and the calibration memory is refreshed. The device is config- ured in high impedance mode. A reset can be initiated in several ways. The hardware reset is initiated by pulsing the RESET pin low. The RESET pulse width must comply with the specifications in Table 14. A software reset is initiated by writing the 0x15FA code (Software Reset Key 1) followed by the 0xAF51 code (Software Reset Key 2) to the CMD_KEY register. A reset can also be initiated via the thermal reset function, which is described in the Thermal Alert and Thermal Reset section. If the VDLDO1V8 or the VDVCC drop below the specified power supply monitors threshold highlighted in Table 13 the internal power-on reset function resets the AD74115. The device does not come out of reset until the VDLDO1V8 and the VDVCC rise above these voltage levels. After a reset cycle completes, the RESET_OCCURRED bit is set in the ALERT_STATUS register. If an SPI transfer is attempted before the reset cycle is complete (see Table 13 for typical reset time), the CAL_MEM_ERR bit in the SUPPLY_ALERT_STATUS register is also set to indicate that the calibration memory is not fully refreshed. After the reset time elapses, clear these bits in the ALERT_STATUS register before continuing to use the device. FAULTS AND ALERTS The AD74115 is equipped with several fault monitors to detect an error condition. If an alert or fault condition occurs, the ALERT pin asserts. To determine the source of the alert condition, read the ALERT_ STATUS register. This register contains a latched bit for each alert condition. After the error condition is removed, clear the activated flag by writ- ing 1 to the location of the corresponding bits in the ALERT_STA- TUS register (write 0xFFFF to the ALERT_STATUS register to clear all alert bits). Alerts asserted in SUPPLY_ALERT_STATUS must be cleared before the ALERT_STATUS register. The LIVE_STATUS register is a live representation of the error conditions. The bits in this register are not latched and clear automatically when the error condition is no longer present. The ALERT_MASK register prevents error conditions from activat- ing the ALERT pin. Channel Faults The AD74115 is equipped with multiple open-circuit and short-cir- cuit faults in the various functions as described in the Device Functions section. Manage faults as these faults appear and reset the channel, if necessary, to avoid overheating the device. Power Supply Monitors The AD74115 includes six power supply monitors to detect a supply failure. If any of the supplies fall to less than the defined threshold detailed in Table 13, the corresponding bit is set in the ALERT_STATUS register. Thermal Alert and Thermal Reset If the AD74115 die temperature reaches the alert temperature described in Table 13, a high temperature error bit (TEMP_ALERT) is set in the ALERT_STATUS register to alert the user of the increasing die temperature. The device can also be configured to reset at higher die temper- atures. To reset the device at higher temperatures, enable the thermal reset function by setting the EN_THERM_RST bit in the THERM_RST register. After this bit is set, the device goes through a full reset after the die temperature reaches the reset temperature described in Table 13. Burnout Currents Burnout currents are used to verify the integrity of an attached sensor and to ensure that it has not gone open circuit before taking a measurement from it. The AD74115 can be enabled to provide a user programmable, current source that can be programmed to a fixed value between 50 nA and 10 μA. Burnout currents are available on the VIOUT (to monitor the I/OP screw terminal), SENSE_EXT1, and SENSE_EXT2 pins and can be programmed to source or sink current. The burnout current sources are disabled on power up. Program the burnout current using the bits in the I_BURNOUT_CONFIG register. The full list of available current settings can be found in Table 13. The current source can be enabled at all times or alternatively enabled when needed for diagnostic purposes. When a burnout current source is enabled, the selected current is switched onto the selected pin, and it flows in the external load. FET LEAKAGE COMPENSATION A software configurable input and output solution can include a precision analog input and output capability along with a high current, digital output capability on a single screw terminal. In this case, the external FET used in the digital output function may
By default, a weak pull-down is enabled on the GPIO_x pins. GP_WK_PD_EN bit to 0 in the relevant GPIO_CONFIGx register. GPO_DATA bit in the GPIO_CONFIGx registers. Table 31. Writing to a Register Table 32. First Frame of a Readback Sequence ►An 8-bit CRC is returned in Bits[D7:D0]. Figure 54 shows the timing diagram of the two-stage readback. Figure 54. 2-Stage Readback Timing Diagram Table 33. SDO Contents for a Read Operation When the SPI_RD_RET_INFO Bit = 0
1 READBACK_ADDR[6:0] Read data CRC
Table 34. SDO Contents for a Read Operation When the SPI_RD_RET_INFO Bit = 1
asserted, and the ALERT pin goes low. there are no SPI errors during the read transaction. register. Mask the SPI_ERR bit via the ALERT_MASK register. Figure 56. CRC Timing
analog.com Rev. 0 | 70 of 103 OWSI CRC To ensure that data is received correctly in noisy environments, the AD74115 has a CRC implemented in the OWSI. This CRC is based on a 5-bit CRC. The AD74115 generates a 5-bit frame check sequence using the following polynomial: C(x) = x5+ x2 + 1 This 5-bit frame check sequence is added to the end of the 11-bit data-word, and the full 16-bit word is sent to the subordinate device before expecting an acknowledge sequence. Subordinate device check if the corresponding CRC is valid and responds with an acknowledge sequence. If the CRC check is not valid, the no acknowledge (NOACK) sequence is issued, and data is ignored. The AD74115 asserts the PPC_TX_ACK_ERR bit in the PPC_AC- TIVE register when NOACK sequence is noticed. The PPC_ERR bit is also asserted in the ALERT_STATUS register. Clear the PPC_ERR bit (ALERT_STATUS register) by writing a 1, which returns the ALERT pin high (assuming that there are no other active alerts). The PPC_ERR error bit can be masked by writing to the relevant bit in the ALERT_MASK register. SYSTEM LEVEL BLOCK DIAGRAM Figure 58 shows the connectivity between the AD74115 and the ADP1034. Figure 58 shows a fully isolated solution for a single- channel software configurable input and output. The VAVDD, VAVCC, VDVCC, and VAVSS supply voltages for the AD74115 are provided by the ADP1034. The AVDD supply voltage can be dynamically controlled from the host controller using the programmable power control function. Refer to the Power and Isolation section for more information on the programmable power control feature using the ADP1034. The output power available from the ADP1034 is dependent on the input supply voltage to the VINP pin of the ADP1034. The total power required to be delivered to the AD74115 and to the end load must be considered when choosing the system supply voltage. Refer to the ADP1034 for more information on power delivery. The connectivity shown in Figure 58 allows the AD74115 to operate in bipolar mode with all of the modes of operation of the device that can be delivered on two screw terminals. An external field supply is only required if digital output currents greater than 100 mA are required with this configuration. The SENSE_EXT1 and SENSE_EXT2 pins on the AD74115 can also be connected to additional screw terminals for 3-wire and 4-wire measurements, if required.
Figure 58. AD74115 and ADP1034 System Level Diagram
Table 35. External Components SENSEHF Filter Resistor3 2.7 kΩ Generic Generic 1% accuracy. SENSELF Filter Resistor3 2.7 kΩ Generic Generic 1% accuracy. SENSEL 2 kΩ Generic Generic 1% accuracy.
36 V TVS 36 SMBJ36CA It is recommended to use low leakage
Table 35. External Components (Continued) PFET for Sourcing Only 100 Si7113ADN Suitable for sourcing designs. NFET for Sinking Only 100 SiA416DJ Suitable for sinking designs. desired current resolution and range.
36 V TVS Generic SMBJ36CA
Filter Resistor3, 4 2.7 kΩ Generic Generic Optional. Filter Capacitor3, 4 4.7 nF 100 Generic Optional. Filter Resistor3, 4 2.7 kΩ Generic Generic Optional. Filter Capacitor3, 4 4.7 nF Generic Generic Optional. 1 Use recommended components or ones that are similar. 2 Voltage rating can be reduced if charge pump is used instead of the external supply. 3 Antialiasing filter values provide a compromise in performance for all use cases and conditions. These values can be adjusted to optimize for specific design conditions. 4 Not recommended for 3-wire and 4-wire resistance measurements. limit the capacitance to ground on the PPC_CTRL pin to 30 pF. screw terminal must also be tied to this ground plane. rectly to the pad of the RSENSE resistor. pad of the external RSET resistors. recommended to directly connect the AGND_SENSE pin to ground.
only access, R/W indicates read and write access, R/W1C indicates read, write, or clear, and W indicates write only access. Table 36. Register Summary
Use the following registers to configure the input and output functionality and to take measurements from the AD74115. Read only register. Writing to this register results in a no operation (NOP) command. Table 37. Bit Descriptions for NOP DIN_CONFIG1, DIN_CONFIG2 and RTD3W4W_CONFIG registers can change. When changing the function, the high impedance function must be programmed first, before programming the new function. Table 38. Bit Descriptions for CH_FUNC_SETUP listed as follows select the high impedance function. 0000: high impedance. The ADC is functional in this mode. 0001: voltage output. Force voltage, measure current. 0010: current output. Force current, measure voltage. 0011: voltage input. Measures the voltage between the I/OP and I/ON screw terminals. 0100: current input, externally powered. 0101: current input, loop powered. 0110: 2-wire resistance measurement. 0111: 3-wire or 4-wire resistance measurement. 1001: digital input, loop powered.
Table 39. Bit Descriptions for ADC_CONFIG 000: 10 SPS. Provides 50 Hz and 60 Hz noise rejection. 001: 20 SPS. Provides 50 Hz and 60 Hz noise rejection. 000: 10 SPS. Provides 50 Hz and 60 Hz noise rejection. 001: 20 SPS. Provides 50 Hz and 60 Hz noise rejection. range. Note that these bits can change when the CH_FUNC_SETUP register is programmed. 00: SENSE_EXT1 to AGND_SENSE. 01: SENSE_EXT2 to AGND_SENSE. 10: SENSE_EXT2 to SENSE_EXT1.
Table 39. Bit Descriptions for ADC_CONFIG (Continued) 10: SENSE_EXT2 to SENSE_EXT1. This register contains some settings to allow for power optimization of the channel. Table 40. Bit Descriptions for PWR_OPTIM_CONFIG 0: the sense AGND buffer is in low power mode. 1: the sense AGND buffer is in full power mode. 0: the SENSE_LF buffer is in low power mode. 1: the SENSE_LF buffer is in full power mode. 0: the SENSE_HF buffer is in low power mode. 1: the SENSE_HF buffer is in full power mode. 0: the SENSE_EXT2 buffer is in low power mode. 1: the SENSE_EXT2 buffer is in full power mode. 0: the SENSE_EXT1 buffer is in low power mode. 1: the SENSE_EXT1 buffer is in full power mode. This register (along with DIN_CONFIG2) is used to configure the digital input function of the channel.
Table 41. Bit Descriptions for DIN_CONFIG1 inputs are counted. If INV_DIN_COMP_OUT is 1, the negative edges of debounced inputs are counted. The count is reflected in the DIN_COUNTER register. 0: Range 0. Range from 0 mA to 3.7 mA in steps of 120 μA and ~2 kΩ of series resistance. 1: Range 1. Range from 0 mA to 7.4 mA in steps of 240 μA and ~1 kΩ of series resistance. to 0 when the corresponding CH_FUNC_SETUP register is written, irrespective of the function. decrements when the signal is deasserted. bypass the debounce circuit. This register (along with DIN_CONFIG1) is used to configure the digital input function of the channel. Table 42. Bit Descriptions for DIN_CONFIG2
Table 42. Bit Descriptions for DIN_CONFIG2 (Continued) described in the Digital Input Logic section). described in the Digital Input Logic section). 0: the threshold scales with AVDD. The threshold range is from −0.96 × AVDD to AVDD. 1: fixed threshold. Threshold is from −19 V to +30 V. This register configures the output settings of the channel. Table 43. Bit Descriptions for OUTPUT_CONFIG 00: slewing disabled. Slewing stops immediately when disabled, there are no further updates to the DAC code. 01: enable linear slew on the DAC output. 00: voltage step size of 0.8% of full-scale DAC voltage. 01: voltage step size of 1.5% of full-scale DAC voltage. 10: voltage step size of 6.1% of full-scale DAC voltage. 11: voltage step size of 22.2% of full-scale DAC voltage. 00: update at a rate of 4 kHz. 01: update at a rate of 64 kHz. 10: update at a rate of 150 kHz. 11: update at a rate of 240 kHz. 0: Current-Limit 0. VOUT: 32 mA source or sink. IOUT: 4 mA sink.
Table 43. Bit Descriptions for OUTPUT_CONFIG (Continued) 1: Current-Limit 1. VOUT: 16 mA source or sink. IOUT: 1 mA sink. This register configures the 3-wire and 4-wire RTD measurements. Table 44. Bit Descriptions for RTD3W4W_CONFIG configuration of the CH_FUNC_SETUP register is to set it to high impedance. Table 45. Bit Descriptions for DO_INT_CONFIG 0: source or sink mode, switch off the FET. Push-pull mode: sink current. 1: source or sink mode, switch on the FET. Push-pull mode: source current.
Table 45. Bit Descriptions for DO_INT_CONFIG (Continued) detected. Note T1 is not available in push-pull mode of operation.
register as an input to the digital output circuit. 0: direct software control of the FET. When under software control, the FET is controlled via DO_DATA_INT. disable mode is the intermediate step. 00: digital output internal disable. 01: digital output internal source. 10:digital output internal sink. enables the FET sinking current, and a 1 from the data source enables the FET sourcing current. configuration of the CH_FUNC_SETUP register is to set it to high impedance.
Table 46. Bit Descriptions for DO_EXT_CONFIG [13:9] DO_EXT_T2 External Digital Output Short-Circuit 2 Timer. Set these bits to program the T2 short-circuit duration. damage to the selected external FET.
Table 46. Bit Descriptions for DO_EXT_CONFIG (Continued) detected. Note T1 is not available in push-pull mode of operation. register as an input to the digital output circuit. 0: direct software control of the FET. When under software control, the FET is controlled via DO_DATA_EXT. external disable mode is the intermediate step. 000: digital output external disable. the FET sinking, and a 1 from the data source enables the FET sourcing. 100: external source with smart diode.
This register configures the burnout currents for the VIOUT, SENSE_EXT1, and SENSE_EXT2 pins. SENSE_EXT2 Burnout Polarity. SENSE_EXT1 Burnout Polarity. Table 47. Bit Descriptions for I_BURNOUT_CONFIG 000: burnout current disabled. 000: burnout current disabled. 000: burnout current disabled.
This register is used to set the DAC code for the output functions. The DAC_CODE register is not reset by changing channel functions. Table 48. Bit Descriptions for DAC_CODE This register displays the current value of the code loaded to the DAC. If slewing is enabled, this register reflects the current slew step. Table 49. Bit Descriptions for DAC_ACTIVE General-Purpose Input Data Bit. Table 50. Bit Descriptions for GPIO_CONFIG0 0: drive a logic low on GPIO_x pin. 1: drive a logic high on GPIO_x pin.
Table 50. Bit Descriptions for GPIO_CONFIG0 (Continued) 000: high impedance. The GPIO_x output driver is off. The GPIO_x pad input buffer is disabled. 001: configured as an output. The output level is set by the GPO_DATA bit. The GPIO_x input buffer is disabled. enabled so that the output data can also be read via GPI_DATA. 011: configured as an input. The GPIO_x output driver is configured in high impedance state. 100: configured to monitor the output of the digital input comparator. General-Purpose Input Data Bit. Table 51. Bit Descriptions for GPIO_CONFIG1 0: drive a logic low on GPIO_x pin. 1: drive a logic high on GPIO_x pin. 000: high impedance. The GPIO_x output driver is off. The GPIO_x pad input buffer is disabled. 001: configured as an output. The output level is set by the GPO_DATA bit. The GPIO input buffer is disabled. enabled so that the output data can also be read via GPI_DATA. 011: configured as an input. GPIO_x output driver is configured in high impedance state. 100: configured to drive the external digital output FET.
General-Purpose Input Data Bit. Table 52. Bit Descriptions for GPIO_CONFIG2 0: drive a logic low on GPIO_x pin. 1: drive a logic high on GPIO_x pin. 000: high impedance. The GPIO_x output driver is off. The GPIO_x pad input buffer is disabled. 001: configured as an output. The output level is set by the GPO_DATA bit. The GPIO_x input buffer is disabled. enabled so that the output data can also be read via GPI_DATA. 011: configured as an input. GPIO_x output driver is configured in high impedance state. 100: configured to drive internal digital output FET. General-Purpose Input Data Bit. Table 53. Bit Descriptions for GPIO_CONFIG3 0: drive a logic low on GPIO_x pin. 1: drive a logic high on GPIO_x pin.
Table 53. Bit Descriptions for GPIO_CONFIG3 (Continued) 000: high impedance. The GPIO_x output driver is off. The GPIO_x pad input buffer is disabled. 001: configured as an output. The output level is set by the GPO_DATA bit. The GPIO_x input buffer is disabled. enabled so that the output data can also be read via GPI_DATA. 011: configured as an input. GPIO_x output driver is configured in high impedance state. 100: the GPIO_x output driver is off. The GPIO_x pad input buffer is disabled. DO_EXT_MODE is programmed to digital output external disable. Table 54. Bit Descriptions for FET_LKG_COMP 0: leakage compensation circuit off. 1: leakage compensation circuit on. 0: leakage compensation circuit off. 1: leakage compensation circuit on. The internal charge pump is enabled in this register when the unipolar capability is required. Table 55. Bit Descriptions for CHARGE_PUMP
This register controls the ADC conversions that must be performed. Disable ADC conversions before making any changes to the ADC_CONV_CTRL register. TUS register is 0 before enabling the next sequence. Table 56. Bit Descriptions for ADC_CONV_CTRL 00: sampling rate of 20 SPS and provides 50 Hz and 60 Hz noise rejection. 01: sampling rate of 4.8 kSPS. 10: sampling rate of 9.6 kSPS. sequence and leave the ADC powered up. diagnostic. Once complete, ADC moves to the idle state. 10: start continuous conversions. Sequences continuously through the enabled channels and diagnostics. power up if subsequent conversions are requested. This register assigns diagnostics to the four available diagnostics inputs.
Table 57. Bit Descriptions for DIAG_ASSIGN 0000: assign AGND to Diagnostic 3. 0001: assign the temperature sensor to Diagnostic 3. 0010: assign DVCC to Diagnostic 3. 0011: assign AVCC to Diagnostic 3. 0100: assign ALDO1V8 to Diagnostic 3. 0101: assign DLDO1V8 to Diagnostic 3. 0110: assign REFOUT to Diagnostic 3. 0111: assign AVDD to Diagnostic 3. 1000: assign AVSS to Diagnostic 3. 1001: assign LVIN to Diagnostic 3. 1010: assign SENSEL to Diagnostic 3. 1011: assign SENSE_EXT1 to Diagnostic 3. 1100: assign SENSE_EXT2 to Diagnostic 3. 1101: assign DO_VDD to Diagnostic 3. 1110: assign AGND to Diagnostic 3. 1111: measure sourcing current from the internal digital output. 0000: assign AGND to Diagnostic 2. 0001: assign the temperature sensor to Diagnostic 2. 0010: assign DVCC to Diagnostic 2. 0011: assign AVCC to Diagnostic 2. 0100: assign ALDO1V8 to Diagnostic 2. 0101: assign DLDO1V8 to Diagnostic 2. 0110: assign REFOUT to Diagnostic 2. 0111: assign AVDD to Diagnostic 2. 1000: assign AVSS to Diagnostic 2. 1001: assign LVIN to Diagnostic 2. 1010: assign SENSEL to Diagnostic 2. 1011: assign SENSE_EXT1 to Diagnostic 2. 1100: assign SENSE_EXT2 to Diagnostic 2. 1101: assign DO_VDD to Diagnostic 2. 1110: assign AGND to Diagnostic 2. 1111: measure sinking current from the internal digital output. 0000: assign AGND to Diagnostic 1. 0001: assign the temperature sensor to Diagnostic 1. 0010: assign DVCC to Diagnostic 1. 0011: assign AVCC to Diagnostic 1. 0100: assign ALDO1V8 to Diagnostic 1. 0101: assign DLDO1V8 to Diagnostic 1. 0110: assign REFOUT to Diagnostic 1.
Table 57. Bit Descriptions for DIAG_ASSIGN (Continued) 0111: assign AVDD to Diagnostic 1. 1000: assign AVSS to Diagnostic 1. 1001: assign LVIN to Diagnostic 1. 1010: assign SENSEL to Diagnostic 1. 1011: assign SENSE_EXT1 to Diagnostic 1. 1100: assign SENSE_EXT2 to Diagnostic 1. 1101: assign DO_VDD to Diagnostic 1. 1110: assign AGND to Diagnostic 1. 1111: measure sourcing current from the external digital output. 0000: assign AGND to Diagnostic 0. 0001: assign the temperature sensor to Diagnostic 0. 0010: assign DVCC to Diagnostic 0. 0011: assign AVCC to Diagnostic 0. 0100: assign ALDO1V8 to Diagnostic 0. 0101: assign DLDO1V8 to Diagnostic 0. 0110: assign REFOUT to Diagnostic 0. 0111: assign AVDD to Diagnostic 0. 1000: assign AVSS to Diagnostic 0. 1001: assign LVIN to Diagnostic 0. 1010: assign SENSEL to Diagnostic 0. 1011: assign SENSE_EXT1 to Diagnostic 0. 1100: assign SENSE_EXT2 to Diagnostic 0. 1101: assign DO_VDD to Diagnostic 0. 1110: assign AGND to Diagnostic 0. 1111: measure sinking current from the external digital output. This register reflects the debounced output of the digital input comparator. Table 58. Bit Descriptions for DIN_COMP_OUT
ADC Conversion or Saturation Error. Digital Input Short-Circuit Error. Digital Input Open-Circuit Error. Table 59. Bit Descriptions for ALERT_STATUS analog input or output functions. analog input or output functions. FET is in the T1 period of operation. FET is in the T1 period of operation. PPC_TX_BUSY_ERR or the PPC_TX_ACK_ERR asserting in the PPC_ACTIVE register. clear the flag. Note that a mask bit is not provided for this bit. This register contains the live status of some of the status bits. The bits are not latched and directly reflect the status bits.
Current Status of TEMP_ALERT. Current Status of Digital Input Short-Circuit. Table 60. Bit Descriptions for LIVE_STATUS during the T1 short-circuit time. assert during the T1 short-circuit time. but the ADC_DATA_RDY status bit stays asserted until a user writes 1 to clear the bit. This register contains the 16 bits of the ADC conversion result.
Table 61. Bit Descriptions for ADC_RESULT1 This register contains the 16 bits of the ADC conversion result. Table 62. Bit Descriptions for ADC_RESULT2 These four registers contain the 16-bit diagnostic conversion results. Table 63. Bit Descriptions for ADC_DIAG_RESULTx from full scale back to 0; therefore, read this register often enough to avoid unexpected roll-over. Note that, when the enable signal is low, the count is frozen. The INV_DIN_COMP_OUT bit inverts the deglitched output allowing the counter increment edge to be modified. Table 64. Bit Descriptions for DIN_COUNTER INV_DIN_COMP_OUT bit inverts the deglitched output allowing the counter increment edge to be modified.
This register contains the supply alert status bits. Once the alert condition has been removed, write 1 to clear the bits in this register. Table 65. Bit Descriptions for SUPPLY_ALERT_STATUS corresponding status bits in the ALERT_STATUS register. To mask a specific alert condition, set the corresponding mask bit to 1. Note that masking a bit does not prevent it from setting the equivalent alert bit in the ALERT_STATUS register. Mask Bit for DO_INT_TIMEOUT. Mask Bit for TEMP_ALERT. Mask Bit for DO_EXT_TIMEOUT. Mask Bit for ADC_ERR. Mask Bit for DO_INT_SC. Mask Bit for DI_SC_ERR. Mask Bit for DO_EXT_SC. Mask Bit for DI_OC_ERR. Mask Bit for DO_THERM_RESET.
Table 66. Bit Descriptions for ALERT_MASK line up the corresponding status bits in the SUPPLY_ALERT_STATUS register. To mask a particular alert, set the corresponding mask bit to 1. Note that masking a bit does not prevent it from setting the equivalent alert bit in the ALERT_STATUS register. Table 67. Bit Descriptions for SUPPLY_ALERT_MASK This register selects the address of the register required to be read back and determines the contents of the SPI readback frame.
Table 68. Bit Descriptions for READ_SELECT 9 AUTO_RD_EN Automatic Read Enabled. When this bit is set to 1, read data is returned on the SDO on every SPI access. The location read is determined by READBACK_ADDR. ADC_RESULTx, ADC_DIAG_RESULTx, and DIN_COUNTER registers. Table 69. Bit Descriptions for BURST_READ_SEL skipped during the burst read. Bit 0: enable burst read of the ALERT_STATUS register. Bit 1: enable burst read of the LIVE_STATUS register. Bit 2: enable burst read of the ADC_RESULT1 register. Bit 3: enable burst read of the ADC_RESULT2 register. Bit 4: enable burst read of the ADC_DIAG_RESULT0 register. Bit 5: enable burst read of the ADC_DIAG_RESULT1 register. Bit 6: enable burst read of the ADC_DIAG_RESULT2 register. Bit 7: enable burst read of the ADC_DIAG_RESULT3 register. Bit 8: enable burst read of the DIN_COUNTER register. Bit 9: enable burst read of the SUPPLY_ALERT_STATUS register.
configured via the OWSI to adjust the AD74115 power supply, AVDD. Table 70. Bit Descriptions for PPC_TX This read only register provides status information on the OWSI transactions. Table 71. Bit Descriptions for PPC_ACTIVE write to TX_DATA while this bit is set. This bit deasserts once TX_DATA is transmitted.
Table 72. Bit Descriptions for THERM_RST This register is used to issue specific commands to the device. Table 73. Bit Descriptions for CMD_KEY writes must be back to back. writes must be back to back. avoid errant trim bits being passed to the oscillator. Table 74. Bit Descriptions for SCRATCHx
Table 75. Bit Descriptions for SILICON_REV Table 76. Bit Descriptions for SILICON_ID0 Table 77. Bit Descriptions for SILICON_ID1 Table 78. Bit Descriptions for SILICON_ID2
Table 79. Bit Descriptions for SILICON_ID3
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP]