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16-Bit, Isolated Sigma-Delta Modulator Data Sheet AD7403

FEATURES

5 MHz to 20 MHz external clock input rate

16 bits, no missing codes Signal-to-noise ratio (SNR): 88 dB typical Effective number of bits (ENOB): 14.2 bits typical Offset drift vs. temperature AD7403: 1.6 µV/°C typical AD7403-8: 2 µV/°C typical On-board digital isolator On-board reference Full-scale analog input range: ±320 mV Operating range AD7403: −40°C to + 125°C AD7403-8: −40°C to + 105°C High common-mode transient immunity: >25 kV/µs Wide-body SOIC with increased creepage package Slew rate limited output for low EMI Safety and regulatory approvals UL recognition

5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 1250 VPEAK

APPLICATIONS

Analog-to-digital and optoisolator replacements FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7403 BUF REF CLK DECODER GND1 GND2 MDAT MCLKIN (5MHz TO 20MHz) 12196-001 VIN+ VIN– CLK ENCODER DATA ENCODER DATA DECODER Σ-Δ ADC Figure 1. GENERAL DESCRIPTION The AD74031 is a high performance, second-order, Σ-Δ modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The device operates from a

5 V (VDD1) power supply and accepts a differential input signal

of ±250 mV (±320 mV full-scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required. The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 20 MHz. The original information can be reconstructed with an appropriate digital filter to achieve 88 dB signal to noise ratio (SNR) at 78.1 kSPS. The serial input/output can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed complementary metal oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7403 device is offered in a 16-lead, wide-body SOIC package and has an oper- ating temperature range of −40°C to +125°C. The AD7403-8 device is offered in an 8-lead, wide-body SOIC package and has an operating temperature range of −40°C to +105°C. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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Rev. B | Page 2 of 24 TABLE OF CONTENTS DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation

REVISION HISTORY

5/15—Rev. A to Rev. B Added Power Supply Considerations Section, Figure 41, and 11/14—Rev. 0 to Rev. A 4/14—Revision 0: Initial Version

VDD1 = 4.5 V to 5.5 V , VDD2 = 3 V to 5.5 V , VIN+ = −250 mV to +250 mV , VIN− = 0 V, TA = −40°C to +125°C, fMCLKIN1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits Integral Nonlinearity (INL)2 ±2 ±12 LSB Differential Nonlinearity (DNL)2 ±0.99 LSB Guaranteed no missed codes to 16 bits Offset Error2 ±0.2 ±0.75 mV Offset Drift vs. Temperature3 1.6 3.8 µV/°C 1.3 3.1 µV/°C 0°C to 85°C Offset Drift vs. VDD13 50 µV/V Gain Error2 ±0.2 ±0.8 % FSR fMCLKIN = 16 MHz ±0.2 ±0.8 % FSR fMCLKIN = 20 MHz, TA = −40°C to +85°C ±0.2 ±1.2 % FSR fMCLKIN = 20 MHz Gain Error Drift vs. Temperature3 65 95 ppm/°C 40 60 µV/°C Gain Error Drift vs. VDD13 ±0.6 mV/V ANALOG INPUT Input Voltage Range −320 +320 mV Full-scale range −250 +250 mV For specified performance Input Common-Mode Voltage Range −200 to +300 mV Dynamic Input Current ±45 ±50 µA VIN+ = ±250 mV, VIN− = 0 V 0.05 µA VIN+ = 0 V, VIN− = 0 V DC Leakage Current ±0.01 ±0.6 µA Input Capacitance 14 pF DYNAMIC SPECIFICATIONS VIN+ = 1 kHz Signal-to-Noise-and-Distortion Ratio (SINAD)2 81 87 dB 83 87 dB −40°C to +85°C Signal-to-Noise Ratio (SNR)2 86 88 dB Total Harmonic Distortion (THD)2 −96 dB Peak Harmonic or Spurious Noise (SFDR)2 −97 dB Effective Number of Bits (ENOB)2 13.1 14.2 Bits 13.4 14.2 Bits −40°C to +85°C Noise Free Code Resolution2 14 Bits ISOLATION TRANSIENT IMMUNITY2 25 30 kV/µs LOGIC INPUTS CMOS with Schmitt trigger Input High Voltage (VIH) 0.8 × VDD2 V Input Low Voltage (VIL) 0.2 × VDD2 V Input Current (IIN) ±0.6 µA Input Capacitance (CIN) 10 pF LOGIC OUTPUTS Output High Voltage (VOH) VDD2 − 0.1 V IO = −200 µA Output Low Voltage (VOL) 0.4 V IO = +200 µA Rev. B | Page 3 of 24

Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD1 4.5 5.5 V VDD2 3 5.5 V IDD1 30 36 mA VDD1 = 5.5 V IDD2 12 18 mA VDD2 = 5.5 V 6 10 mA VDD2 = 3.3 V Power Dissipation 231 297 mW VDD1 = VDD2 = 5.5 V 185 231 mW VDD1 = 5.5 V, VDD2 = 3.3 V 1 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%. 2 See the Terminology section. 3 Not production tested. Sample tested during initial release to ensure compliance. AD7403-8 VDD1 = 4.5 V to 5.5 V , VDD2 = 3 V to 5.5 V , VIN+ = −250 mV to +250 mV , VIN− = 0 V, TA = −40°C to +105°C, fMCLKIN1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits Integral Nonlinearity (INL)2 ±2 ±6.5 LSB Differential Nonlinearity (DNL)2 ±0.99 LSB Guaranteed no missed codes to 16 bits Offset Error2 ±1 ±1.7 mV Offset Drift vs. Temperature3 2 6.8 µV/°C Offset Drift vs. VDD13 425 µV/V Gain Error2 ±0.2 ±0.8 % FSR fMCLKIN = 16 MHz ±0.2 ±1.4 % FSR fMCLKIN = 20 MHz Gain Error Drift vs. Temperature3 32 80 ppm/°C 20 51 µV/°C Gain Error Drift vs. VDD13 ±0.2 mV/V ANALOG INPUT Input Voltage Range −320 +320 mV Full-scale range −250 +250 mV For specified performance Input Common-Mode Voltage Range −200 to +300 mV Dynamic Input Current ±45 ±50 µA VIN+ = ±250 mV, VIN− = 0 V 0.05 µA VIN+ = 0 V, VIN− = 0 V DC Leakage Current ±0.01 ±0.6 µA Input Capacitance 14 pF DYNAMIC SPECIFICATIONS VIN+ = 1 kHz Signal-to-Noise-and-Distortion Ratio (SINAD)2 82 87 dB Signal-to-Noise Ratio (SNR)2 86 88 dB Total Harmonic Distortion (THD)2 −94 dB Peak Harmonic or Spurious Noise (SFDR)2 −94 dB Effective Number of Bits (ENOB)2 13.3 14.2 Bits ISOLATION TRANSIENT IMMUNITY2 25 30 kV/µs LOGIC INPUTS CMOS with Schmitt trigger Input High Voltage (VIH) 0.8 × VDD2 V Input Low Voltage (VIL) 0.2 × VDD2 V Input Current (IIN) ±0.6 µA Input Capacitance (CIN) 10 pF LOGIC OUTPUTS Output High Voltage (VOH) VDD2 − 0.1 V IO = −200 µA Output Low Voltage (VOL) 0.4 V IO = +200 µA Rev. B | Page 4 of 24

1 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%. 2 See the Terminology section. 3 Not production tested. Sample tested during initial release to ensure compliance. Sample tested during initial release to ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge.

20 MHz

VDD2 for VDD2 = 4.5 V to 5.5 V as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance. 1SEE NOTE 1 OF TABLE 3 FOR FURTHER DETAILS. Figure 2. Data Timing

Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 RI-O 1012 Ω Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 1 The device is considered a 2-terminal device. For AD7403, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. For AD7403-8, Pin 1 to Pin 4 are shorted together, Pin 5 to Pin 8 are shorted together. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 5. Parameter Symbol Value Unit Test Conditions/Comments Input to Output Momentary Withstand Voltage VISO 5000 min V 1 minute duration Minimum External Air Gap (Clearance) AD7403 L(I01) 8.3 min1, 2 mm Measured from input terminals to output terminals, shortest distance through air AD7403-8 L(I01) 8.1 min1, 2 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) AD7403 L(I02) 8.3 min1 mm Measured from input terminals to output terminals, shortest distance path along body AD7403-8 L(I02) 8.1 min1 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.034 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 13 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I)3 1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. 2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. 3 CSA CTI rating for the AD7403 is >600 V and a Material Group I isolation group. AD7403-8 is >400 and a Material Group II isolation group. REGULATORY INFORMATION Table 6. UL1 CSA VDE2 Recognized under 1577 Component Recognition Program Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122

5000 V rms Isolation Voltage

Basic insulation per CSA 60950-1-07 and IEC 60950-1, AD7403: 830 V rms (1173 VPEAK), AD7403-8: 810 Vrms (1145 VPEAK) maximum working voltage3 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 1250 VPEAK Reinforced insulation per CSA 60950-1-07 and IEC 60950-1. AD7403: 415 V rms (586 VPEAK), AD7403-8:

405 V rms (583 VPEAK) maximum working voltage3

Reinforced insulation per IEC 60601-1, 250 V rms (353 VPEAK) maximum working voltage File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each AD7403 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA). 2 In accordance with DIN V VDE V 0884-10, each AD7403 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC). 3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7403 RI-16-2 package material is rated by CSA to a CTI of >600 V and therefore Material Group I. The AD7403-8 RI-8-1 package material is rated by CSA to a CTI of >400 V and therefore Material Group II. Rev. B | Page 6 of 24

1 Transient currents of up to 100 mA do not cause SCR to latch up. 2 JESD22-C101; RC network: 1 Ω, Cpkg; Class: IV. 3 ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A. Table 9. Maximum Continuous Working Voltage

1 Refers to continuous voltage magnitude imposed across the isolation

Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −250 mV (V IN+ − VIN−), Code 7168 for the 16-bit level, and specified positive full scale, +250 mV (VIN+ − VIN−), Code 58,368 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (32,768 for the 16-bit level) from the ideal V IN+ − VIN− (that is, 0 V). Gain Error The gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58,368 for the 16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7168 for the 16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the offset error is adjusted out. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise Ratio = (6.02N + 1.76) dB Therefore, for a 12-bit converter, the SNR is 74 dB. Isolation Transient Immunity The isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. The AD7403 was tested using a transient pulse frequency of 100 kHz. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. It is defined as 65432 V VVVVVTHD 22222 log20(dB) ++++= where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Effective Number of Bits (ENOB) ENOB is defined by ENOB = (SINAD − 1.76)/6.02 bits Noise Free Code Resolution Noise free code resolution represents the resolution in bits for which there is no code flicker. The noise free code resolution for an N-bit converter is defined as Noise Free Code Resolution (Bits) = log 2(2N/Peak-to-Peak Noise) The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±250 mV frequency, f, to the power of a +250 mV peak-to-peak sine wave applied to the common-mode voltage of V IN+ and VIN− of frequency, fS, as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the specified full-scale (±250 mV) transition point due to a change in power supply voltage from the nominal value. Rev. B | Page 14 of 24

shunt resistor with a simple RC low-pass filter on each input. Figure 33. An RC low-pass filter is placed on both the analog source impedance on each analog input to minimize offset. Figure 33. RC Low-Pass Filter Input Network capacitor are 22 Ω and 47 pF, respectively. Figure 34. Differential RC Filter Network resistor and capacitor values. Figure 35. SNR vs. Decimation Rate for Different Filter Structures for Different Figure 36. SNR vs. Decimation Rate for Different Sincx Filter Orders a digital signal processor (DSP). Equation 1 describes the transfer function of a sinc filter. modulator clock and the decimation rate selected.

2 DR (3)

sinc filter are summarized in Table 13. Table 13. Sinc3 Filter Characteristics for 20 MHz MCLKIN configurable to accommodate decimation rates from 32 to 4096. Figure 37. Accumulator

1.27 BSC

1.93 REF

Figure 46. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Figure 47. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Model1 Temperature Range Package Description Package Option AD7403-8BRIZ −40°C to +105°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1 AD7403-8BRIZ-RL −40°C to +105°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1 AD7403-8BRIZ-RL7 −40°C to +105°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1 AD7403BRIZ −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2 AD7403BRIZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2 AD7403BRIZ-RL7 −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2 EVAL-AD7403-8FMCZ AD7403-8 Evaluation Board EVAL-AD7403FMCZ AD7403 Evaluation Board EVAL-SDP-CH1Z System Demonstration Platform 1 Z = RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12196-0-5/15(B) Rev. B | Page 24 of 24