AD7401YRWZ

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Isolated Sigma-Delta Modulator Data Sheet AD7401 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2006–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

20 MHz maximum external clock rate

±2 LSB INL typical at 16 bits 3.5 μV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 20 mA maximum at 5.25 V −40°C to +105°C operating range 16-lead SOIC package Safety and regulatory approvals UL recognition

5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V IORM = 891 V peak

APPLICATIONS

A/D + opto-isolator replacements GENERAL DESCRIPTION The AD74011 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full-scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sample- and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate up to 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial input/output can use a 5 V or a 3 V supply (V DD2). The serial interface is digitally isolated. High speed CMOS, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The device contains an on-chip reference. The AD7401 is offered in a 16-lead SOIC and has an operating temperature range of −40°C to +105°C. An internal clock version, AD7400, is also available. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. FUNCTIONAL BLOCK DIAGRAM VIN+ VDD1 VDD2 VIN– Σ-∆ ADC CONTROL LOGIC AD7401 BUF T/H REF WATCHDOG GND1 GND2 MDAT MCLKINDECODE ENCODE DECODE ENCODE UPDATE WATCHDOGUPDATE 05851-001 Figure 1.

Rev. F | Page 2 of 18 TABLE OF CONTENTS DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

REVISION HISTORY

4/2018—Rev. E to Rev. F 12/2015—Rev. D to Re v. E 7/2011—Rev. C to Rev. D Changes to Minimum External Air Gap (Clearance) Parameter, Table 3 and Minimum External Tracking (Creepage) Parameter, Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7 1/2011—Rev. B to Rev. C Changes to Input-to-Output Momentary Withstand Voltage 9/2007—Rev. A to Rev. B 12/2006—Rev. 0 to Rev. A 1/2006—Revision 0: Initial Version

Rev. F | Page 3 of 18 SPECIFICATIONS VDD1 = 4.5 V to 5.25 V , VDD2 = 3 V to 5.5 V , VIN+ = −200 mV to +200 mV , and VIN− = 0 V (single-ended); TA = TMIN to TMAX, fMCLK = 16 MHz maximum, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. Parameter Y Version1, 2 Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits min Filter output truncated to 16 bits Integral Nonlinearity3 ±15 LSB max −40°C to +85°C; ±2 LSB typical; fMCLK = 20 MHz maximum4 ±25 LSB max >85°C to 105°C ±55 LSB max fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Differential Nonlinearity3 ±0.9 LSB max Guaranteed no missed codes to 16 bits; fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Offset Error3 ±0.6 mV max fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV ±50 µV typ TA = 25°C Offset Drift vs. Temperature 3.5 µV/°C max −40°C to +105°C 1 µV/°C typ Offset Drift vs. VDD1 120 µV/V typ Gain Error3 ±1.6 mV max −40°C to +85°C ±2 mV max >85°C to 105°C ±1 mV typ fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C Gain Error Drift vs. VDD1 110 µV/V typ ANALOG INPUT Input Voltage Range ±200 mV min/mV max For specified performance; full range ±320 mV Dynamic Input Current ±9 µA max VIN+ = 400 mV, VIN− = 0 V DC Leakage Current ±0.5 µA max Input Capacitance 10 pF typ DYNAMIC SPECIFICATIONS VIN+ = 5 kHz, 400 mV p-p sine Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB min −40°C to +85°C; fMCLK = 9 MHz to 20 MHz4 68 dB min −40°C to +85°C; fMCLK = 5 MHz to <9 MHz 65 dB min >85°C to 105°C 65 dB min fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV 81 dB typ Signal-to-Noise Ratio (SNR) 80 dB min −40°C to +105°C; 82 dB typ 80 dB min fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Total Harmonic Distortion (THD)3 −92 dB typ fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Peak Harmonic or Spurious Noise (SFDR)3 −92 dB typ Effective Number of Bits (ENOB)3 11.5 Bits Isolation Transient Immunity3 25 kV/µs min 30 kV/µs typ LOGIC INPUTS Input High Voltage, VIH 0.8 × VDD2 V min Input Low Voltage, VIL 0.2 × VDD2 V max Input Current, IIN ±0.5 µA max Input Capacitance, CIN5 10 pF max

1 Temperature range is −40°C to +85°C. 2 All voltages are relative to their respective ground. 3 See the Terminology section. 5 Sample tested during initial release to ensure compliance.

5 MHz min Master clock input frequency

1 Sample tested during initial release to ensure compliance

2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2. Load Circuit for Digital Output Timing Specifications Figure 3. Data Timing

Rev. F | Page 5 of 18 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter Symbol Value Unit Conditions Input-to-Output Momentary Withstand Voltage VISO 5000 min V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.81,2 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.81,2 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I) 1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. 2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. REGULATORY INFORMATION Table 4. UL1 CSA VDE2 Recognized under 1577 Component Recognition Program1 Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122

5000 V rms Isolation Voltage Basic insulation per CSA 60950-1-07

and IEC 60950-1, 780 V rms maximum working voltage. Reinforced insulation per CSA 60950-1-03 and IEC 60950-1,

390 V rms maximum working

voltage. Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 891V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (current leakage detection limit = 15 µA). 2 In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥1671 V peak for 1 second (partial discharge detection limit = 5 pC).

means of protective circuits. Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

1 Transient currents of up to 100 mA do not cause SCR to latch-up. Table 7. Maximum Continuous Working Voltage

565 VPK 50-year minimum lifetime

891 VPK Maximum CSA/VDE

1 Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

Figure 5. Pin Configuration Table 8. Pin Function Descriptions 2 V IN+ Positive Analog Input. Specified range of ±200 mV. 3 V IN− Negative Analog Input. Normally connected to GND1. operate normally provided that the supply voltage is applied to Pin 1. 8 GND 1 Ground 1. This is the ground reference point for all circuitry on the isolated side. 9, 16 GND 2 Ground 2. This is the ground reference point for all circuitry on the nonisolated side. clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge. 13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN. 14 V DD2 Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND 2.

TA = 25°C, using a 25 kHz brick wall filter, unless otherwise noted. Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 7. SINAD vs. Analog Input Frequency

4096 POINT FFT

Figure 8. Typical FFT (±200 mV Range) Figure 9. SINAD vs. VIN Figure 10. Typical DNL (±200 mV Range) Figure 11. Typical INL (±200 mV Range)

Rev. F | Page 12 of 18 TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full-scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit level, and specified positive full-scale, +200 mV (VIN+ − VIN−), Code 53,248 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error Gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-(Noise + Distortion) Ratio This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD − 1.76)/6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7401, it is defined as 65432 V VVVVVTHD 22222 log20)dB( ++++= where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±200 mV frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of V IN+ and VIN− of frequency fS, expressed as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not converter linearity. PSRR is the maximum change in the specified full-scale (±200 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.)

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] registered trademarks are the prop erty of their respective owners.