AD7400

AD7400 (Rev.I)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 17

Technical content

Isolated Sigma-Delta Modulator Rev. I DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►10 MHz clock rate ►Second-order modulator ►16 bits no missing codes ►±2 LSB INL typical at 16 bits ►3.5 µV/°C maximum offset drift ►On-board digital isolator ►On-board reference ►Low power operation: 18 mA maximum at 5.25 V ►−40°C to +105°C operating range ►16-lead SOIC package ►Safety and regulatory approvals ►UL 1577 ►VISO = 5000 V rms for 1 minute ►IEC / CSA 62368-1 ►IEC / CSA 61010-1 ►DIN EN IEC 60747-17 (VDE 0884-17) ►VIORM = 645 V peak

APPLICATIONS

►AC motor controls ►Data acquisition systems ►A/D + opto-isolator replacements GENERAL DESCRIPTION The AD7400 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal to a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc. iCou- pler® technology. The AD7400 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sample-and-hold circui- try. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed CMOS, com- bined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. The part contains an on-chip reference. The AD7400 is offered in a 16-lead SOIC and has an operating temperature range of −40°C to +105°C. An external clock version, AD7401, is also available. FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

analog.com Rev. I | 2 of 17 DIN EN IEC 60747-17 (VDE 0884-17)

REVISION HISTORY

9/2024—Rev. H to Rev. I Changed DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Section to DIN EN IEC

analog.com Rev. I | 3 of 17 VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX, fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Temperature range is −40°C to +85°C. Table 1. Parameter Y Version1, 2 Unit Test Conditions/CommentsMin Typ Max STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits Integral Nonlinearity3 ±15 LSB −40°C to +85°C; ±2 LSB typical ±25 LSB >85°C to 105°C Differential Nonlinearity3 ±0.9 LSB Guaranteed no missing codes to 16 bits Offset Error3 ±0.5 mV ±50 µV TA = 25°C Offset Drift vs. Temperature 3.5 µV/°C −40°C to +105°C 1 µV/°C Offset Drift vs. VDD1 120 µV/V Gain Error3 ±1 mV Gain Error Drift vs. Temperature 23 µV/°C −40°C to +105°C Gain Error Drift vs. VDD1 110 µV/V ANALOG INPUT Input Voltage Range ±200 ±200 mV For specified performance; full range ±320 mV Dynamic Input Current ±8 µA VIN+ = 400 mV, VIN− = 0 V ±0.5 µA VIN+ = VIN− = 0 V Input Capacitance 10 pF DYNAMIC SPECIFICATIONS VIN+ = 35 Hz, 400 mV p-p sine Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB −40°C to +85°C 65 dB >85°C to 105°C 79 dB Signal-to-Noise Ratio (SNR) 71 dB −40°C to +105°C Total Harmonic Distortion (THD)3 −88 dB Peak Harmonic or Spurious Noise (SFDR)3 −88 dB Effective Number of Bits (ENOB)3 11.5 Bits Isolation Transient Immunity3 25 kV/µs 30 kV/µs LOGIC OUTPUTS Output High Voltage, VOH VDD2 − 0.1 V IO = −200 µA Output Low Voltage, VOL 0.4 V IO = +200 µA POWER REQUIREMENTS VDD1 4.5 5.25 V VDD2 3 5.5 V IDD14 13 mA VDD1 = 5.25 V IDD25 6 mA VDD2 = 5.5 V 4 mA VDD2 = 3.3 V 1 Temperature range is −40°C to +85°C. 2 All voltages are relative to their respective ground. 3 See the Terminology section. 4 See Figure 14. 5 See Figure 15.

The AD7400 certification approvals are listed in Table 4. Table 4. Regulatory Information 1 In accordance with UL 1577, each AD7400 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).

Table 5. (Continued) Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN IEC 60747-17 (VDE 0884-17)

analog.com Rev. I | 7 of 17 TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 6. Parameter Rating VDD1 to GND1 −0.3 V to +6.5 V VDD2 to GND2 −0.3 V to +6.5 V Analog Input Voltage to GND1 −0.3 V to VDD1 + 0.3 V Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 89.2°C/W θJC Thermal Impedance 55.6°C/W Resistance (Input-to-Output), RI-O 1012 Ω Capacitance (Input-to-Output), CI-O2 1.7 pF typ Pb-Free Temperature, Soldering Reflow 260 (+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR to latch-up. 2 f = 1 MHz. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devi- ces and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 5. Pin Configuration Table 7. Pin Function Descriptions 2 VIN+ Positive Analog Input. Specified range of ±200 mV. 3 VIN− Negative Analog Input. Normally connected to GND1. provided that the supply voltage is applied to Pin 1. 8 GND1 Ground 1. This is the ground reference point for all circuitry on the isolated side. 9, 16 GND2 Ground 2. This is the ground reference point for all circuitry on the nonisolated side. rising edge of the MCLKOUT output and valid on the following MCLKOUT rising edge. 13 MCLKOUT Main Clock Logic Output. 10 MHz typical. The bit stream from the modulator is valid on the rising edge of MCLKOUT. 14 VDD2 Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.

Figure 18. RMS Noise Voltage vs. VIN DC Input Figure 19. MCLKOUT vs. Temperature for Various Supplies

analog.com Rev. I | 12 of 17 Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit level, and specified positive full scale, +200 mV (VIN+ − VIN−), Code 53,248 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error Gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-(Noise + Distortion) Ratio (SINAD) This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the funda- mental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB (1) Therefore, for a 12-bit converter, this is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD − 1.76)/6.02 (2) Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7400, it is defined as THD d B = 20log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V 6 2 V 1 (3) where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±200 mV frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency fS, expressed as CMRR (dB) = 10log(Pf/PfS) (4) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not converter linearity. PSRR is the maximum change in the specified full-scale (±200 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.)

analog.com Rev. I | 16 of 17 GROUNDING AND LAYOUT Supply decoupling with a value of 100 nF is strongly recommended on both VDD1 and VDD2. Decoupling on one or both VDD1 pins does not significantly affect performance. In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Fur- thermore, the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure this may cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Any decoupling used should be placed as close to the supply pins as possible. Series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Beware of mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift. EVALUATING THE AD7400 PERFORMANCE A simple standalone AD7400 evaluation board is available with split ground planes and a board split beneath the AD7400 package to ensure isolation. This board allows access to each pin on the device for evaluation purposes. External supplies and all other circuitry (such as a digital filter) must be provided by the user.

©2006-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. I | 17 of 17 Package Drawing (Option) Package Type Package Description RW-16 SOIC_W 16-Lead Standard Small Outline Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7400YRWZ −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 AD7400YRWZ-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 AD7400YRWZ-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-AD7400EDZ Evaluation Board EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part.