AD7324

AD7324 (Rev. B)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC Data Sheet AD7324 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V

1 MSPS throughput rate

4 analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability High analog input impedance Low power: 21 mW Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 16-lead TSSOP package iCMOS™ process technology FUNCTIONAL BLOCK DIAGRAM VIN0 DOUT SCLK CS DIN VDRIVE VIN1 VIN2 VIN3 VDD REFIN/OUT VCC AGND VSS DGND CONTROL LOGIC AND REGISTERS 13-BIT SUCCESSIVE APPROXIMATION ADC T/H 2.5V VREF I/P MUX CHANNEL SEQUENCER AD7324 04864-001 Figure 1. GENERAL DESCRIPTION The AD73241 is a 4-channel, 12-bit plus sign, successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. The AD7324 can accept true bipolar analog input signals. The AD7324 has four software-selectable input ranges: ±10 V , ±5 V, ±2.5 V , and 0 V to +10 V . Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7324 can be programmed to be single-ended, true differential, or pseudo differential. The ADC contains a 2.5 V internal reference. The AD7324 also allows for external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7324 can accept a true bipolar ±12 V analog input. Minimum ±12 V V DD and VSS supplies are required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS. 1Protected by U.S. Patent No. 6,731,232. PRODUCT HIGHLIGHTS 1. The AD7324 can accept true bipolar analog input signals, ±10 V , ±5 V , ±2.5 V , and 0 V to +10 V unipolar signals. 2. The four analog inputs can be configured as four single- ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. 3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™- compatible interface. 4. Low power, 31 mW maximum, at 1 MSPS throughput rate. 5. Channel sequencer. Table 1. Similar Products Selection Table

Rev. B | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

12/13—Rev. A to Rev. B 1/10—Rev. 0 to Rev. A Added Power Supply Configuration Section, Figure 54, 12/05—Revision 0: Initial Version

Rev. B | Page 3 of 36 SPECIFICATIONS 3.0 V internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN; For VCC < 4.75 V, all specifications are typical. Table 2. B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE FIN = 50 kHz sine wave Signal-to-Noise Ratio (SNR)2 76 dB Differential mode 72.5 dB Single-ended/pseudo differential mode Signal-to-Noise + Distortion (SINAD)2 75 dB Differential mode; ±2.5 V and ±5 V ranges 76 dB Differential mode; 0 V to 10 V and ±10 V ranges 72 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 72.5 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges −82 dB Differential mode; 0 V to +10 V and ±10 V ranges −77 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges −80 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Peak Harmonic or Spurious Noise (SFDR)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges −82 dB Differential mode; 0 V to +10 V and ±10 V ranges −78 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges −79 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 30 kHz Second-Order Terms −88 dB Third-Order Terms −90 dB Aperture Delay3 7 ns Aperture Jitter3 50 ps Common-Mode Rejection Ratio (CMRR)2 −79 dB Up to 100 kHz ripple frequency; see Figure 17 Channel-to-Channel Isolation2 −72 dB FIN on unselected channels up to 100 kHz; see Figure 14 Full Power Bandwidth 22 MHz At 3 dB 5 MHz At 0.1 dB DC ACCURACY4 All dc accuracy specifications are typical for 0 V to 10 V mode. Single-ended/pseudo differential mode 1 LSB = FSR/4096, unless otherwise noted. Differential mode 1 LSB = FSR/8192, unless otherwise noted. Resolution 13 Bits No Missing Codes 12-bit plus sign (13 bits) Bits Differential mode 11-bit plus sign (12 bits) Bits Single-ended/pseudo differential mode Integral Nonlinearity2 ±1.1 LSB Differential mode ±1 LSB Single-ended/pseudo differential mode −0.7/+1.2 LSB Single-ended/pseudo differential mode (LSB = FSR/8192)

Rev. B | Page 4 of 36 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Differential Nonlinearity2 −0.9/+1.5 LSB Differential mode; guaranteed no missing codes to 13 bits ±0.9 LSB Single-ended mode; guaranteed no missing codes to 12 bits −0.7/+1 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Offset Error2, 5 −4/+9 LSB Single-ended/pseudo differential mode −7/+10 LSB Differential mode Offset Error Match2, 5 ±0.6 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Gain Error2, 5 ±8 LSB Single-ended/pseudo differential mode ±14 LSB Differential mode Gain Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Positive Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode ±7 LSB Differential mode Positive Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Bipolar Zero Error2, 6 ±8.5 LSB Single-ended/pseudo differential mode ±7.5 LSB Differential mode Bipolar Zero Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Negative Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode ±6 LSB Differential mode Negative Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range Register) ±10 V VDD = 10 V min, VSS = −10 V min, VCC = +2.7 V to +5.25 V ±5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V ±2.5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V 0 to 10 V VDD = +10 V min, VSS = AGND min, VCC = +2.7 V to +5.25 V Pseudo Differential VIN(−) Input Range VDD = +16.5 V, VSS = −16.5 V, VCC = +5 V; see Figure 40 and Figure 41 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±80 nA VIN = VDD or VSS 3 nA Per channel, VIN = VDD or VSS Input Capacitance3 13.5 pF When in track, ±10 V range 16.5 pF When in track, ±5 V and 0 V to +10 V ranges 21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 µA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error at 25°C ±5 mV

Rev. B | Page 5 of 36 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Reference Output Voltage TMIN to TMAX ±10 mV Reference Temperature Coefficient 25 ppm/°C 3 ppm/°C Reference Output Impedance 7 Ω LOGIC INPUTS Input High Voltage, VINH 2.4 V Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V 0.4 V VCC = 2.7 V to 3.6 V Input Current, IIN ±1 µA VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V V ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance3 5 pF Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz Track-and-Hold Acquisition Time2, 3 305 ns Full-scale step input; see the Terminology section Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE VDD 12 16.5 V See Table 6 VSS −12 −16.5 V See Table 6 VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V VDRIVE 2.7 5.25 V Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V Normal Mode (Operational) fSAMPLE = 1 MSPS IDD 360 µA VDD = 16.5 V ISS 410 µA VSS = −16.5 V ICC and IDRIVE 3.4 mA VCC/VDRIVE = 5.25 V Autostandby Mode (Dynamic) fSAMPLE = 250 kSPS IDD 200 µA VDD = 16.5 V ISS 210 µA VSS = −16.5 V ICC and IDRIVE 1.3 mA VCC/VDRIVE = 5.25 V Autoshutdown Mode (Static) SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V Full Shutdown Mode SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V

Rev. B | Page 6 of 36 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION Normal Mode (Operational) 31 mW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V 21 mW VDD = +12 V, VSS = −12 V, VCC = +5 V Full Shutdown Mode 38.25 µW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless otherwise noted. 5 Unipolar 0 V to 10 V range with straight binary output coding. 6 Bipolar range with twos complement output coding.

1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.

2 IDENTIFICATION BITS

Figure 2. Serial Interface Timing Diagram

Rev. B | Page 8 of 36 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter Rating VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to VCC VCC − 0.3 V to 16.5 V VCC to AGND, DGND −0.3 V to +7 V VDRIVE to AGND, DGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND1 VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin Except Supplies2 ±10 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 150.4°C/W θJC Thermal Impedance 27.6°C/W Pb-Free Temperature, Soldering Reflow 260(0)°C ESD 2.5 kV

1 If the analog inputs are being driven from alternative VDD and VSS supply

circuitry, Schottky diodes should be placed in series with the AD7324 VDD and VSS supplies. See Power Supply Configuration section. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. TSSOP Pin Configuration Table 5. Pin Function Description the AD7324 and frames the serial data transfer. register on the falling edge of SCLK (see the Reference section). condition (see the Reference section). 6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7, 8, 10, 9 VIN0 to VIN3 Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold. channel when a +2.5 V reference voltage is used (see the Reference section). 11 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 12 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7324. This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V. but it should not exceed VCC by more than 0.3 V. conversion data. The data is provided MSB first (see the Serial Interface section). AD7324. This clock is also used as the clock source for the conversion process.

4096 POINT FFT

Figure 4. FFT True Differential Mode Figure 5. FFT Single-Ended Mode Figure 6. Typical DNL True Differential Mode Figure 7. Typical INL True Differential Mode Figure 8. Typical DNL Single-Ended Mode Figure 9. Typical INL Single-Ended Mode

Figure 22. THD vs. Analog Input Frequency for Various

Rev. B | Page 14 of 36 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Offset Code Error This applies to straight binary output coding. It is the deviation ideal, that is, AGND + 1 LSB. Offset Error Match This is the difference in offset error between any two input channels. Gain Error This applies to straight binary output coding. It is the deviation ideal (that is, 4 × V REF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the offset error. Gain Error Match This is the difference in gain error between any two input channels. Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB. Bipolar Zero Code Error Match This refers to the difference in bipolar zero code error between any two input channels. Positive Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. It is the deviation of the last code transition (011 … 110) to (011 … 111) from the ideal (4 × V REF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the bipolar zero code error. Positive Full-Scale Error Match This is the difference in positive full-scale error between any two input channels. Negative Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. This is the deviation of the first code transition (10 … 000) to (10 … 001) from the ideal (that is, −4 × V REF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB) after adjusting for the bipolar zero code error. Negative Full-Scale Error Match This is the difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the 14th SCLK rising edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of a conversion. For the ±2.5 V range, the specified acquisition time is the time required for the track-and-hold amplifier to settle to within ±1 LSB. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digi- tization process. The more levels, the smaller the quantization noise. Theoretically, the signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB For a 13-bit converter, this is 80.02 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7324, it is defined as log20)dB( V VVVVVTHD ++++= where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak.

Rev. B | Page 15 of 36 Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worst- case across all eight channels for the AD7324. The analog input range is programmed to be the same on all channels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7324 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. PSR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section). CMRR (Common-Mode Rejection Ratio) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the V IN+ and VIN− frequency, fS, as CMRR (dB) = 10 log (Pf/PfS) where Pf is the power at frequency f in the ADC output, and PfS is the power at frequency fS in the ADC output (see Figure 17).

Figure 30. Equivalent Analog Input Circuit (Differential) exceed the VDD and VSS supply rails by more than 300 m V. causing irreversible damage to the part. analog input range selected (see the Specifications section). AD7324 can handle frequencies up to 22 MHz. any extra source impedance on the analog input. The AD7324 enters track mode on the 14th SCLK rising edge.

1.5 SCLK + t8 + tQUIET

hold mode on the CS falling edge. the specified THD performance is maintained. Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS, 750 kSPS, analog signal is sampled directly onto the sampling capacitor. current required to drive the analog input, therefore, decreases.

register select bits. If the write bit is 0, the data on the DIN line does not load into any register. for Analog Devices internal use only. Do not access these registers, as doing so may lead to unspecified operation of the device. Table 8. Decoding Register Select Bits and Write Bit 0 0 0 Data on the DIN line during this serial transfer is ignored. register have been initialized. The bit functions of the control register are shown in Table 9 (the power-up status of all bits is 0). Table 9. Control Register Details 12, 1 ZERO A 0 must be written to this bit to ensure correct operation of the device. select the final channel in a consecutive sequence. three pseudo differential inputs (see Table 10). 7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7324 (see Table 11). coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. bit during the last write to the control register. channel is the value written to the Ref bit during the last write to the control register. 3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).

differential input pairs, or four single-ended analog inputs. Table 10. Analog Input Configuration Selection Table 11. Power Mode Selection is retained when the AD7324 is in full shutdown mode. 1 0 Autoshutdown Mode. The AD7324 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. autostandby mode on the 15th SCLK rising edge after the control register is updated. 0 0 Normal Mode. All internal circuitry is powered up at all times. Table 12. Sequencer Selection control register, selects the next channel for conversion. in the control register. The range for each channel defaults to the range previously written into the range register. control register, selects the next channel for conversion. the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.

range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see Table 13). Table 13. Range Selection 0 0 This combination selects the ±10 V input range on VINx. 0 1 This combination selects the ±5 V input range on VINx. 1 0 This combination selects the ±2.5 V input range on VINx. 1 1 This combination selects the 0 V to +10 V input range on VINx.

Seq2 to 1. The ADC converts on the first channel in the sequence. THROUGH SEQUENCE OF CONSECUTIVE CHANNELS. RANGE SELECTED IN RANGE REGISTER. RANGE SELECTED IN RANGE REGISTER. AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE. SEQUENCE, Seq1 = 0, Seq2 = 0. Figure 45. Flowchart for Consecutive Sequence of Channels

Rev. B | Page 27 of 36 REFERENCE The AD7324 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, selecting the external reference for the AD7324 conversion. Suitable reference sources for the AD7324 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7324 in internal reference mode, the 2.5 V internal reference is available at the REFIN/OUT pin, which should be decoupled to AGND using a 680 nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 90 μA. On power-up, if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the Ref bit to 1. During the control register write, the conversion result from the first initial conversion is invalid. The reference buffer requires 500 µs to power up and charge the 680 nF decoupling capacitor during the power-up time. The AD7324 is specified for a 2.5 V to 3 V reference range. When a 3 V reference is selected, the ranges are ±12 V , ±6 V , ±3 V , and 0 V to +12 V . For these ranges, the V DD and VSS supply must be equal to or greater than the maximum analog input range selected, see Table 6. VDRIVE The AD7324 has a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7324 is operated with a VCC o f 5 V, t h e VDRIVE pin can be powered from a 3 V supply. This allows the AD7324 to accept large bipolar input signals with low voltage digital processing.

and from the AD7324 during a conversion. high, the addressed register may be updated.

3 MSBs on the DIN line are decoded to select which register is

identifier bit is clocked out on the first SCLK falling edge. Figure 51. Serial Interface Timing Diagram (Control Register Write)

planes that can easily be separated. to the ground pins on the AD7324. paths and reduce the effects of glitches on the power supply line. planes, and signals are placed on the other side. transient currents due to internal logic switching. Schottky diode configuration. BAT43 Schottky diodes are used. 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 54. Schottky Diode Connection recommended that these supplies be symmetrical. Table 16. Non-Symmetrical VDD and VSS Requirements

8 V −5 V to −15 V

minimum supply recommendations outlined in Table 6.

Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. B | Page 35 of 36 NOTES

Rev. B | Page 36 of 36 NOTES ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04864-0-12/13(B)