AD7322BRUZ-REEL7

AD7322 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 37

Technical content

2-Channel, Software-Selectable, True Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC Data Sheet AD7322 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V

1 MSPS throughput rate

Two analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability High analog input impedance Low power: 21 mW Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 14-lead TSSOP package iCMOS process technology FUNCTIONAL BLOCK DIAGRAM 04863-001 VIN0 DOUT SCLK CS DIN VDRIVE VIN1 VDD REFIN/OUT VCC AGND VSS DGND CONTROL LOGIC AND REGISTERS 13-BIT SUCCESSIVE APPROXIMATION ADC T/H 2.5V VREF I/P MUX CHANNEL SEQUENCER AD7322 Figure 1. GENERAL DESCRIPTION The AD73221 is a 2-channel, 12-bit plus sign, successive approx- imation analog-to-digital converter (ADC) designed on the iCMOS™ (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the develop- ment of a wide range of high performance analog ICs capable of

33 V operation in a footprint that no previous generation of high

voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. The AD7322 can accept true bipolar analog input signals. The AD7322 has four software-selectable input ranges, ±10 V, ± 5 V, ±2.5 V, and 0 V to +10 V . Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7322 can be programmed to be single-ended, true differential, or pseudo differential. The ADC contains a 2.5 V internal reference. The AD7322 also allows for external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7322 can accept a true bipolar ±12 V analog input. Minimum ±12 V VDD and VSS supplies are required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS. PRODUCT HIGHLIGHTS 1. The AD7322 can accept true bipolar analog input signals, ±10 V, ± 5 V, and ±2.5 V, and 0 V to +10 V unipolar signals. 2. The two analog inputs can be configured as two single- ended inputs, one true differential input, or one pseudo differential input. 3. 1 MSPS serial interface. SPI-/QSPI™-/DSP-/MICROWIRE™- compatible interface. 4. Low power, 31 mW maximum, at 1 MSPS throughput rate. 5. Channel sequencer. Table 1. Similar Devices 1 Protected by U.S. Patent No. 6,731,232.

AD7322* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD7322 Evaluation Board
• AD7328 Evaluation Board DOCUMENTATION Data Sheet
• AD7322: 2-Channel, Software-Selectable, True Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC Data Sheet SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7322 Evaluation Software REFERENCE MATERIALS Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD7322 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD7322 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

12/13—Rev. A to Rev. B 1/10—Rev. 0 to Rev. A Changes to Power Requirements, Normal Mode (Operational), ICC and IDRIVE Parameter; and Power Dissipation, Normal Mode Changes to Autostandby Mode (PM1 = 0, PM = 1) Section .... 28 12/05—Revision 0: Initial Version

Rev. B | Page 3 of 36 SPECIFICATIONS internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN; for VCC < 4.75 V, all specifications are typical. Table 2. B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave Signal-to-Noise Ratio (SNR)2 76 dB Differential mode 72.5 dB Single-ended/pseudo differential mode Signal-to-Noise + Distortion (SINAD)2 75 dB Differential mode; ±2.5 V and ±5 V ranges 76 dB Differential mode; 0 V to +10 V and ±10 V ranges 72 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 72.5 dB Single-ended/pseudo differential mode;

0 V to +10 V and ±10 V ranges

Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges −82 dB Differential mode; 0 V to +10 V and ±10 V ranges −77 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges −80 dB Single-ended/pseudo differential mode; Peak Harmonic or Spurious Noise (SFDR)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges −82 dB Differential mode; 0 V to +10 V and ±10 V ranges −78 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges −79 dB Single-ended/pseudo differential mode; Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 30 kHz Second-Order Terms −88 dB Third-Order Terms −90 dB Aperture Delay3 7 ns Aperture Jitter3 50 ps Common-Mode Rejection Ratio (CMRR)2 −79 dB Up to 100 kHz ripple frequency; see Figure 17 Channel-to-Channel Isolation2 −72 dB fIN on unselected channels up to 100 kHz; see Figure 14 Full Power Bandwidth 22 MHz At 3 dB 5 MHz At 0.1 dB DC ACCURACY All dc accuracy specifications are typical for 0 V to

10 V mode

Single-ended/pseudo differential mode:

1 LSB = FSR/4096; unless otherwise noted

Differential mode: 1 LSB = FSR/8192; unless otherwise noted Resolution 13 Bits No Missing Codes 12-bit plus sign (13 bits) Bits Differential mode 11-bit plus sign (12 bits) Bits Single-ended/pseudo differential mode Integral Nonlinearity2 ±1.1 LSB Differential mode ±1 LSB Single-ended/pseudo differential mode −0.7/+1.2 LSB Single-ended/pseudo differential mode (LSB = FSR/8192)

Rev. B | Page 4 of 36 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Differential Nonlinearity2 −0.9/+1.5 LSB Differential mode; guaranteed no missing codes to 13 bits ±0.9 LSB Single-ended mode; guaranteed no missing codes to 12 bits −0.7/+1 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Offset Error2, 4 −4/+9 LSB Single-ended/pseudo differential mode −7/+10 LSB Differential mode Offset Error Match2, 4 ±0.6 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Gain Error2, 4 ±8 LSB Single-ended/pseudo differential mode ±14 LSB Differential mode Gain Error Match2, 4 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Positive Full-Scale Error2, 5 ±4 LSB Single-ended/pseudo differential mode ±7 LSB Differential mode Positive Full-Scale Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Bipolar Zero Error2, 5 ±8.5 LSB Single-ended/pseudo differential mode ±7.5 LSB Differential mode Bipolar Zero Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Negative Full-Scale Error2, 5 ±4 LSB Single-ended/pseudo differential mode ±6 LSB Differential mode Negative Full-Scale Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range Register) ±10 V VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V ±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V ±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V 0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V Pseudo Differential VIN(−) Input Range VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and Figure 41 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±80 nA VIN = VDD or VSS 3 nA Per channel, VIN = VDD or VSS Input Capacitance3 13.5 pF When in track, ±10 V range 16.5 pF When in track, ±5 V and 0 V to +10 V range 21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 µA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error at 25°C ±5 mV Reference Output Voltage TMIN to TMAX ±10 mV Reference Temperature Coefficient 3 25 ppm/°C Reference Output Impedance 7 Ω

Rev. B | Page 5 of 36 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 2.4 V Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V 0.4 V VCC = 2.7 V to 3.6 V Input Current, IIN ±1 µA VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance3 5 pF Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz Track-and-Hold Acquisition Time2, 3 305 ns Full-scale step input; see the Terminology section Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE VDD 12 16.5 V See Table 6 VSS −12 −16.5 V See Table 6 VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V VDRIVE 2.7 5.25 V Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V Normal Mode (Operational) fS = 1 MSPS IDD 360 µA VDD = 16.5 V ISS 410 µA VSS = −16.5 V ICC and IDRIVE 3.4 mA VCC/VDRIVE = 5.25 V Autostandby Mode (Dynamic) fS = 250 kSPS IDD 200 µA VDD = 16.5 V ISS 210 µA VSS = −16.5 V ICC and IDRIVE 1.3 mA VCC/VDRIVE = 5.25 V Autoshutdown Mode (Static) SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V Full Shutdown Mode SCLK on or off IDD 1 µA VDD = 16.5 V ISS 1 µA VSS = −16.5 V ICC and IDRIVE 1 µA VCC/VDRIVE = 5.25 V POWER DISSIPATION Normal Mode 31 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V Full Shutdown Mode 38.25 µW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Unipolar 0 V to 10 V range with straight binary output coding. 5 Bipolar range with twos complement output coding.

1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio must be limited to 50:50. Figure 2. Serial Interface Timing Diagram

Rev. B | Page 7 of 36 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 4. Parameter Rating VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to VCC VCC − 0.3 V to 16.5 V VCC to AGND, DGND −0.3 V to +7 V VDRIVE to AGND, DGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND1 VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin Except Supplies2 ±10 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 113.5°C/W θJC Thermal Impedance 30°C/W Pb-Free Temperature, Soldering Reflow 260(0)°C ESD 2.5 kV

1 If the analog inputs are driven from alternative VDD and VSS supply circuitry,

Schottky diodes should be placed in series with the AD7322’s VDD and VSS supplies. See the Power Supply Configuration section. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. Pin Configuration Table 5. Pin Function Descriptions the AD7322 and framing the serial data transfer. register on the falling edge of SCLK (see the Registers section). mode is the default condition. 6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7, 8 VIN0, VIN1 Analog Input 0 and Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold. on each analog input channel when a +2.5 V reference voltage is used (see the Registers section). 9 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 10 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7322. This supply should be decoupled to AGND. VCC, but it should not exceed VCC by more than 0.3 V. conversion data. The data is provided MSB first (see the Serial Interface section). AD7322. This clock is also used as the clock source for the conversion process.

4096 POINT FFT

Figure 4. FFT True Differential Mode Figure 5. FFT Single-Ended Mode Figure 6. Typical DNL True Differential Mode Figure 7. Typical INL True Differential Mode Figure 8. Typical DNL Single-Ended Mode Figure 9. Typical INL Single-Ended Mode

Figure 22. THD vs. Analog Input Frequency for Various

Rev. B | Page 13 of 36 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Offset Code Error This applies to straight binary output coding. It is the deviation of the first code transition (00…000) to (00…001) from the ideal, that is, AGND + 1 LSB. Offset Error Match This is the difference in offset error between any two input channels. Gain Error This applies to straight binary output coding. It is the deviation of the last code transition (111…110) to (111…111) from the ideal (that is, 4 × V REF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the offset error. Gain Error Match This is the difference in gain error between any two input channels. Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transi- tion (all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB. Bipolar Zero Code Error Match This refers to the difference in bipolar zero code error between any two input channels. Positive Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. It is the deviation of the last code transition (011…110) to (011…111) from the ideal (4 × V REF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjust- ing for the bipolar zero code error. Positive Full-Scale Error Match This is the difference in positive full-scale error between any two input channels. Negative Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. This is the deviation of the first code transition (10…000) to (10…001) from the ideal (that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB) after adjusting for the bipolar zero code error. Negative Full-Scale Error Match This is the difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the 14th SCLK rising edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of a conversion. For the ±2.5 V range, the specified acquisition time is the time required for the track-and-hold amplifier to settle to within ±1 LSB. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digi- tization process. The more levels there are, the smaller the quantization noise becomes. Theoretically, the signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB For a 13-bit converter, this is 80.02 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7322, it is defined as log20)dB( V VVVVVTHD ++++= where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic can be a noise peak.

Rev. B | Page 14 of 36 Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worst- case across all eight channels for the AD7322. The analog input range is programmed to be the same on all channels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7322 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. PSR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section). CMRR (Common-Mode Rejection Ratio) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the V IN+ and VIN− frequency, fS, as CMRR (dB) = 10 log (Pf/PfS) where Pf is the power at frequency f in the ADC output, and PfS is the power at frequency fS in the ADC output (see Figure 17).

1. VIN+ REFERS TO VIN0 AND VIN– REFERS TO VIN1.

Figure 30. Equivalent Analog Input Circuit (Differential) exceed the VDD and VSS supply rails by more than 300 m V. causing irreversible damage to the part. analog input range selected (see the Specifications section). AD7322 can handle frequencies up to 22 MHz. by the track-and-hold amplifier looking back on the input. any extra source impedance on the analog input. The AD7322 enters track mode on the 14th SCLK rising edge.

1.5 SCLK + t8 + tQUIET

hold mode on the CS falling edge. supplies, the specified THD performance is maintained. Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS analog signal is sampled directly onto the sampling capacitor. current required to drive the analog input therefore decreases.

MSBs consist of the write bit, zero bit, and register select bit. is 0, the data on the DIN line does not load into any register. The zero bit must always be set to 0. as doing so may lead to unspecified operation of the device. Table 8. Decoding Register Select Bit and Write Bit 0 0 X Data on the DIN line during this serial transfer is ignored. Register contents remain unchanged. 1 0 0 This combination selects the control register. The subsequent 12 bits are loaded into the control register. 1 0 1 This combination selects the range register. The subsequent six bits are loaded into the range register.

analog input configuration, reference, coding, and power mode. power-up status of all bits is 0). single-ended analog inputs (see Table 10). Table 9. Control Register Details 12, 11, 1 Zero These bits should contain 0 during each write to the control register. final channel in the consecutive sequence (see Table 10). These two mode bits are used to select the configuration of the two analog input pins, VIN0 and VIN1. configured as single-ended inputs, true differential inputs, or pseudo differential inputs (see Table 10). 7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7322 (see Table 11). coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. bit during the last write to the control register. channel is the value written to the Ref bit during the last write to the control register. 3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12). Table 10. Analog Input Configuration Selection

0 Not allowed VIN0 VIN1 VIN0 VIN1 VIN0 AGND

1 Not allowed VIN0 VIN1 VIN0 VIN1 VIN1 AGND

Table 11. Power Mode Selection is retained when the AD7322 is in full shutdown mode. 1 0 Autoshutdown mode. The AD7322 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. enters autostandby mode on the 15th SCLK rising edge after the control register is updated. 0 0 Normal mode. All internal circuitry is powered up at all times. Table 12. Sequencer Selection selects the next channel for conversion. bits in the control register. The range for each channel defaults to the ranges previously written into the range register. selects the next channel for conversion.

is selected by default on each analog input channel (see Table 13). Table 13. Range Selection 0 0 This combination selects the ±10 V input range on VINx. 0 1 This combination selects the ±5 V input range on VINx. 1 0 This combination selects the ±2.5 V input range on VINx. 1 1 This combination selects the 0 V to +10 V input range on VINx.

register selects the next channel for conversion. FOR THE ANALOG INPUT CHANNELS. THROUGH SEQUENCE OF CONSECUTIVE CHANNELS. AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE. SEQUENCE, Seq1 = 0, Seq2 = 0. Figure 44. Flowchart for Consecutive Sequence of Channels

Rev. B | Page 26 of 36 REFERENCE The AD7322 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, resulting in the selection of the external reference for the AD7322 conversion. Suitable reference sources for the AD7322 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7322 in internal reference mode, the 2.5 V internal reference is available at the REFIN/OUT pin, which should be decoupled to AGND using a 680 nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 90 μA. On power-up, if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the Ref bit to 1. During the control register write, the conversion result from the first initial conversion is invalid. The reference buffer requires 500 µs to power up and charge the 680 nF decoupling capacitor during the power-up time. The AD7322 is specified for a 2.5 V to 3 V reference range. When a 3 V reference is selected, the ranges are ±12 V , ±6 V , ±3 V , and 0 V to +12 V . For these ranges, the V DD and VSS supply must be equal to or greater than the maximum analog input range selected (see Table 6). VDRIVE The AD7322 has a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7322 is operated with a V CC o f 5 V, t h e VDRIVE pin can be powered from a 3 V supply. This allows the AD7322 to accept large bipolar input signals with low voltage digital processing.

ground planes that can easily be separated. to the ground pins on the AD7322. paths and reduce the effects of glitches on the power supply line. shielded with digital ground and never run near the analog inputs. planes, and signals are placed on the other side. transient currents due to internal logic switching. Schottky diode configuration. BAT43 Schottky diodes are used. 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 53. Schottky Diode Connection recommended that these supplies be symmetrical. minimum supply recommendations outlined in Table 6. Table 16. Nonsymmetrical VDD and VSS Requirements

8 V −5 V to −15 V

0.65 BSC

Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. B | Page 34 of 36 NOTES

Rev. B | Page 35 of 36 NOTES

Rev. B | Page 36 of 36 NOTES ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04863-0-12/13(B)