AD7305BRUZ AD | Alldatasheet

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3 V/5 V, Rail-to-Rail

Quad, 8-Bit DAC AD7304/AD7305 Rev. C Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Four 8-bit DACs in one package +3 V, +5 V, and ±5 V operation Rail-to-rail REF input to voltage output swing

2.6 MHz reference multiplying bandwidth

SPI serial interface-compatible—AD7304 Fast parallel interface—AD7305 40 µA power shutdown

APPLICATIONS

Automotive output span voltage Instrumentation, digitally controlled calibration Pin-compatible AD7226 replacement when VDD < 5.5 V GENERAL DESCRIPTION The AD7304/AD73051 are quad, 8-bit DACs that operate from a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has a serial interface, while the AD7305 has a parallel interface. Internal precision buffers swing rail-to-rail. The reference input range includes both supply rails, allowing for positive or negative full-scale output voltages. Operation is guaranteed over the supply voltage range of 2.7 V to 5.5 V, consuming less than 9 mW from a 3 V supply. The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail VREF input to DAC VOUT allows for a full-scale voltage set equal to the positive supply, VDD, the negative supply, VSS, or any value in between. The AD7304’s doubled-buffered serial data interface offers high speed, 3-wire, SPI®-, and microcontroller-compatible inputs using data in (SDI), clock (CLK), and chip select (CS) pins. Additionally, an internal power-on reset sets the output to zero scale. The parallel input AD7305 uses a standard address decode along with the WR control line to load data into the input registers. The double-buffered architecture allows all four input registers to be preloaded with new values, followed by an LDAC control strobe that copies all the new data into the DAC registers, thereby updating the analog output values. 1 Protected under Patent No. 5684481. FUNCTIONAL BLOCK DIAGRAMS CS PWR-ON RESET VSS AD7304 VOUTAINPUT REG A DAC A LDAC SDI/SHDN GND CLK 8 8 8 8 DAC A REG DAC B 8 8 8 8 DAC D DAC CSERIAL REG VREFB VREFA CLR VREFCV REFD VDD VOUTB VOUTC VOUTD INPUT REG B DAC B REG INPUT REG C DAC C REG INPUT REG D DAC D REG 01114-001 Figure 1. PWR-ON RESET AD7305 VOUTAINPUT REG A DAC A LDAC 8 8 8 8 DAC A REG DAC B 8 8 8 8 DAC D DAC C DECODE VREF VSS GND VDD VOUTB VOUTC VOUTD INPUT REG B DAC B REG INPUT REG C DAC C REG INPUT REG D DAC D REG 01114-002 DB0 DB1 DB2 DB3 DB4 DB5 DB6 8 WR A0/SHDN Figure 2. When operating from less than 5.5 V, the AD7305 is pin-compatible with the popular industry-standard AD7226. An internal power-on reset places both parts in the zero-scale state at turn-on. A 40 µA power shutdown (SHDN) feature is activated on both parts by three-stating the SDI/SHDN pin on the AD7304 and three-stating the A0/SHDN address pin on the AD7305. The AD7304/AD7305 are specified over the extended industrial −40°C to +85°C and the automotive −40°C to +125°C temperature ranges. AD7304s are available in a wide-body 16-lead SOIC (R-16) package. The parallel input AD7305 is available in the wide-body 20-lead SOIC (R-20) surface-mount package. For ultracompact applications, the thin 1.1 mm, 16-lead TSSOP (RU-16) package is available for the AD7304, while the 20-lead TSSOP (RU-20) houses the AD7305.

Rev. C | Page 2 of 20 TABLE OF CONTENTS

Revision History

11/04—Data Sheet Changed from Rev. B to Rev. C 2/04—Data Sheet Changed from Rev. A to Rev. B 3/98—Changed from Rev. 0 to Rev. A 2/98—Revision 0: Initial Version

Rev. C | Page 3 of 20 SPECIFICATIONS @ VDD = 3 V or 5 V , VSS = 0 V; or VDD = +5 V and VSS = –5 V , VSS ≤ VREF ≤ VDD, −40°C < TA < +85°C/+125°C, unless otherwise noted. Table 1. Parameter Symbol Condition 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit STATIC PERFORMANCE Resolution1 N 8 8 8 Bits Integral Nonlinearity2 INL ±1 ±1 ±1 LSB max Differential Nonlinearity DNL Monotonic, all codes 0 to 0xFF ±1 ±1 ±1 LSB max Zero-Scale Error VZSE Data = 0x00 15 15 ±15 mV max Full-Scale Voltage Error VFSE Data = 0xFF ±4 ±4 ±4 LSB max Full-Scale Temperature Coefficient3 TCVFS 5 5 5 ppm/°C typ4 REFERENCE INPUT VREFIN Range VREFIN VSS/VDD VSS/VDD VSS/VDD V min/max Input Resistance (AD7304) RREFIN Code = 0x55 28 28 28 kΩ typ Input Resistance (AD7305) RREFIN All DACs at code = 0x55 7.5 7.5 7.5 kΩ typ Input Capacitance3 CREFIN 5 5 5 pF typ ANALOG OUTPUTS Output Voltage Range VOUT VSS/VDD VSS/VDD VSS/VDD V min/max Output Current Drive IOUT Code = 0x80, ∆VOUT < 1 LSB ±3 ±3 ±3 mA typ Shutdown Resistance ROUT DAC outputs placed in shutdown state 120 120 120 kΩ typ Capacitive Load3 CL No oscillation 200 200 200 pF typ LOGIC INPUTS Logic Input Low Voltage VIL 0.6 0.8 0.8 V min Logic Input High Voltage VIH 2.1 2.4 2.4 V max Input Leakage Current5 IIL ±10 ±10 ±10 µA max Input Capacitance3 CIL 8 8 8 pF max AC CHARACTERISTICS3 Output Slew Rate SR Code = 0x00 to 0xFF to 0x00 1/2.7 1/3.6 1.0/3.6 V/µs min/typ Reference Multiplying BW Small signal, VSS = –5 V 2.6 MHz typ Total Harmonic Distortion THD VREF = 4 V p-p, VSS = –5 V, f = 1 kHz 0.025 % Settling Time6 tS To ±0.1% of full scale 1.1/2 1.0/2 1.0/2 µs typ/max Shutdown Recovery Time tSDR To ±0.1% of full scale 2 2 2 µs max Time to Shutdown tSDN 15 15 15 µs typ DAC Glitch Q 15 15 15 nVs typ Digital Feedthrough Q 2 2 2 nVs typ Feedthrough VOUT/VREF Code = 0x00, VREF = 1 V p-p, f = 100 kHz −65 dB SUPPLY CHARACTERISTICS Positive Supply Current IDD VLOGIC = 0 V or VDD, no load 6 6 6 mA max Negative Supply Current ISS VSS = –5 V 6 mA max Power Dissipation PDISS VLOGIC = 0 V or VDD, no load 15 30 60 mW max Power Down IDD_SD SDI/SHDN = floating 40 40 40 µA typ Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/% 1 One LSB = VREF/256. 2 The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typical specifications represent average readings measured at 25°C. 5 The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current. 6 The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.

Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz @ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted. 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Rev. C | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VDD to GND −0.3 V, +8 V VSS to GND +0.3 V, −8 V VREFX to GND VSS, VDD Logic Inputs to GND −0.3 V, VDD + 0.3 V VOUTX to GND −0.3 V, VDD + 0.3 V IOUT Short-Circuit to GND 50 mA Package Power Dissipation (TJ MAX – TA)/θJA Thermal Resistance θJA 16-Lead SOIC Package (R-16) 73°C/W 16-Lead TSSOP Package (RU-16) 180°C/W 20-Lead SOIC Package (R-20) 74°C/W 20-Lead TSSOP Package (RU-20) 155°C/W Maximum Junction Temperature (TJ MAX) 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C R-16, R-20, RU-16, RU-20 (Infrared, 15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 8. AD7304 Pin Configuration Table 7. AD7304 Pin Function Descriptions 1 VOUTB Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is open circuit when SHDN is enabled. 2 VOUTA Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is open circuit when SHDN is enabled. 3 VSS Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V. 4 VREFA Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation is VSS < VREFA < VDD. 5 VREFB Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation is VSS < VREFB < VDD. 6 GND Common Analog and Digital Ground. the decoded input register when CS returns high. Does not effect LDAC operation. 10 CLK Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS. 12 VREFD Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation is VSS < VREFD < VDD. 13 VREFC Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation is VSS VREFC < VDD. 14 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V. 15 VOUTD Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is open circuit when SHDN is enabled. 16 VOUTC Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is open circuit when SHDN is enabled.

Figure 9. AD7305 Pin Configuration Table 8. AD7305 Pin Function Description open circuit when SHDN is enabled. open circuit when SHDN is enabled. 3 VSS Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V. 4 VREF Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation is VSS < VREF < VDD. 5 GND Common Analog and Digital Ground. 7 DB7 MSB Digital Input Data Bit. 14 DB0 LSB Digital Input Data Bit. 15 WR Write Data into Input Register Control Line, Active Low. See Table 6 for operation. Driver. Does not effect DAC register contents as long as power is present on VDD. 18 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V. open circuit when SHDN is enabled. open circuit when SHDN is enabled.

Rev. C | Page 17 of 20 The AD7304/AD7305 are inherently 2-quadrant multiplying DACs. That is, they can easily be set up for unipolar output operation. The full-scale output polarity is the same as the reference input voltage polarity. In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished using an external true rail-to-rail op amp, such as the OP295. Connecting the external amplifier with two equal value resistors, as shown in Figure 38, results in a full 4-quadrant multiplying circuit. In this circuit, the amplifier provides a gain of two, which increases the output span magnitude to 10 V. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = –5 V) to midscale (VOUT = 0 V) to full scale (VOUT = +5 V). REFOUT VDV ×−= 1128 (2) +5V 10kΩ 10kΩ AD7304 REF –5V < VOUT < +5V 01114-038 2.2pF Figure 38. 4-Quadrant Multiplying Application Circuit

Figure 39. 16-Lead Standard Small Outline Package [SOIC] Figure 40. 20-Lead Standard Small Outline Package [SOIC] Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

6.40 BSC

Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. C | Page 19 of 20 ORDERING GUIDE Model Temperature Range Package Description Package Options AD7304BR –40°C to +85°C 16-Lead SOIC R-16 AD7304BR-REEL –40°C to +85°C 16-Lead SOIC R-16 AD7304BRZ1 –40°C to +85°C 16-Lead SOIC R-16 AD7304BRZ-REEL1 –40°C to +85°C 16-Lead SOIC R-16 AD7304YR –40°C to +125°C 16-Lead SOIC R-16 AD7304YRZ1 –40°C to +125°C 16-Lead SOIC R-16 AD7304BRU –40°C to +85°C 16-Lead TSSOP RU-16 AD7304BRU-REEL7 –40°C to +85°C 16-Lead TSSOP RU-16 AD7305BR –40°C to +85°C 20-Lead SOIC R-20 AD7305BR-REEL –40°C to +85°C 20-Lead SOIC R-20 AD7305YR –40°C to +125°C 20-Lead SOIC R-20 AD7305YR-REEL –40°C to +125°C 20-Lead SOIC R-20 AD7305BRU –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRU-REEL7 –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRUZ1 –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRUZ-REEL71 –40°C to +85°C 20-Lead TSSOP RU-20 1 Z = Pb-free part.

Rev. C | Page 20 of 20 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the proper ty of their respectiv e companies. Printed in the U.S.A. C01114-0-11/04(C)