AD7303

AD7303 +2.7V to +5.5V, Serial Input, Dual Voltage Output 8-Bit DAC

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Technical content

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC AD7303 FUNCTIONAL BLOCK DIAGRAM I DAC A POWER ON RESETDIN SYNC SCLK REF VDD AD7303 VOUT A VOUT B GND I/VINPUT REGISTER MUX DAC REGISTER I/VINPUT REGISTER DAC REGISTER 16-BIT SHIFT REGISTER DATA (8) CONTROL (8) I DAC B

FEATURES

Two 8-Bit DACs in One Package 8-Pin DIP/SOIC and microSOIC Packages +2.7 V to +5.5 V Operation Internal & External Reference Capability Individual DAC Power-Down Function Three-Wire Serial Interface QSPI™, SPI™ and Microwire™ Compatible On-Chip Output Buffer Rail-to-Rail Operation On-Chip Control Register Low Power Operation: 2.3 mA @ 3.3 V Full Power-Down to 1 mA max, typically 80 nA

APPLICATIONS

Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators PRODUCT HIGHLIGHTS 1. Low power, single supply operation. This part operates from a single +2.7 V to +5.5 V supply and consumes typically 15 mW at 5.5 V, making it ideal for battery powered applications. 2. The on-chip output buffer amplifiers allow the outputs of the DACs to swing rail to rail with a settling time of typically 1.2µs. 3. Internal or external reference capability. 4. High speed serial interface with clock rates up to 30 MHz. 5. Individual power-down of each DAC provided. When com- pletely powered down, the DAC consumes typically 80 nA. GENERAL DESCRIPTION The AD7303 is a dual, 8-bit voltage out DAC that operates from a single +2.7 V to +5.5 V supply. Its on-chip precision out- put buffers allow the DAC outputs to swing rail to rail. This de- vice uses a versatile 3-wire serial interface that operates at c lock rates up to 30 MHz, and is compatible with QSPI, SPI, microwire and digital signal processor interface standards. The serial input register is sixteen bits wide; 8 bits act as data bits for the DACs, and the remaining eight bits make up a control register. The on-chip control register is used to address the relevant DAC, to power down the complete device or an individual DAC, to select internal or external reference and to provide a synchronous loading facility for simultaneous update of the DAC outputs with a software LDAC function. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consump- tion is 7.5 mW max at 3 V, reducing to less than 3 µW in full power-down mode. The AD7303 is available in an 8-pin plastic dual in-line pack- age, 8-lead SOIC and microSOIC packages. QSPI and SPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997

REV. 0–2– AD7303–SPECIFICATIONS (VDD = +2.7 V to +5.5 V, Internal Reference; R L = 10 kV to VDD and GND; CL = 100 pF to GND; all specifications T MIN to TMAX unless otherwise noted) Parameter B Versions 1 Units Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy ± 1 LSB max Note 2 Differential Nonlinearity ± 1 LSB max Guaranteed Monotonic Zero-Code Error @ +25 °C 3 LSB max All Zeros Loaded to DAC Register Full-Scale Error –0.5 LSB typ All Ones Loaded to DAC Register Gain Error3 +1 % FSR typ Zero-Code Temperature Coefficient 100 µV/°C typ DAC REFERENCE INPUT REFIN Input Range 1 to V DD/2 V min to max REFIN Input Impedance 10 ΜΩ typ Internal Voltage Reference Error 4 ± 1 % max OUTPUT CHARACTERISTICS Output Voltage Range 0 to V DD V min to max Output Voltage Settling Time 2 µs max Typically 1.2 µs Slew Rate 7.5 V/ µs typ Digital to Analog Glitch Impulse 0.5 nV-s typ 1 LSB Change Around Major Carry Digital Feedthrough 0.2 nV-s typ Digital Crosstalk 0.2 nV-s typ Analog Crosstalk ± 0.2 LSB typ DC Output Impedance 40 Ω typ Short Circuit Current 14 mA typ Power Supply Rejection Ratio 0.0001 %/% max Δ VDD = ± 10% LOGIC INPUTS Input Current ± 10 µA max VINL, Input Low Voltage 0.8 V max V DD = +5 V

0.6 V max V DD = +3 V

VINH, Input High Voltage 2.4 V min V DD = +5 V

2.1 V min V DD = +3 V

VDD 2.7/5.5 V min/max IDD (Normal Mode) Both DACs Active and Excluding Load Currents, VDD = 3.3 V V IH = VDD, VIL = GND @ +25°C 2.1 mA max See Figure 8 TMIN – TMAX 2.3 mA max VDD = 5.5 V @ +25°C 2.7 mA max TMIN – TMAX 3.5 mA max IDD (Full Power-Down) @ +25°C 80 nA typ V IH = VDD, VIL = GND TMIN – TMAX 1 µA max See Figure 19 NOTES 1Temperature ranges are as follows: B Version, –40 °C to +105 °C. 2Relative Accuracy is calculated using a reduced digital code range of 15 to 245. 3Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4Internal Voltage Reference Error = (Actual V REF – Ideal VREF/Ideal VREF) • 100. Ideal VREF = VDD/2, actual V REF = voltage on reference pin when internal reference is selected. Specifications subject to change without notice. ORDERING GUIDE Temperature Package Model Range Options* AD7303BN –40 °C to +105°C N-8 AD7303BR –40 °C to +105°C SO-8 AD7303BRM –40 °C to +105°C RM-8 *N = Plastic DIP; R = SOIC; RM = microSOIC.

–4– REV. 0 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Operating Temperature Range WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7303 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS (DIP, SOIC and microSOIC) TOP VIEW (Not to Scale) AD7303 VOUT A SCLK DIN SYNC VOUT B VDD GND REF PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V OUT A Analog Output Voltage from DAC A. The output amplifier swings rail to rail on its output. 2V DD Power Supply Input. These parts can be operated from +2.7 V to +5.5 V and should be decoupled to GND. 3 GND Ground reference point for all circuitry on the part. 4 REF External Reference Input. This can be used as the reference for both DACs, and is selected by setting the INT/EXT bit in the control register to a logic one. The range on this reference input is 1 V to V DD/2. When the internal reference is selected, this voltage will appear as an output for decoupling purposes at the REF Pin. When using the internal reference, external voltages should not be connected to the REF Pin, see Figure 21. 5 SCLK Serial Clock. Logic Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 DIN Serial Data Input. This device has a 16-bit shift register, 8 bits for data and 8 bits for control. Data is clocked into the register on the rising edge of the clock input. 7 SYNC Level Triggered Control Input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the rising edges of the following clocks. The rising edge of the SYNC causes the relevant registers to be updated. 8V OUT B Analog output voltage from DAC B. The output amplifier swings rail to rail on its output. Lead Temperature, Soldering Lead Temperature, Soldering *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

–5–REV. 0 TERMINOLOGY INTEGRAL NONLINEARITY For the DACs, relative accuracy or endpoint nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer func- tion. A graphical representation of the transfer curve is shown in Figure 15. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change of any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. ZERO CODE ERROR Zero code error is the measured output voltage from V OUT of either DAC when zero code (all zeros) is loaded to the DAC latch. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-scale error is expressed in LSBs. GAIN ERROR This is a measure of the span error of the DAC. It is the devia- tion in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale value. Gain error is calcu- lated between Codes 15 and 245. FULL-SCALE ERROR Full-Scale Error is a measure of the output error when the DAC latch is loaded with FF Hex. Full-scale error includes the offset error. DIGITAL-TO-ANALOG GLITCH IMPULSE Digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the software LDAC used to update the DAC. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. DIGITAL FEEDTHROUGH Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same DAC, but is measured when the DAC is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. DIGITAL CROSSTALK Digital crosstalk is the glitch impulse transferred to the output of one converter due to a digital code change to another DAC. It is specified in nV-s. ANALOG CROSSTALK Analog crosstalk is a change in output of any DAC in response to a change in the output of the other DAC. It is measured in LSBs. POWER SUPPLY REJECTION RATIO (PSRR) This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of % change in output per % of change in V DD for full-scale output of the DAC. V DD is varied ± 10%. This specification applies to an external reference only because the output voltage will track the V DD voltage when in- ternal reference is selected.

Figure 3. Output Sink Current Capa- Figure 6. Relative Accuracy vs. Figure 9. Large Scale Signal Figure 4. Output Source Current

2.5 LOGIC INPUTS = VDD OR GND

Figure 7. Supply Current vs. Figure 10. Full-Scale Settling Time Figure 5. Output Source Current Figure 8. Supply Current vs. Figure 11. Exiting Power-Down (Full

2 VOUT B

Figure 12. Exiting Power-Down Figure 15. Integral Linearity Plot Figure 13. Supply Current vs. Figure 16. Typical INL vs.

10 LSB STEP CHANGE

Figure 14. Small Scale Settling Figure 17. Typical DNL vs. Figure 19. Power-Down Current vs. Figure 18. Typical Internal Reference

which allows their outputs to be simultaneously updated. shift register is given below. and can be transmitted in one 16-bit write or two 8-bit writes.

308 TO 32

8 DAC

Figure 23. Logic Interface on the AD7303

DB15 INT/EXT Selects between internal and external reference. DB13 LDAC Load DAC bit for synchronous update of DAC outputs. A/B Address bit to select either DAC A or DAC B. DB9 CR1 Control Bit 1 used in conjunction with CR0 to implement the various data loading functions. DB8 CR0 Control Bit 0 used in conjunction with CR1 to implement the various data loading functions. DB0 the LSB of the 8-bit data word. 0 X 0 0 Both DAC registers loaded from shift register. 0 0 0 1 Update DAC A input register from shift register. 0 1 0 1 Update DAC B input register from shift register. 0 0 1 0 Update DAC A DAC register from input register. 0 1 1 0 Update DAC B DAC register from input register. 0 0 1 1 Update DAC A DAC register from shift register. 0 1 1 1 Update DAC B DAC register from shift register. both DAC A and DAC B DAC registers. both DAC A and DAC B DAC registers outputs. 0 Internal V DD/2 reference selected.

1 External reference selected; this external reference is applied at the REF pin and ranges from

0 1 DAC A active and DAC B in power-down mode. 1 0 DAC A in power-down mode and DAC B active. Figure 24. Input Shift Register Contents

–14– REV. 0 AD7303 to 68HC11 Interface Program Source Code PORTC EQU $1003 Port C Control Register DDRC EQU $1007 Port C Data Direction PORTD EQU $1008 Port D Data Register DDRD EQU $1009 Port D Data Direction SPCR EQU $1028 SPI Control Register * "SPIE, SPE, DWOM, MSTR, CPOL, CPHA, SPR1, SPR0" SPSR EQU $1029 SPI Status Register * "SPIF, WCOL, 0, MODF, 0, 0, 0, 0" SPDR EQU $102A SPI Data Register, Read Buffer, Write Shifter * SDI RAM Variables: DIN 1 is eight MSBs, Control BYTE DIN 2 is eight LSBs, Data BYTE DAC requires 2*8-bit Writes DIN1 EQU $00 DIN BYTE 1: " INT/EXT, X, LDAC, PDB, PBA, A/B, CR1, CR0" DIN2 EQU $01 DIN BYTE 2: " DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0" ORG $C000 Start of users ram INIT LDS #$CFFF Top of C page Ram * SYNC is High STAA PORTC Initialize Port C Outputs STAA DDRC SYNC enabled as output * SCLK is low, DIN is low STAA PORTD Initialize Port D outputs Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD7303 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD7303 is in a system where multiple devices require an AGND to DGND connection, the connec- tion should be made at one point only. The star ground point should be established as closely as possible to the AD7303. The AD7303 should have ample supply bypassing of 10 µF in paral- lel with 0.1 µF on the supply located as closely to the package as possible, ideally right up against the device. The 10 µF capaci- tors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD7303 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching sig- nals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digi- tal and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.

–15–REV. 0 * SCLK and DIN enabled as outputs LDAA #$53 STAA SPCR SPI on, Master mode, CPOL=0, CPHA=0, Clock rate =E/32 BSR UPDATE Update AD7303 output. JMP #$E000 Restart. UPDATE PSHX Save relevant registers. PSHY PSHA LDAA #$00 Control Word "0, 0, 0, 0, 0, 0, 0, 0" STAA DIN 1 Load both DAC A and DAC B DAC registers from shift register with internal reference selected. LDAA #$AA Data Word "1, 0, 1, 0, 1, 0, 1, 0" STAA DIN 2 LDX #DIN1 Stack pointer at first first byte to send via DIN 1. LDY #$1000 Stack pointer at on chip registers. BCLR PORTC,Y $80 Assert SYNC. TRANSFER LDAA 0,X Get BYTE to transfer via SPI. STAA SPDR Write to DIN register to start transfer. WAIT LDAA SPSR Wait for SPIF to be set to indicate that transfer has been completed. BPL WAIT SPIF is the MSB of the SPCR. SPIF is automatically reset if in a set state when the status register is read. INX Increment counter for transfer of second byte. CPX #DIN 2+1 16 bits transferred? BNE TRANSFER If not, transfer second BYTE. *Execute instruction BSET PORTC,Y $80 Bring SYNC back high. PULA Restore registers. PULY PULX RTS Return to main program.

–16– REV. 0 C2224–12–1/97PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35)SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 8-Lead microSOIC (RM-8) 8 5 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.122 (3.10) 0.114 (2.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33° 27° 0.120 (3.05) 0.112 (2.84)