AD7302

AD7302 2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC

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Technical content

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7302 Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC FUNCTIONAL BLOCK DIAGRAM POWER ON RESET CS WR REFIN VDD AD7302 VOUT A DGND AGND A/B CLR LDACPD I/V VOUT B MUX INPUT REGISTER DAC REGISTER I DAC A DAC REGISTER I DAC B I/VINPUT REGISTER CONTROL LOGIC

FEATURES

Two 8-Bit DACs In One Package 20-Lead DIP/SOIC/TSSOP Package +2.7 V to +5.5 V Operation Internal and External Reference Capability DAC Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Low Power Operation 3 mA max @ 3.3 V Power-Down to 1 mA max @ 25 8C

APPLICATIONS

Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION The AD7302 is a dual, 8-bit voltage out DAC that operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output buffers allow the DAC outputs to swing rail to rail. The AD7302 has a parallel microprocessor and DSP-compatible interface with high speed registers and double buffered interface logic. Data is loaded to the registers on the rising edge of CS or WR and the A/B pin selects either DAC A or DAC B. Reference selection for AD7302 can be either an internal reference derived from the V DD or an external reference applied at the REFIN pin. Both DACs can be simultaneously updated using the asynchronous LDAC input and can be cleared by using the asynchronous CLR input. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consump- tion is less than 10 mW at 3.3 V, reducing to 3 µW in power- down mode. The AD7302 is available in a 20-pin plastic dual-in-line package, 20-lead SOIC and a 20-lead TSSOP package. PRODUCT HIGHLIGHTS 1.␣ Low Power, Single Supply Operation. This part operates from a single +2.7 V to +5.5 V supply and typically consumes 15 mW at 5 V, making it ideal for battery powered applications. 2.␣ The on-chip output buffer amplifiers allow the outputs of the DACs to swing rail to rail with a settling time of typically 1.2µs. 3.␣ Internal or external reference capability. 4.␣ High speed parallel interface. 5. Power-Down Capability. When powered down the DAC consumes less than 1 µA at 25°C. 6. Packaged in 20-lead DIP, SOIC and TSSOP packages.

–2– REV. 0 AD7302–SPECIFICATIONS (VDD = +2.7 V to +5.5 V, Internal Reference; C L = 100 pF, RL = 10 kV to VDD and GND; to TMAX unless otherwise noted) Parameter B Versions 1 Units Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy ± 1 LSB max Note 2 Differential Nonlinearity ± 1 LSB max Guaranteed Monotonic Full-Scale Error –0.75 LSB typ Zero Code Error @ 25 °C 3 LSB typ All Zeroes Loaded to DAC Register Gain Error 3 ± 1 % FSR typ Zero Code Temperature Coefficient 100 µV/°C typ DAC REFERENCE INPUT REFIN Input Range 1.0 to V DD/2 V min to max REFIN Input Impedance 10 M Ω typ OUTPUT CHARACTERISTICS Output Voltage Range 0 to V DD V min to max Output Voltage Settling Time 2 µs max Typically 1.2 µs Slew Rate 7.5 V/ µs typ Digital to Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry Digital Feedthrough 0.2 nV-s typ Digital Crosstalk 0.2 nV-s typ Analog Crosstalk ± 0.2 LSB typ DC Output Impedance 40 Ω typ Short Circuit Current 14 mA typ Power Supply Rejection Ratio 4 0.0003 %/% max ΔVDD = ± 10% LOGIC INPUTS Input Current ± 10 µA max VINL, Input Low Voltage 0.8 V max V DD = +5 V VINL, Input Low Voltage 0.6 V max V DD = +3␣ V VINH, Input High Voltage 2.4 V min V DD = +5 V VINH, Input High Voltage 2.1 V min V DD = +3 V Pin Capacitance 7 pF max POWER REQUIREMENTS VDD 2.7/5.5 V min/max IDD Both DACs Active and Excluding Load Currents VDD = 3.3 V V IH = VDD and VIL = GND @ 25°C 2.8 mA max Typically 2.3 mA @ TMIN to TMAX 3 mA max See Figures 6 and 7 VDD = 5.5 V V IH = VDD and VIL = GND @ 25°C 4.5 mA max Typically 2.8 mA @ TMIN to TMAX 5 mA max See Figures 6 and 7 IDD (Full Power-Down) @ 25°C1 µA max V IH = VDD and VIL = GND TMIN to TMAX 2 µA max See Figure 18 NOTES 1Temperature ranges are as follows: B Version: –40 °C to +105 °C. 2Relative Accuracy is calculated using a reduced code range of 15 to 245. 3Gain error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4Guaranteed by characterization at product release, not production tested. Specifications subject to change without notice.

(VIL + VIH)/2. tr and tf should not exceed 1 µs on any digital input. Figure 1. Timing Diagram for Parallel Data Write

–4– REV. 0 ORDERING GUIDE Temperature Package Model Range Options* AD7302BN –40 °C to +105°C N-20 AD7302BR –40 °C to +105°C R-20 AD7302BRU –40 °C to +105°C RU-20 *N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) V Operating Temperature Range Lead Temperature, Soldering θ Lead Temperature, Soldering *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7302 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1-8 D7–D0 Parallel D ata Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS and WR. 9 CS Chip Select. Active low logic input. 10 WR Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected DAC register. 11 A/B DAC Select. Address pin used to select writing to either DAC A or DAC B. 12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA. 13 LDAC Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising edge of WR. 14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all zeroes and the DAC outputs are cleared to zero volts. 15 V DD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND. 16 REFIN External Reference Input. This can used as the reference for both DACs. The range on this reference input is 1 V to VDD/2. If REFIN is directly tied to V DD the internal VDD/2 reference is selected. 17 AGND Analog Ground reference point and return point for all analog current on the part. 18 V OUTB Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output. 19 V OUTA Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output. 20 DGND Digital Ground reference point and return point for all digital current on the part. PIN CONFIGURATION TOP VIEW (Not to Scale) AD7302 (MSB) DB7 AGND VOUT B VOUT A DGND DB6 DB5 DB4 CLR V DD REFINDB3 DB2 DB1 (LSB) DB0 CS WR A/B PD LDAC

–6– REV. 0 TERMINOLOGY INTEGRAL NONLINEARITY For the DACs, relative accuracy or endpoint nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A graphical representation of the transfer curve is shown in Figure 14. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. ZERO CODE ERROR Zero Code Error is the measured output voltage from V OUT of either DAC when zero code (all zeros) is loaded to the DAC latch. It is due to a combination of the offset errors in the DAC and output amplifier. Zero scale error is expressed in LSBs. GAIN ERROR This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale value. It includes full-scale errors but not offset errors. DIGITAL-TO-ANALOG GLITCH IMPULSE Digital-to-Analog Glitch Impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. DIGITAL FEEDTHROUGH Digital Feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same DAC, but is measured when the DAC is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. DIGITAL CROSSTALK Digital Crosstalk is the glitch impulse transferred to the output of one converter due to a digital code change to another DAC. It is specified in nV-s. ANALOG CROSSTALK Analog Crosstalk is a change in output of any DAC in response to a change in the output of the other DAC. It is measured in LSBs. POWER SUPPLY REJECTION RATIO (PSRR) This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of % change in output per % change in V DD for full-scale output of the DAC. V DD is varied ± 10%.

Figure 11. Power-On—RESET Figure 14. Integral Linearity Plot Figure 12. Zero Code Error vs. Figure 15. Typical INL vs. Temperature

10 LSB STEP CHANGE

Figure 13. Small-Scale Settling Time Figure 16. Typical DNL vs. Temperature Figure 17. Typical Internal Reference Figure 18. Power-Down Current vs.

Figure 19. DAC Architecture DD/2 when the internal reference is selected. register and ranges from 0 to 255. externally applied reference can be selected. Figure 20. Reference Selection Circuitry reference source for the DAC. on reset phase of the power-up procedure. Figure 21. Logic Interface a block diagram of the register arrangement within the AD7302.

4 TO 15

Figure 22. Register Arrangement

Figure 26. DAC Transfer Function Figure 27. Typical Configuration Selecting the Internal

1 V to V

reference would be the AD589 a 1.23 V bandgap reference. Figure 28. Typical Configuration Using An External

–13–REV. 0 Bipolar Operation Using the AD7302 The AD7302 has been designed for single supply operation, but bipolar operation is achievable using the circuit shown in Figure 32. The circuit shown has been configured to achieve an REF is the reference voltage input. Figure 32. Bipolar Operation Using the AD7302

1 AD7302

Figure 33. Decoding Multiple AD7302 DACs in a System Figure 34. Programmable Window Detector

–15–REV. 0 20-Lead Plastic DIP (N-20) 11 0 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-Lead SO (R-20) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 20 11 101 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 20-Lead TSSOP (RU-20) 20 11 101 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

–16– C2990–12–4/97PRINTED IN U.S.A.