AD7228

AD7228 (Rev. D)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 15

Technical content

Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 1992–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Eight 8-bit DACs with output amplifiers Operates with single or dual supplies Microprocessor-compatible (95 ns WR pulse) No user trims required Skinny 24-lead PDIP, C E R D I P, and SOIC packages, and a 28-lead PLCC surface-mount package FUNCTIONAL BLOCK DIAGRAM VSS GND LATCH 5 DAC 5 LATCH 6 DAC 6 LATCH 7 DAC 7 LATCH 8 CONTROL LOGIC DAC 8 VOUT88 WR A2 AD7228 10 12 11 1 VOUT77 VOUT66 VOUT55 VOUT44 VOUT33 VOUT22 VOUT11 LATCH 1 DAC 1 LATCH 2 DAC 2 LATCH 3 DAC 3 LATCH 4 DAC 4 DATA BUS VREF VDD MSB DATA (8-BIT) LSB 13034-001 F igure 1. GENERAL DESCRIPTION The AD7228 contains eight 8-bit voltage mode digital-to- analog converters (DACs), with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve the full specified performance for the device. Separate on-chip latches are provided for each of the eight DACs. Data is transferred into the data latches through a common 8-bit, TTL/CMOS-compatible input port (5 V). The A0, A1, and A2 address inputs determine which latch is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from 2 V to 10 V when using dual supplies. The device is also specified for single-supply operation using a reference of 10 V. Each output buffer amplifier is capable of developing 10 V across a 2 kΩ load. The AD7228 is fabricated on an all ion implanted, high speed, linear-compatible CMOS (LC2MOS) process, specifically developed to integrate high speed digital logic circuits and precision analog circuits on the same chip. PRODUCT HIGHLIGHTS 1. The single chip design of eight 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. The PDIP , CERDIP , and SOIC pinout is aimed at optimizing board layout with all analog inputs and outputs at one side of the package and all digital inputs at the other. 2. The voltage mode configuration of the DACs allows single supply operation of the AD7228. The device can also be operated with dual supplies giving enhanced performance for some parameters. 3. The AD7228 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered and speed compatible with most high performance 8-bit microprocessors.

Rev. D | Page 2 of 15 TABLE OF CONTENTS

REVISION HISTORY

10/2017—Rev. C to Rev. D —Rev. B to Rev. C

Rev. D | Page 3 of 15 SPECIFICATIONS DUAL SUPPLY VDD = 10.8 V to 16.5 V , VSS = −5 V ± 10%, GND = 0 V , VREF = 2 V to 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C unless otherwise noted. VOUT must be less than VDD by 3.5 V to ensure correct operation. Table 1. Parameter K and B Versions L and C Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error (TUE)1 ±2 ±1 LSB max VDD = 15 V ± 10%, VREF = 10 V Relative Accuracy ±1 ±1/2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic Full-Scale Error2 ±1 ±1/2 LSB max Typical temperature coefficient is 5 ppm/°C with VREF = 10 V Zero Code Error at 25°C ±25 ±15 mV max Typical temperature coefficient is 30 µV/°C TMIN to TMAX ±30 ±20 mV max Minimum Load Resistance 2 2 kΩ min VOUT = 10 V REFERENCE INPUT Voltage Range 2/10 2/10 V min/V max Input Resistance 2 2 kΩ min Input Capacitance3 500 500 pF max Occurs when each DAC is loaded with all 1s AC Feedthrough −70 −70 dB typ VREF = 8 V p-p sine wave at 10 kHz DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 µA max VIN = 0 V or VDD Input Capacitance3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE3 Voltage Output Slew Rate 2 2 V/µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 µs max VREF = 10 V; settling time to ±1/2 LSB Negative Full-Scale Change 5 5 µs max VREF = 10 V; settling time to ±1/2 LSB Digital Feedthrough 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 0 V; WR = VDD Digital Crosstalk4 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 10 V; WR = 0 V POWER SUPPLIES VDD Range 10.8/16.5 10.8/16.5 V min/V max For specified performance VSS Range −4.5/−5.5 −4.5/−5.5 V min/V max For specified performance IDD Out puts unloaded; VIN = VINL or VINH at 25°C 16 16 mA max TMIN to TMAX 20 20 mA max ISS Out puts unloaded; VIN = VINL or VINH at 25°C 14 14 mA max TMIN to TMAX 18 18 mA max 1 Total unadjusted error includes zero code error, relative accuracy, and full-scale error. 2 Calculated after zero code error is adjusted out. 3 Sample tested at TA = 25°C to ensure compliance. 4 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.

Rev. D | Page 4 of 15 SINGLE SUPPLY VDD = 15 V ± 10%, VSS = GND, GN D = 0 V, VREF = 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C, unless otherwise noted. Table 2. Parameter K and B Versions L and C Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error1 ±2 ±1 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic Minimum Load Resistance 2 2 kΩ min VOUT = 10 V REFERENCE INPUT Input Resistance 2 2 kΩ min Input Capacitance2 500 500 pF max Occurs when each DAC is loaded with all 1s DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 µA max VIN = 0 V or VDD Input Capacitance2 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE2 Voltage Output Slew Rate 2 2 V/µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 µs max Settling time to ±1/2 LSB Negative Full-Scale Change 7 7 µs max Settling time to ±1/2 LSB Digital Feedthrough 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 0 V, WR = VDD Digital Crosstalk3 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 10 V, WR = 0 V POWER SUPPLIES VDD Range 13.5/16.5 13.5/16.5 V min/V max For specified performance IDD Out puts unloaded; VIN = VINL or VINH at 25°C 16 16 mA max TMIN to TMAX 20 20 mA max 1 Total unadjusted error includes zero code error, relative accuracy and full-scale error. 2 Sample tested at TA = 25°C to ensure compliance. 3 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.

Rev. D | Page 5 of 15 SWITCHING CHARACTERISTICS See Figure 8 and Figure 2; VDD = 5 V ± 5% or 10.8 V to 16.5 V; VSS = 0 V or –5 V ± 10%. Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of 5 V, tR = tF = 5 ns. Timing measurement reference level is (VINH + VINL)/2. Table 3. Parameter Limit at 25°C, All Grades Limit at TMIN, TMAX, K, L, B, and C Versions Unit Description t1 0 0 ns min Address to WR setup time t2 0 0 ns min Address to WR hold time t3 70 90 ns min Data valid to WR setup time t4 10 10 ns min Data valid to WR hold time t5 95 120 ns min Write pulse width VINH VINL WR ADDRESS NOTES 1. THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS. DATA 13034-003 F igure 2. Write Cycle Timing Diagram

Rev. D | Page 6 of 15 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDD to GND −0.3 V to +17 V VDD to VSS −0.3 V to +24 V Digital Input Voltage to GND −0.3 V to VDD VREF to GND −0.3 V to VDD VOUTx to GND1 VSS, VDD Power Dissipation (Any Package) to 75°C 1000 mW Derates Above 75°C by 2.0 mW/°C Operating Temperature Range Commercial −40°C to +85°C Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C

1 Outputs can be shorted to any voltage in the range VSS to VDD provided that

the power dissipation of the package is not exceeded. Typical short-circuit current fora short to GND or VSS is 50 mA. S tresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

Rev. D | Page 8 of 15 THEORY OF OPERATION CIRCUIT INFORMATION DACs The AD7228 contains eight identical, 8-bit, voltage mode DACs. The output voltages from the converters have the same polarity as the reference voltage, allowing single-supply operation. A novel DAC switch pair arrangement on the AD7228 allows a reference voltage range from 2 V to 10 V . Each DAC consists of a highly stable, thin film, R-2R ladder and eight high speed NMOS switches. The simplified circuit diagram for one channel is shown in Figure 5. Note that V REF and GND are common to all eight DACs. RR R DB7 DB6 DB5 VREF VOUT NOTES 1. SHOWN FOR ALL 1s ON DAC. GND DB0 13034-006 Figure 5. DAC Simplified Circuit Diagram The input impedance at the VREF pin of the AD7228 is the parallel combination of the eight individual DAC reference input imp- edances. It is code dependent and can vary from 2 kΩ to infinity. The lowest input impedance occurs when all eight DACs are loaded with digital code 01010101. Therefore, it is important that the external reference source presents a low output imp- edance to the V REF terminal of the AD7228 under changing load conditions. Due to transient currents at the reference input during digital code changes, a 0.1 μF (or greater) decoupling capacitor is recommended on the V REF input for dc applications. The nodal capacitance at the reference terminal is also code dependent and typically varies from 120 pF to 350 pF. Consider each V OUTX pin as a digitally programmable voltage source with an output voltage. VOUTx = DN × VREF where DN is a fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier as described in the Op Amp section. Op Amp Each voltage mode DAC output is buffered by a unity-gain, noninverting, CMOS amplifier. This buffer amplifier is tested with a 2 kΩ and 100 pF load, but typically drives a 2 kΩ and 500 pF load. The AD7228 can be operated from single or dual supplies. Operating the device from single or dual supplies has no effect on the positive going settling time. However, the negative going settling time to voltages near 0 V in single-supply operation is slightly longer than the settling time for dual supply operation. Additionally, to ensure that the output voltage can go to 0 V in single-supply operation, a transistor on the output acts as a passive pull-down as the output voltage nears 0 V . As a result, the sink capability of the amplifier is reduced as the output voltage nears 0 V in single-supply operation. In dual supply operation, the full sink capability of 400 μA at 25°C is maintained over the entire output voltage range. The single-supply output sink capability is shown in Figure 6. The negative V SS also gives improved output amplifier performance, allowing an extended input reference voltage range and giving an improved slew rate at the output. 600 500 400 300 200 100 123456 OUTPUT VOLTAGE (V) ISINK (µA) 789 1 0 VDD = +15V VSS = 0V TA = –55°C TA = +25°C TA = +125°C 13034-007 Figure 6. Single Supply Sink Current The output broadband noise from the amplifier is 300 μV p-p. Figure 7 shows a plot of noise spectral density vs. frequency. 700 600 500 400 300 200 100 FREQUENCY (Hz) 100 1k 10k 100k NOISE SPECTRAL DENSITY (nV/√Hz) 13034-008 VDD = +15V VSS = –5V TA = 25°C Fig ure 7. Noise Spectral Density vs. Frequency Digital Inputs The AD7228 digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by on-chip distributed diodes.

the eight DACs and Figure 8 shows the input control logic. Table 6. AD7228 Truth Table range. Figure 9 shows a typical plot of power supply current vs.

1. Power Supply Current vs. Temperature

Table 7. Unipolar Code Table

128 REFV+ =

Table 8. Bipolar Code Table therefore, these resistors must match and track over temperature. relationship for the circuit of Figure 11 with R1 = R2. limits of reference voltage when operated with dual supplies. *ADDITIONAL PINS OMITTED FOR CLARITY. *ADDITIONAL PINS OMITTED FOR CLARITY.

comparator, and the signals are applied to the other inputs. AL PINS OMITTED FOR CLARITY. Figure 14. AD7

228 Timing Deskew Circuit

using one external op amp and a few resistors per pair of DACs. available from Analog Devices, Inc.). *ADDITIONAL PINS OMITTED FOR CLARITY. *ADDITIONAL PINS OMITTED FOR CLARITY.

effective 10-bit dynamic range to the other seven converters. VSS is equal to −5 V and R1 be greater than 6.8 kΩ.

5 V Single-Supply Operation

Figure 18 is for a device with a true positive offset. reduces the power dissipation considerably (typically to 50 mW). not affected by operating the device from the single 5 V supply.

1. Relative Accuracy at VDD = 5 V

1FOR 8085A, DATA BUS NEEDS TO BE DEMULTIPLEXED. 3ADDITIONAL PINS OMITTED FOR CLARITY. Figure 19. AD7 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 20. AD7

*ADDITIONAL PINS OMITTED FOR CLARITY. Figure 21. AD7

8051 AD7228*

*ADDITIONAL PINS OMITTED FOR CLARITY. Figure 22. AD7

Rev. D | Page 14 of 15 OUTLINE DIMENSIONS CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. COMPLIANT TO JEDEC STANDARDS MS-001 071006-A 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.060 (1.52) 0.045 (1.14) 1 12 0.100 (2.54) BSC 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) MAX SEATING PLANE 0.015 (0.38) MIN0.005 (0.13) MIN 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) MAX 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) GAUGE PLANE 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) F igure 23. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1 12 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) MIN 0.098 (2.49) MAX 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 1.280 (32.51) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) PIN 1 100808-A F igure 24. 24-Lead Ceramic Dual In-Line Package [CERDIP] Narrow Body (Q-24-1) Dimensions shown in inches and (millimeters)

Rev. D | Page 15 of 15 COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45° 1.27 (0.0500) 0.40 (0.0157) COPLANARITY 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 24 13 121 1.27 (0.0500) BSC 12-09-2010-A Fig ure 25. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. TOP VIEW (PINS DOWN) SQ0.456 (11.582) 0.450 (11.430) 0.050 (1.27) BSC 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32)SQ 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) MIN 0.180 (4.57) 0.165 (4.19) BOTTOM VIEW (PINS UP) 0.045 (1.14) 0.025 (0.64) R PIN 1 IDENTIFIER 042508-A Fig ure 26. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Maximum TUE (LSB) Package Description Package Option AD7228BQ −40°C to +85°C ±2 24-Lead CERDIP Q-24-1 AD7228CQ −40°C to +85°C ±1 24-Lead CERDIP Q-24-1 AD7228KN −40°C to +85°C ±2 24-Lead PDIP N-24-1 AD7228KNZ −40°C to +85°C ±2 24-Lead PDIP N-24-1 AD7228KP −40°C to +85°C ±2 28-Lead PLCC P-28 AD7228KP-REEL −40°C to +85°C ±2 28-Lead PLCC P-28 AD7228KPZ −40°C to +85°C ±2 28-Lead PLCC P-28 AD7228KR −40°C to +85°C ±2 24-Lead SOIC_W RW-24 AD7228KRZ −40°C to +85°C ±2 24-Lead SOIC_W RW-24 AD7228LNZ −40°C to +85°C ±1 24-Lead PDIP N-24-1 AD7228LPZ −40°C to +85°C ±1 28-Lead PLCC P-28 1 Z = RoHS Compliant Part. ©1992–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13034-0-10/17(D)