AD7226KP

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REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: © 20 Analog Devices, Inc. All rights reserved. AD7226 LC2MOS Quad 8-Bit D/A Converter FUNCTIONAL BLOCK DIAGRAM CONTROL LOGIC DAC A DAC B DAC C DAC D LATCH A LATCH B LATCH C LATCH D A B C D MSB DATA (8-BIT) LSB WR VSS AGND AGND VREF VDD VOUTA VOUTB VOUTC VOUTD D A T A B U S AD7226 GENERAL DESCRIPTION The AD7226 contains four 8-bit voltage-output digital-to- analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve full specified performance for the part. Separate on-chip latches are provided for each of the four D/A converters. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS (5 V) compatible input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed-compat- ible with most 8-bit microprocessors. Each D/A converter includes an output buffer amplifier capable of driving up to 5 mA of output current. The amplifiers’ offsets are laser-trimmed during manufacture, thereby eliminating any requirement for offset nulling. Specified performance is guaranteed for input reference voltages from 2 V to 12.5 V with dual supplies. The part is also specified for single supply operation at a reference of 10 V. The AD7226 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC 2MOS) process, which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. PRODUCT HIGHLIGHTS 1. DAC-to-DAC Matching Since all four DACs are fabricated on the same chip at the same time, precise matching and tracking between the DACs is inherent. 2. Single-Supply Operation The voltage mode configuration of the DACs allows the AD7226 to be operated from a single power supply rail. 3. Microprocessor Compatibility The AD7226 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered. 4. Small Size Combining four DACs and four op amps plus interface logic into a 20-pin package allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one end of the package and all the digital inputs at the other.

FEATURES

Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages Microprocessor-Compatible TTL/CMOS-Compatible No User Trims Extended Temperature Range Operation Single Supply Operation Possible

APPLICATIONS

Automatic Calibration of Large System Parameters, e.g., Gain/Offset

REV.–2– AD7226–SPECIFICATIONS (VDD = 11.4 V to 16.5 V, VSS = –5 V /H11550 10%, AGND = DGND = 0 V; VREF = +2 V to (VDD – 4 V)1, unless otherwise noted. All Specifications TMIN to TMAX unless otherwise noted.) DUAL SUPPLY Parameter K, B Versions2 Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Total Unadjusted Error ± 1L SB max V DD = 15 V ± 5%, VREF = 10 V Relative Accuracy ± 0.5 LSB max Differential Nonlinearity ± 1L SB max Guaranteed Monotonic Full-Scale Error ± 0.5 LSB max Full-Scale Temperature Coefficient ± 20 ppm/ ∞C typ V DD = 14 V to 16.5 V, VREF = +10 V Zero Code Error ± 20 mV max Zero Code Error Temperature Coefficient ± 50 mV/∞C typ REFERENCE INPUT Voltage Range 2 to (V DD – 4) V min to V max Input Resistance 2 kW min Input Capacitance3 50 pF min Occurs when each DAC is loaded with all 0s. 200 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Leakage Current ± 1 mA max VIN = 0 V or VDD Input Capacitance 8 pF max Input Coding Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 4 2.5 V/ms min Voltage Output Settling Time 4 4 ms max V REF = 10 V; Settling Time to ± 1/2 LSB Digital Crosstalk 10 nV secs typ Minimum Load Resistance 2 kW min VOUT = 10 V POWER SUPPLIES VDD Range 11.4/16.5 V min/V max For Specified Performance IDD 13 mA max Outputs Unloaded; VIN = VINL or VINH ISS 11 mA max Outputs Unloaded; VIN = VINL or VINH SWITCHING CHARACTERISTICS 4, 5 Address to Write Setup Time, t AS 0n s min Address to Write Hold Time, t AH 0n s min Data Valid to Write Setup Time, t DS 50 ns min Data Valid to Write Hold Time, t DH 0n s min Write Pulsewidth, tWR 50 ns min NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: K Version: –40 ∞C to +85∞C B Version: –40 ∞C to +85∞C 3Guaranteed by design. Not production tested. 4Sample Tested at 25 ∞C to ensure compliance. 5Switching Characteristics apply for single and dual supply operation. Specifications subject to change without notice. o f

REV. AD7226 –3– SINGLE SUPPLY Parameter K, B Versions2 Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Total Unadjusted Error ± 2L SB max Differential Nonlinearity ± 1L SB max Guaranteed Monotonic REFERENCE INPUT Input Resistance 2 k W min Input Capacitance3 50 pF min Occurs when each DAC is loaded with all 0s. 200 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.8 V max Input Leakage Current ± 1 mA max V IN = 0 V or VDD Input Capacitance 8 pF max Input Coding Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 4 2V /ms min Voltage Output Settling Time 4 4 ms max Settling Time to ± 1/2 LSB Digital Crosstalk 10 nV secs typ Minimum Load Resistance 2 kW min V OUT = +10 V POWER SUPPLIES VDD Range 14.25/15.75 V min/V max For Specified Performance IDD 13 mA max Outputs Unloaded; V IN = VINL or VINH NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: K Version: –40 ∞C to +85∞C B Version: –40 ∞C to +85∞C 3Guaranteed by design. Not production tested. 4Sample Tested at 25 ∞C to ensure compliance. Specifications subject to change without notice. (VDD = 15 V /H11550 5%, VSS = AGND = DGND = O V; VREF = 10 V1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 50 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. o f

REV.–4– AD7226 PIN CONFIGURATIONS DIP and SOIC/SSOP TOP VIEW (Not to Scale) AD7226 VREF AGND DGND DB7 (MSB) DB6 WR DB0(LSB) DB5 DB4 DB3 DB2 DB1 VSS VOUTA VOUTBV OUTC VOUTD VDD PLCC 3 2 1 20 19 9 10 11 12 13 TOP VIEW (Not to Scale) VREF AGND DGND DB7 (MSB) DB8 AD7226 VDD WR DB0(LSB) DB5 DB4 DB3 DB2 DB1 V SS VOUTA VOUTB VOUTC VOUTD TERMINOLOGY TOTAL UNADJUSTED ERROR This is a comprehensive specification that includes full-scale error, relative accuracy and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is V REF/ 256. The LSB size will vary over the V REF range. Hence the zero code error will, relative to the LSB size, increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSB’s over the V REF range. As a result, total unadjusted error is specified for a fixed refer- ence voltage of 10 V. RELATIVE ACCURACY Relative Accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full-scale error and is normally expressed in LSB’s or as a percentage of full-scale reading. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. DIGITAL CROSSTALK The glitch impulse transferred to the output of one converter due to a change in the digital input code to another of the con- verters. It is specified in nV secs and is measured at V REF = 0 V. FULL SCALE ERROR Full-Scale Error is defined as: Measured Value – Zero Code Error – Ideal Value o f

REV. Typical Performance Characteristics–AD7226 –7– (TA = 25/H11543C, VDD = 15 V, VSS = –5 V) INPUT CODE (DECIMAL EQUIVALENT) 2.0 0 16 TOTAL UNADJUSTED ERROR (LSBs) 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 VREF = 10V TPC 1. Channel-to-Channel Matching VREF (V) 01 4 2468 1 0 1 2 RELA TIVE ACCURACY (LSBs) AD7226K, B TPC 2. Relative Accuracy vs. V REF VREF (V) 01 4 2468 1 0 1 2 DIFFERENTIAL NONLINEARITY (LSBs) AD7226K, B TPC 3. Differential Nonlinearity vs. V REF TEMPERA TURE (/H11543C) 2.0 01 0 ZERO CODE ERROR (LSBs) 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 20 30 40 50 60 70 80 90 100 110 120 130 VOUTA VOUTB VOUTC VOUTD TPC 4. Zero Code Error vs. Temperature

Figure 10. AGND Bias Circuit of the AD7226 should be referenced to DGND. cycle is generated by stepping through the full look-up table. ing the D/A converter outputs. R and is given by the formula. and DD is a fractional representation of the digital word in latch D.

4.0 VIN

3.5 VIN

3.0 VIN

2.5 VIN

2.0 VIN

1.5 VIN

Figure 12. Variation of V REF with Feedback Configuration Figure 11. 3-Phase Sine Wave Generation Circuit Figure 13. 3-Phase Sine Wave Output

0.05 MIN

0.65 BSC

2.00 MAX

Figure 3. 20-Lead Shrink Small Outline Package [SSOP] REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 20-Lead Standard Small Outline Package [SOIC_W]

Rev. D | Page COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.020 (0.50) R BOTTOM VIEW (PINS UP) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) MIN 0.120 (3.04) 0.090 (2.29) TOP VIEW (PINS DOWN) 0.395 (10.03) 0.385 (9.78)SQ 0.356 (9.04) 0.350 (8.89)SQ 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) R 0.050 (1.27) BSC 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) R PIN 1 IDENTIFIER Figure 5. 20-Lead Plastic Leaded Chip Carrier [PLCC] 3 N = plastic DIP; P = plastic leaded chip carrier; Q = CERDIP; RW = SPIC; RS = SSOP.

REVISION HISTORY

1/11—Rev. C to Rev. D 3/03—Rev. B to Rev. C 3/03—Rev. A to Rev. B

Rev. D | Page NOTES ©2003-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00987-0-1/11(D)