AD7225KP-REEL

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with Separate Reference Inputs AD7225 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Four 8-bit DACs with output amplifiers Separate reference input for each DAC Microprocessor compatible with double-buffered inputs Simultaneous update of all 4 outputs Operates with single or dual supplies Extended temperature range operation No user trims required Skinny 24-lead PDIP , CERDIP , SOIC, and SSOP packages 28-lead PLCC package FUNCTIONAL BLOCK DIAGRAM VREFA VREFB VREFC VREFD VDD LDAC VSS AGND DGND INPUT LATCH A DAC LATCH A VOUTADAC A A INPUT LATCH B DAC LATCH B VOUTBDAC B B INPUT LATCH C DAC LATCH C VOUTCDAC C C INPUT LATCH D CONTROL LOGIC DAC LATCH D VOUTDDAC D D DATA BUS DB7 DATA (8-BIT) DB0 WR AD7225 00986-001 Figure 1. GENERAL DESCRIPTION The AD7225 contains four 8-bit voltage output digital-to- analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. Each DAC has a separate reference input terminal. No external trims are required to achieve full specified performance for the part. The double-buffered interface logic consists of two 8-bit registers per channel—an input register and a DAC register. Control Input A0 and Control Input A1 determine which input register is loaded when WR goes low. Only the data held in the DAC registers determines the analog outputs of the converters. The double-buffering allows simultaneous update of all four outputs under control of LDAC. All logic inputs are TTL and CMOS (5 V) level compatible, and the control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from 2 V to 12.5 V when using dual supplies. The part is also specified for single-supply operation using a reference of 10 V . Each output buffer amplifier is capable of developing 10 V across a 2 kΩ load. The AD7225 is fabricated on an all ion-implanted, high speed, linear-compatible CMOS (LC 2MOS) process, which is specifically developed to integrate high speed digital logic circuits and precision analog circuitry on the same chip. PRODUCT HIGHLIGHTS 1. DACs and Amplifiers on CMOS Chip. The single-chip design of four 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all analog inputs and outputs at one end of the package and all digital inputs at the other. 2. Single- or Dual-Supply Operation. The voltage-mode configuration of the AD7225 allows single-supply operation. The part can also be operated with dual supplies, giving enhanced performance for some parameters. 3. Versatile Interface Logic. The AD7225 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. The double-buffered interface allows simultaneous update of the four outputs. 4. Separate Reference Input for Each DAC. The AD7225 offers great flexibility in dealing with input signals, with a separate reference input provided for each DAC and each reference having variable input voltage capability.

Rev. C | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

3/10—Rev. B to Rev. C Deleted 28-Terminal Leadless Ceramic Chip Carrier Changes to Pin Configurations and Function Descriptions Changes to Programmable Transversal Filter Section and

Rev. C | Page 3 of 24 SPECIFICATIONS VDD = 11.4 V to 16.5 V , VSS = −5 V ± 10%; AGND = DGND = 0 V; VREFx = +2 V to (VDD − 4 V)1 Parameter , unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 1. K, B Versions2 L, C Versions

2 Unit Conditions/Comments

Total Unadjusted Error ±2 ±1 LSB max VDD = 15 V ± 5%, VREF = 10 V Relative Accuracy ±1 ±1/2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic Full-Scale Error ±1 ±1/2 LSB max Full-Scale Temperature Coefficient ±5 ±5 ppm/°C typ VDD = 14 V to 16.5 V, VREF = 10 V Zero Code Error ±30 ±20 mV max Zero Code Error Temperature Coefficient ±30 ±30 μV/°C typ REFERENCE INPUT Voltage Range 2 to (VDD − 4) 2 to (VDD − 4) V min to V max Input Resistance 11 11 kΩ min Input Capacitance3 50 50 pF max Occurs when each DAC is loaded with all 1s Channel-to-Channel Isolation3 60 60 dB min VREF = 10 V p-p sine wave at 10 kHz AC Feedthrough3 −70 −70 dB max VREF = 10 V p-p sine wave at 10 kHz DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 μA max VIN = 0 V or VDD Input Capacitance3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate3 2.5 2.5 V/μs min Voltage Output Settling Time3 4 4 μs max VREF = 10 V; settling time to ±½ LSB Digital Feedthrough3 50 50 nV sec typ Code transition all 0s to all 1s Digital Crosstalk3 50 50 nV sec typ Code transition all 0s to all 1s Minimum Load Resistance 2 2 kΩ min VOUT = 10 V POWER SUPPLIES VDD Range 11.4/16.5 11.4/16.5 V min to V max For specified performance IDD 10 10 mA max Outputs unloaded; VIN = VINL or VINH ISS 9 9 mA max Outputs unloaded; VIN = VINL or VINH SWITCHING CHARACTERISTICS3, 4 t1 50 50 ns min Write pulse width t2 0 0 ns min Address to write setup time t3 0 0 ns min Address to write hold time t4 50 50 ns min Data valid to write setup time t5 0 0 ns min Data valid to write hold time t6 50 50 ns min Load DAC pulse width 1 Maximum possible reference voltage. 2 Temperature range is as follows for all versions: −40°C to +85°C. 3 Sample tested at 25°C to ensure compliance. 4 Switching characteristics apply for single-supply and dual-supply operation.

Rev. C | Page 4 of 24 SINGLE SUPPLY VDD = 15 V ± 5%; VSS = AGND = DGND = 0 V; VREFx = 10 V , unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter K, B Versions1 L, C Versions1 Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error2 ±2 ±1 LSB max Differential Nonlinearity2 ±1 ±1 LSB max Guaranteed monotonic REFERENCE INPUT Voltage Range 2 to (VDD − 4) 2 to (VDD − 4) V min to V max Input Resistance 11 11 kΩ min Input Capacitance3 50 50 pF max Occurs when each DAC is loaded with all 1s Channel-to-Channel Isolation2, 3 60 60 dB min VREF = 10 V p-p sine wave at 10 kHz AC Feedthrough2, 3 −70 −70 dB max VREF = 10 V p-p sine wave at 10 kHz DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 μA max VIN = 0 V or VDD Input Capacitance3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate3 2 2 V/μs min Voltage Output Settling Time3 4 4 μs max Digital Feedthrough2, 3 10 10 nV sec typ Code transition all 0s to all 1s Digital Crosstalk2, 3 10 10 nV sec typ Code transition all 0s to all 1s Minimum Load Resistance 2 2 kΩ min VOUT = 10 V POWER SUPPLIES VDD Range 14.25/15.75 14.25/15.75 V min to V max For specified performance IDD 10 10 mA max Outputs unloaded; VIN = VINL or VINH SWITCHING CHARACTERISTICS3 t1 50 50 ns min Write pulse width t2 0 0 ns min Address to write setup time t3 0 0 ns min Address to write hold time t4 50 50 ns min Data valid to write setup time t5 0 0 ns min Data valid to write hold time t6 50 50 ns min Load DAC pulse width 1 Temperature range is as follows for all versions: −40°C to +85°C. 2 Sample tested at 25°C to ensure compliance. 3 Switching characteristics apply for single-supply and dual-supply operation.

Rev. C | Page 5 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VDD to AGND −0.3 V, +17 V VDD to DGND −0.3 V, +17 V VDD to VSS −0.3 V, +24 V AGND to DGND −0.3 V, VDD Digital Input Voltage to DGND −0.3 V, VDD + 0.3 V VREFx to AGND −0.3 V, VDD + 0.3 V VOUTx to AGND1 VSS, VDD Power Dissipation (Any Package) to 75°C 500 mW Derates Above 75°C by 2.0 mW/°C Operating Temperature Commercial (K, L Versions) −40°C to +85°C Industrial (B, C Versions) −40°C to +85°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C

1 Outputs can be shorted to any voltage in the range VSS to VDD provided that

the power dissipation of the package is not exceeded. Typical short-circuit current for a short to AGND or VSS is 50 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. PDIP, SOIC, CERDIP, and SSOP Figure 3. PLCC Table 4. Pin Function Descriptions 1 2 VOUTB DAC Channel B Voltage Output. 2 3 VOUTA DAC Channel A Voltage Output. 3 4 VSS Negative Power Supply Connection. 4 5 VREFB Reference Voltage Connection for DAC Channel B. 5 6 VREFA Reference Voltage Connection for DAC Channel A. 6 7 AGND Analog Ground Reference Connection. 7 9 DGND Digital Ground Reference Connection. 8 10 LDAC Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC. 9 11 DB7 Data Bit 7 (Most Significant Data Bit). 16 19 DB0 Data Bit 0 (Least Significant Data Bit). 17 20 WR Active Low Data Write Signal. Input register data is latched on the rising edge of WR. 18 21 A1 DAC Address Select Pin. 19 23 A0 DAC Address Select Pin. 20 24 VREFD Reference Voltage Connection for DAC Channel D. 21 25 VREFC Reference Voltage Connection for DAC Channel C. 22 26 VDD Positive Power Supply Connection. 23 27 VOUTD DAC Channel D Voltage Output. 24 28 VOUTC DAC Channel C Voltage Output. N/A 1, 8, 15, 22 NC No Internal Connection.

Rev. C | Page 8 of 24 TERMINOLOGY Total Unadjusted Error Tot a l unadjusted error is a comprehensive specification that includes full-scale error, relative accuracy, and zero code error. Maximum output voltage is VREF − 1 LSB (ideal), where 1 LSB (ideal) is VREF/256. The LSB size varies over the VREF range. Therefore, the zero code error, relative to the LSB size, increases as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, also varies in terms of LSB over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of 10 V. Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero code error and full-scale error and is normally expressed in LSB or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum over the operating temperature range ensures monotonicity. Digital Feedthrough Digital feedthrough is the glitch impulse transferred to the output of the DAC due to a change in its digital input code. It is specified in nV sec and is measured at V REF = 0 V. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. It is specified in nV sec and is measured at VREF = 0 V. AC Feedthrough AC feedthrough is the proportion of reference input signal that appears at the output of a converter when that DAC is loaded with all 0s. Channel-to-Channel Isolation Channel-to-channel isolation is the proportion of input signal from the reference of one DAC (loaded with all 1s) that appears at the output of one of the other three DACs (loaded with all 0s) The figure given is the worst case for the three other outputs and is expressed as a ratio in dB. Full-Scale Error Full-scale error is defined as FSE = Measured Value − Zero Code Error − Ideal Value

Rev. C | Page 12 of 24 SPECIFICATION RANGES For the AD7225 to operate to rated specifications, its input reference voltage must be at least 4 V below the VDD power supply voltage. This voltage differential is the overhead voltage required by the output amplifiers. The AD7225 is specified to operate over a VDD range from 12 V ± 5% to 15 V ± 10% (that is, from 11.4 V to 16.5 V) with a VSS of −5 V ± 10%. Operation is also specified for a single 15 V ± 5% VDD supply. Applying a VSS of −5 V results in improved zero- code error, improved output sink capability with outputs near AGND, and improved negative-going settling time. Performance is specified over a wide range of reference voltages from 2 V to (V DD − 4 V) with dual supplies. This allows a range of standard reference generators to be used, such as the AD780, a 2.5 V band gap reference, and the AD584, a precision 10 V reference. Note that an output voltage range of 0 V to 10 V requires a nominal 15 V ± 5% power supply voltage.

operation is shown in Table 7. Figure 16. Unipolar Output Circuit Table 7. Unipolar Code Table

128 REF

*DIGITAL INPUTS OMITTED FOR CLARITY. Figure 18. AGND Bias Circuit of the AD7225 should be referenced to DGND.

bandwidth figure for small signal inputs is 800 kHz. *DIGITAL INPUTS OMITTED FOR CLARITY. Figure 19. Applying an AC Signal to the AD7225

of the transversal filter (see Figure 23). words in DAC Latch A and DAC Latch B, respectively. If DA = DB = D, the result is D2 × VREFA. complex waveforms. Figure 24 shows one such application. *DIGITAL INPUTS OMITTED FOR CLARITY. Figure 24. Complex Waveform Generation

ment over the commercial operating temperature range. Figure 29. VSS Generation Circuit

0.05 MIN

0.65 BSC

2.00 MAX

Figure 34. 24-Lead Shrink Small Outline Package [SSOP] 1 To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet.

Rev. C | Page 24 of 24 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00986-0-3/10(C)