AD7224KRZ-18 AD | Alldatasheet
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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC2MOS 8-Bit DAC with Output Amplifiers AD7224 Tel: 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAM
FEATURES
8-Bit CMOS DAC with Output Amplifiers Operates with Single or Dual Supplies Low Total Unadjusted Error: Less Than 1 LSB Over Temperature Extended Temperature Range Operation mP-Compatible with Double Buffered Inputs Standard 18-Pin DIPs, and 20-Terminal Surface Mount Package and SOIC Package PRODUCT HIGHLIGHTS 1. DAC and Amplifier on CMOS Chip The single-chip design of the 8-bit DAC and output amplifier is inherently more reliable than multi-chip designs. CMOS fabrication means low power consumption (35 mW typical with single supply). 2. Low Total Unadjusted Error The fabrication of the AD7224 on Analog Devices Linear Compatible CMOS (LC 2MOS) process coupled with a novel DAC switch-pair arrangement, enables an excellent total un- adjusted error of less than 1 LSB over the full operating tem- perature range. 3. Single or Dual Supply Operation The voltage-mode configuration of the AD7224 allows opera- tion from a single power supply rail. The part can also be op- erated with dual supplies giving enhanced performance for some parameters. 4. Versatile Interface Logic The high speed logic allows direct interfacing to most micro- processors. Additionally, the double buffered interface en- ables simultaneous update of the AD7224 in multiple DAC systems. The part also features a zero override function. GENERAL DESCRIPTION The AD7224 is a precision 8-bit voltage-output, digital-to- analog converter, with output amplifier and double buffered interface logic on a monolithic CMOS chip. No external trims are required to achieve full specified performance for the part. The double buffered interface logic consists of two 8-bit regis- ters–an input register and a DAC register. Only the data held in the DAC registers determines the analog output of the con- verter. The double buffering allows simultaneous update in a system containing multiple AD7224s. Both registers may be made transparent under control of three external lines, CS, WR and LDAC. With both registers transparent, the RESET line functions like a zero override; a useful function for system cali- bration cycles. All logic inputs are TTL and CMOS (5 V) level compatible and the control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from +2 V to +12.5 V when using dual supplies. The part is also specified for single supply operation using a reference of +10 V. The output amplifier is capable of developing +10 V across a 2 kΩ load. The AD7224 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC 2MOS) process which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip.
REV. B–2– AD7224–SPECIFICATIONS (VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; V REF = +2 V to (VDD – 4 V)1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)DUAL SUPPLY K, B, T L, C, U Parameter Versions 2 Versions2 Units Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error ± 2 ± 1 LSB max V DD = +15 V ± 5%, VREF = +10 V Relative Accuracy ± 1 ± 1/2 LSB max Differential Nonlinearity ± 1 ± 1 LSB max Guaranteed Monotonic Full-Scale Error ± 3/2 ± 1 LSB max Full-Scale Temperature Coefficient ± 20 ± 20 ppm/ °C max V DD = 14 V to 16.5 V, V REF = +10 V Zero Code Error ± 30 ± 20 mV max Zero Code Error Temperature Coefficient ± 50 ± 30 µV/°C typ REFERENCE INPUT Voltage Range 2 to (V DD – 4) 2 to (V DD – 4) V min to V max Input Resistance 8 8 k Ω min Input Capacitance 3 100 100 pF max Occurs when DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.8 0.8 V max Input Leakage Current ± 1 ± 1 µA max V IN = 0 V or VDD Input Capacitance 3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 3 2.5 2.5 V/ µs min Voltage Output Settling Time 3 Positive Full-Scale Change 5 5 µs max V REF = +10 V; Settling Time to ± 1/2 LSB Negative Full-Scale Change 7 7 µs max V REF = +10 V; Settling Time to ± 1/2 LSB Digital Feedthrough 50 50 nV secs typ V REF = 0 V Minimum Load Resistance 2 2 k Ω min V OUT = +10 V POWER SUPPLIES VDD Range 11.4/16.5 11.4/16.5 V min/V max For Specified Performance VSS Range 4.5/5.5 4.5/5.5 V min/V max For Specified Performance IDD @ 25°C 4 4 mA max Outputs Unloaded; V IN = VINL or VINH TMIN to TMAX 6 6 mA max Outputs Unloaded; V IN = VINL or VINH ISS @ 25°C 3 3 mA max Outputs Unloaded; V IN = VINL or VINH TMIN to TMAX 5 5 mA max Outputs Unloaded; V IN = VINL or VINH SWITCHING CHARACTERISTICS 3, 4 @ 25°C 90 90 ns min Chip Select/Load DAC Pulse Width TMIN to TMAX 90 90 ns min @ 25°C 90 90 ns min Write/Reset Pulse Width TMIN to TMAX 90 90 ns min @ 25°C 0 0 ns min Chip Select/Load DAC to Write Setup Time TMIN to TMAX 0 0 ns min @ 25°C 0 0 ns min Chip Select/Load DAC to Write Hold Time TMIN to TMAX 0 0 ns min @ 25°C 90 90 ns min Data Valid to Write Setup Time TMIN to TMAX 90 90 ns min @ 25°C 10 10 ns min Data Valid to Write Hold Time TMIN to TMAX 10 10 ns min NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: K, L Versions: –40 °C to +85°C B, C Versions: –40 °C to +85°C T, U Versions: –55 °C to +125 °C 3Sample Tested at 25 °C by Product Assurance to ensure compliance. 4Switching characteristics apply for single and dual supply operation. Specifications subject to change without notice.
REV. B –3– SINGLE SUPPLY K, B, T L, C, U Parameter Versions 2 Versions2 Units Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error ± 2 ± 2 LSB max Differential Nonlinearity ± 1 ± 1 LSB max Guaranteed Monotonic REFERENCE INPUT Input Resistance 8 8 k Ω min Input Capacitance 3 100 100 pF max Occurs when DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.8 0.8 V max Input Leakage Current ± 1 ± 1 µA max V IN = 0 V or VDD Input Capacitance 3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 4 22V / µs min Voltage Output Settling Time 4 Positive Full-Scale Change 5 5 µs max Settling Time to ± 1/2 LSB Negative Full-Scale Change 20 20 µs max Settling Time to ± 1/2 LSB Digital Feedthrough 3 50 50 nV secs typ V REF = 0 V Minimum Load Resistance 2 2 k Ω min V OUT = +10 V POWER SUPPLIES VDD Range 14.25/15.75 14.25/15.75 V min/V max For Specified Performance IDD @ 25°C 4 4 mA max Outputs Unloaded; V IN = VINL or VINH TMIN to TMAX 6 6 mA max Outputs Unloaded; V IN = VINL or VINH SWITCHING CHARACTERISTICS 3, 4 @ 25°C 90 90 ns min Chip Select/Load DAC Pulse Width TMIN to TMAX 90 90 ns min @ 25°C 90 90 ns min Write/Reset Pulse Width TMIN to TMAX 90 90 ns min @ 25°C 0 0 ns min Chip Select/Load DAC to Write Setup Time TMIN to TMAX 0 0 ns min @ 25°C 0 0 ns min Chip Select/Load DAC to Write Hold Time TMIN to TMAX 0 0 ns min @ 25°C 90 90 ns min Data Valid to Write Setup Time TMIN to TMAX 90 90 ns min @ 25°C 10 10 ns min Data Valid to Write Hold Time TMIN to TMAX 10 10 ns min NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: AD7224KN, LN: 0 °C to +70 °C AD7224BQ, CQ: –25 °C to +85°C AD7224TD, UD: –55 °C to +125 °C 3See Terminology. 4Sample tested at 25 °C by Product Assurance to ensure compliance. Specifications subject to change without notice. (VDD = +15 V 6 5%; VSS = AGND = DGND = O V; V REF = +10 V1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
REV. B–4– ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2The outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA. ORDERING GUIDE Total Temperature Unadjusted Package Model1 Range Error (LSB) Option 2 AD7224KN –40 °C to +85°C ± 2 max N-18 AD7224LN –40 °C to +85°C ± 1 max N-18 AD7224KP –40 °C to +85°C ± 2 max P-20A AD7224LP –40 °C to +85°C ± 1 max P-20A AD7224KR-1 –40 °C to +85°C ± 2 max R-20 AD7224LR-1 –40 °C to +85°C ± 1 max R-20 AD7224KR-18 –40 °C to +85°C ± 2 max R-18 AD7224LR-18 –40 °C to +85°C ± 1 max R-18 AD7224BQ –40 °C to +85°C ± 2 max Q-18 AD7224CQ –40 °C to +85°C ± 1 max Q-18 AD7224TQ –55 °C to +125°C ± 2 max Q-18 AD7224UQ –55 °C to +125°C ± 1 max Q-18 AD7224TE –55 °C to +125°C ± 2 max E-20A AD7224UE –55 °C to +125°C ± 1 max E-20A NOTES 1To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7224 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS DIP and SOIC (SOIC) (SOIC) VSS VOUT VDD RESET DGND (MSB) DB7 DB6 DB0 (LSB) DB1 VREF AGND LDAC DB5 DB2 DB4 DB3 CS WR 81 1 91 0 TOP VIEW (Not to Scale) AD7224 VSS VOUT VDD RESET DGND (MSB) DB7 DB6 DB0 (LSB) DB1 VREF AGND LDAC DB5 DB2 DB4 DB3 CS WR 81 1 9 10 TOP VIEW (Not to Scale) AD7224 R-18 NC = NO CONNECT VSS VOUT VDD RESET DGND (MSB) DB7 DB6 CS DB0 (LSB) DB1 VREF AGND LDAC WR DB5 DB2 DB4 DB3 NC NC 8 13 9 12 10 11 TOP VIEW (Not to Scale) AD7224 R-20 LCCC PLCC NC = NO CONNECT VREF AGND DB6 DGND (MSB) DB7 VOUT VSS RESET NC VDD DB5 DB4 DB2 NC DB3 LDAC WR DB1 CS DB0 (LSB) 193 122 0 12 1391 110 TOP VIEW (Not to Scale) AD7224 NC = NO CONNECT VREF AGND DB6 DGND (MSB) DB7 VOUT VSS RESET NC VDD DB5 DB4 DB2 NC DB3 LDAC WR DB1 CS DB0 (LSB) 1931 2 20 12 139 1110 TOP VIEW (Not to Scale) AD7224
H = High State, L = Low State, X = Don’t Care. All control inputs are level triggered.
0 V on the AD7224 output and is also useful, when used as a
input control logic for the AD7224. Figure 3. Input Control Logic
- ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V DD .
- TIMING MEASUREMENT REFERENCE LEVEL IS
Figure 4. Write Cycle Timing Diagram age must be at least 4 V below the V DD power supply voltage. voltages for the DAC switches. DGND pins (IN914 or equivalent). operation is shown in Table II. Figure 5. Unipolar Output Circuit
Figure 6. Bipolar Output Circuit DAC register and can vary from 0 to 255/256. Figure 7. AGND Bias Circuit Figure 8. AD7224 to 8085A/8088 Interface
6502 ADDRESS
Figure 9. AD7224 to 6809/6502 Interface Figure 10. AD7224 to Z-80 Interface Figure 11. AD7224 to 68008 Interface
REV. B–8– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C836a–10–10/84PRINTED IN U.S.A. 18-Pin Plastic (Suffix N) 18-Pin Ceramic (Suffix D) P-20A 0.048 (1.21) 0.042 (1.07) 0.356 (9.04) 0.350 (8.89)SQ 0.395 (10.02) 0.385 (9.78)SQ 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) BSC 0.020 (0.50) R 19 3 TOP VIEW PIN 1 IDENTIFIER 0.110 (2.79) 0.085 (2.16) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.015 (0.38) 0.040 (1.01) 0.025 (0.64) 0.180 (4.57) 0.165 (4.19) 0.330 (8.38) 0.290 (7.37) E-20A 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) 0.100 (2.54) 0.342 (8.69) SQ 0.075 (1.91) REF 0.075 (1.91) REF 0.011 (0.28) 0.007 (0.18) R TYP BOTTOM VIEW 0.015 (0.38) MIN 13 9 0.028 (0.71) 0.022 (0.56) 0.095 (2.41) 0.075 (1.90) 0.200 (5.08) BSC 0.100 (2.54) BSC 0.055 (1.40) 0.045 (1.14) 45° TYP0.150 (3.81) BSC 0.050 (1.27) BSC 18-Pin Cerdip (Suffix Q) 18-Lead SOIC (R-18) PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 18 10 0.4625 (11.75) 0.4469 (11.35) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 20-Lead SOIC (R-20) PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 20 11 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 0.5118 (13.00) 0.4961 (12.60) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35)