AD7124-4TRUZ-EP-R7

AD7124-4-EP AD | Alldatasheet

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4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Enhanced Product AD7124-4-EP Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator and temperature sensor On-chip bias voltage generator Low-side power switch Multiple filter options Sensor burnout detection Automatic channel sequencer Per channel configuration Power-down current: 5 μA maximum 24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request

APPLICATIONS

Σ-∆ ADC X-MUX REFIN1(+) AVDD AVSS REFOUT AVDD AVSS PSW VARIABLE DIGITAL FILTER DIAGNOSTICS COMMUNICATIONS POWER SUPPLY SIGNAL CHAIN DIGITAL REFIN1(–) REFIN2(+) REFIN2(–) BURNOUT DETECT EXCITATION CURRENTSPOWER SWITCH GPOs CHANNEL SEQUENCER CROSSPOINT MUX REGCAP AAVDD 1.9V LDO DIAGNOSTICS AV DD AVSS AVSS DOUT/RDY CS 1.8V LDO ANALOG BUFFERS REFERENCE BUFFERS BUF BUF PGA2PGA1 AIN0/IOUT/VBIAS AIN1/IOUT/VBIAS AIN2/IOUT/VBIAS/P1 AIN3/IOUT/VBIAS/P2 AIN4/IOUT/VBIAS AIN5/IOUT/VBIAS AIN6/IOUT/VBIAS/REFIN2(+) AIN7/IOUT/VBIAS/REFIN2(–) 20190-001 Figure 1.

AD7124-4-EP Enhanced Product Rev. 0 | Page 2 of 17 TABLE OF CONTENTS

REVISION HISTORY

4/2019—Revision 0: Initial Version

Enhanced Product AD7124-4-EP Rev. 0 | Page 3 of 17 GENERAL DESCRIPTION The AD7124-4-EP is a low power, low noise, completely integrated analog front end for high precision measurement applications. The device contains a low noise, 24-bit Σ-Δ analog- to-digital converter (ADC), and can be configured to have four differential inputs or seven single-ended or pseudo differential inputs. The on-chip low gain stage ensures that signals of small amplitude can be interfaced directly to the ADC. One of the major advantages of the AD7124-4-EP is that it gives the user the flexibility to employ one of three integrated power modes. The current consumption, range of output data rates, and rms noise can be tailored with the power mode selected. The device also offers a multitude of filter options, ensuring that the user has the highest degree of flexibility. The AD7124-4-EP can achieve simultaneous 50 Hz and 60 Hz rejection when operating at an output data rate of 25 SPS (single cycle settling), with rejection in excess of 80 dB achieved at lower output data rates. The AD7124-4-EP establishes the highest degree of signal chain integration. The device contains a precision, low noise, low drift internal band gap reference, and also accepts an external differential reference, which can be internally buffered. Other key integrated features include programmable low drift excitation current sources, burnout currents, and a bias voltage generator, which sets the common-mode voltage of a channel to AV DD/2. The low-side power switch enables the user to power down bridge sensors between conversions, ensuring the absolute minimal power consumption of the system. The device also allows the user the option of operating with either an internal clock or an external clock. The integrated channel sequencer allows several channels to be enabled simultaneously, and the AD7124-4-EP sequentially converts on each enabled channel, simplifying communication with the device. As many as 16 channels can be enabled at any time; a channel being defined as an analog input or a diagnostic such as a power supply check or a reference check. This unique feature allows diagnostics to be interleaved with conversions. The AD7124-4-EP also supports per channel configuration. The device allows eight configurations or setups. Each configuration consists of gain, filter type, output data rate, buffering, and reference source. The user can assign any of these setups on a channel by channel basis. The AD7124-4-EP also has extensive diagnostic functionality integrated as part of its comprehensive feature set. These diagnostics include a cyclic redundancy check (CRC), signal chain checks, and serial interface checks, which lead to a more robust solution. These diagnostics reduce the need for external components to implement diagnostics, resulting in reduced board space needs, reduced design cycle times, and cost savings. The failure modes effects and diagnostic analysis (FMEDA) of a typical application has shown a safe failure fraction (SFF) greater than 90% according to IEC 61508. The device operates with a single analog power supply from 2.7 V to 3.6 V or a dual 1.8 V power supply. The digital supply has a range of 1.65 V to 3.6 V . It is specified for the full military temperature range of −55°C to +125°C. The AD7124-4-EP is housed in a 24-lead TSSOP package. Note that, throughout this data sheet, multifunction pins, such as DOUT/RDY , are referred to either by the entire pin name or by a single function of the pin, for example, RDY, when only that function is relevant. Additional application and technical information can be found in the AD7124-4 data sheet.

AD7124-4-EP Enhanced Product Rev. 0 | Page 4 of 17 SPECIFICATIONS REFINx(+) = 2.5 V , REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments ADC Output Data Rate, fADC Low Power Mode 1.17 2400 SPS Mid Power Mode 2.34 4800 SPS Full Power Mode 9.38 19,200 SPS No Missing Codes2 24 Bits FS3 > 2, sinc4 filter

24 Bits FS3 > 8, sinc3 filter

RMS Noise and Update Rates Integral Nonlinearity (INL) −4 ±1 +4 ppm of FSR Gain = 1 2 −15 ±2 +15 ppm of FSR Gain > 1 4 Offset Error5 Before Calibration ±15 μV Gain = 1 to 8 200/gain μV Gain = 16 to 128 After Internal Calibration/System Calibration In order of noise Offset Error Drift vs. Temperature6 Low Power Mode 10 nV/°C Gain = 1 or gain > 16 80 nV/°C Gain = 2 to 8 40 nV/°C Gain = 16 Mid Power Mode 10 nV/°C Gain = 1 or gain > 16 40 nV/°C Gain = 2 to 8 20 nV/°C Gain = 16 Full Power Mode 10 nV/°C Gain Error5, 7 Before Internal Calibration −0.0025 +0.0025 % Gain = 1, TA = 25°C −0.3 % Gain > 1 After Internal Calibration −0.016 +0.004 +0.016 % Gain = 2 to 8, TA = 25°C ±0.025 % Gain = 16 to 128 After System Calibration In order of noise Gain Error Drift vs. Temperature 1 2 ppm/°C Power Supply Rejection AIN = 1 V/gain, external reference Low Power Mode 87 dB Gain = 2 to 16 96 dB Gain = 1 or gain > 16 Mid Power Mode2 92 dB Gain = 2 to 16 100 dB Gain = 1 or gain > 16 Full Power Mode 99 dB Common-Mode Rejection8 At DC2 85 90 dB AIN = 1 V, gain = 1 105 115 dB AIN = 1 V/gain, gain 2 or 4 102 9, 2 dB A IN = 1 V/gain, gain 2 or 4 115 120 dB AIN = 1 V/gain, gain ≥ 8 105 9, 2 dB A IN = 1 V/gain, gain ≥ 8 Sinc3, Sinc4 Filter2 At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz

Enhanced Product AD7124-4-EP Rev. 0 | Page 5 of 17 Parameter1 Min Typ Max Unit Test Conditions/Comments Fast Settling Filters2 At 50 Hz 115 dB First notch at 50 Hz, 50 Hz ± 1 Hz At 60 Hz 115 dB First notch at 60 Hz, 60 Hz ± 1 Hz Post Filters2 At 50 Hz, 60 Hz 130 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 130 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Normal Mode Rejection2 Sinc4 Filter External Clock At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 80 dB 50 SPS, REJ60 10=1, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz

At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 98 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 66 dB 50 SPS, REJ60 10 = 1, 50 Hz ± 1 Hz, At 50 Hz 92 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 92 dB 60 SPS, 60 Hz ± 1 Hz Sinc3 Filter External Clock At 50 Hz, 60 Hz 100 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 65 dB 50 SPS, REJ60 10 = 1, 50 Hz ± 1 Hz, At 50 Hz 100 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 100 dB 60 SPS, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 73 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 52 dB 50 SPS, REJ60 10 = 1, 50 Hz ± 1 Hz, At 50 Hz 68 dB 50 SPS, 50 Hz ± 1 Hz At 60 Hz 68 dB 60 SPS, 60 Hz ± 1 Hz Fast Settling Filters External Clock At 50 Hz 40 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz At 60 Hz 40 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz Internal Clock At 50 Hz 24.5 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz At 60 Hz 24.5 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz Post Filters External Clock At 50 Hz, 60 Hz 86 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 62 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Internal Clock At 50 Hz, 60 Hz 67 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

AD7124-4-EP Enhanced Product Rev. 0 | Page 6 of 17 Parameter1 Min Typ Max Unit Test Conditions/Comments ANALOG INPUTS11 Differential Input Voltage Ranges12 ±V REF/gain V V REF = REFINx(+) − REFINx(−), or internal reference Absolute AIN Voltage Limits2 Gain = 1 (Unbuffered) AVSS − 0.05 AVDD + 0.05 V Gain = 1 (Buffered) AVSS + 0.1 AVDD − 0.1 V Gain > 1 AVSS − 0.05 AVDD + 0.05 V Analog Input Current Gain > 1 or Gain = 1 (Buffered) Low Power Mode Absolute Input Current ±1 nA Differential Input Current ±0.2 nA Analog Input Current Drift 25 pA/°C Mid Power Mode Absolute Input Current ±1.2 nA Differential Input Current ±0.4 nA Analog Input Current Drift 25 pA/°C Full Power Mode Absolute Input Current ±3.3 nA Differential Input Current ±1.5 nA Analog Input Current Drift 25 pA/°C Gain = 1 (Unbuffered) Current varies with input voltage Absolute Input Current ±2.65 μA/V Analog Input Current Drift 1.1 nA/V/°C REFERENCE INPUT Internal Reference Drift 2 10 ppm/°C Output Current 10 mA Load Regulation 50 μV/mA Power Supply Rejection 85 dB External Reference External REFIN Voltage2 0.5 2.5 AV DD V REFIN = REFINx(+) − REFINx(−) Absolute REFIN Voltage Limits2 AV SS − 0.05 AVDD + 0.05 V Unbuffered AV SS + 0.1 AVDD − 0.1 V Buffered Reference Input Current Buffered Low Power Mode Absolute Input Current ±0.5 nA Reference Input Current Drift 10 pA/°C Mid Power Mode Absolute Input Current ±1 nA Reference Input Current Drift 10 pA/°C Full Power Mode Absolute Input Current ±3 nA Reference Input Current Drift 10 pA/°C Unbuffered Absolute Input Current ±12 μA Reference Input Current Drift 6 nA/°C Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB

Enhanced Product AD7124-4-EP Rev. 0 | Page 7 of 17 Parameter1 Min Typ Max Unit Test Conditions/Comments EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Available on any analog input pin Output Current 50/100/250/ 500/750/1000 μA Initial Tolerance ±4 % TA = 25°C Drift 50 ppm/°C Current Matching ±0.5 % Matching between IOUT0 and IOUT1, VOUT = 0 V Drift Matching2 5 30 ppm/°C Line Regulation (AVDD) 2 %/V AV DD = 3 V ± 5% Load Regulation 0.2 %/V Output Compliance2 AV SS − 0.05 AVDD − 0.37 V 50 μA/100 μA/250 μA/500 μA current sources, 2% accuracy AV SS − 0.05 AVDD − 0.48 V 750 μA and 1000 μA current sources, 2% accuracy BIAS VOLTAGE (VBIAS) GENERATOR Available on any analog input pin VBIAS AVSS + (AVDD − AVSS)/2 V VBIAS Generator Start-Up Time 6.7 μs/nF Dependent on the capacitance connected to AINx TEMPERATURE SENSOR Accuracy ±0.5 °C Sensitivity 13,584 Codes/°C LOW-SIDE POWER SWITCH On Resistance (RON) 7 10 Ω Allowable Current2 30 mA Continuous current BURNOUT CURRENTS AIN Current 0.5/2/4 μA Analog inputs must be buffered DIGITAL OUTPUTS (P1 AND P2) Output Voltage High, VOH AV DD − 0.6 V ISOURCE = 100 μA Low, VOL 0.4 V ISINK = 100 μA DIAGNOSTICS Power Supply Monitor Detect Level Analog Low Dropout Regulator (ALDO) 1.6 V AVDD − AVSS ≥ 2.7 V Digital LDO (DLDO) 1.55 V IOVDD ≥ 1.75 V Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V AINM/AINP Overvoltage Detect Level AV DD + 0.04 V AINM/AINP Undervoltage Detect Level AVSS − 0.04 V INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 614.4 − 5% 614.4 614.4 + 5% kHz Duty Cycle 50:50 % External Clock Frequency 2.4576 MHz Internal divide by 4 Duty Cycle Range 45:55 to 55:45 % LOGIC INPUTS2 Input Voltage Low, VINL 0.3 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.35 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V High, VINH 0.7 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.65 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 1.7 V 2.3 V ≤ IOVDD < 2.7 V 2 V 2.7 V ≤ IOVDD ≤ 3.6 V Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V Input Currents −1 +1 μA V IN = IOVDD or GND Input Capacitance 10 pF All digital inputs

AD7124-4-EP Enhanced Product Rev. 0 | Page 8 of 17 Parameter1 Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (INCLUDING CLK) Output Voltage2 High, VOH IOVDD − 0.35 V I SOURCE = 100 μA Low, VOL 0.4 V ISINK = 100 μA Floating State Leakage Current −1 +1 μA Floating State Output Capacitance 10 pF Data Output Coding Offset binary SYSTEM CALIBRATION2 Calibration Limit Full Scale (FS) 1.05 × FS V Zero Scale −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER SUPPLY VOLTAGES FOR ALL POWER MODES AVDD to AVSS Low Power Mode 2.7 3.6 V Mid Power Mode 2.7 3.6 V Full Power Mode 2.9 3.6 V IOVDD to GND 1.65 3.6 V AVSS to GND −1.8 0 V IOVDD to AVSS 5.4 V POWER SUPPLY CURRENTS11, 13 IAVDD, External Reference Low Power Mode Gain = 12 125 140 μA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 15 25 μA Gain = 2 to 8 205 250 μA Gain = 16 to 128 235 300 μA IAVDD Increase per Reference Buffer2 10 20 μA All gains Mid Power Mode Gain = 12 150 170 μA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 30 40 μA Gain = 2 to 8 275 345 μA Gain = 16 to 128 330 430 μA IAVDD Increase per Reference Buffer2 20 30 μA All gains Full Power Mode Gain = 12 315 350 μA All buffers off Gain = 1 IAVDD Increase per AINx Buffer2 90 135 μA Gain = 2 to 8 660 830 μA Gain = 16 to 128 875 1200 μA IAVDD Increase per Reference Buffer2 85 120 μA All gains IAVDD Increase Due to Internal Reference2 50 70 μA Independent of power mode; the reference buffers are not required when using this reference Due to VBIAS2 15 20 μA Independent of power mode Due to Diagnostics2 4 5 μA IIOVDD Low Power Mode 20 35 μA Mid Power Mode 25 40 μA Full Power Mode 55 80 μA

Enhanced Product AD7124-4-EP Rev. 0 | Page 9 of 17 Parameter1 Min Typ Max Unit Test Conditions/Comments POWER-DOWN CURRENTS13 Independent of power mode Standby Current IAVDD 7 15 μA LDOs on only IIOVDD 8 20 μA Power-Down Current IAVDD 1 3 μA IIOVDD 1 2 μA 1 Temperature range = −55°C to +125°C. 2 These specifications are not production tested but are supported by characterization data at the initial product release. 3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers. 4 The integral nonlinearity is production tested in full power mode only. For other power modes, the specification is supported by characterization data at the initial product release. 5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 6 Recalibration at any temperature removes these errors. 7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C. 10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and 60 Hz rejection. 11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1. 12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode when gain > 1. 13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.

TA = 25°C, unless otherwise noted. PCB thermal design is required. resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 3. Thermal Resistance

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board. See JEDEC JESD51.

Figure 2. Pin Configuration Table 4. Pin Function Descriptions identifying the appropriate register. with the information being transmitted to or from the ADC in smaller batches of data. driven from a common clock, allowing simultaneous conversions to be performed. ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device. 5 REGCAPD Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 μF capacitor. interface can operate at 1.65 V with AVDD at 3.6 V, for example. 7 DGND Digital Ground Reference Point. input. Alternatively, the internal programmable excitation current source can be made available at this pin. supply rails can be generated at this pin. input. Alternatively, the internal programmable excitation current source can be made available at this pin. supply rails can be generated at this pin. as a general-purpose output bit, referenced between AVSS and AVDD.

AD7124-4-EP Enhanced Product Rev. 0 | Page 12 of 17 Pin No. Mnemonic Description 11 AIN3/IOUT/VBIAS/P2 Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured as a general-purpose output bit, referenced between AVSS and AVDD. 12 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) − REFIN1(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD. 13 REFIN1(−) Negative Reference Input. This reference input can be anywhere between AVSS and AVDD – 0.5 V. 14 AIN4/IOUT/VBIAS Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. 15 AIN5/IOUT/VBIAS Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin.

16 AIN6/IOUT/VBIAS/

REFIN2(+) Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as a positive reference input for REFIN2(±). REFIN2(+) can be anywhere between AV DD and AVSS + 0.5 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

17 AIN7/IOUT/VBIAS/

REFIN2(−) Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as the negative reference input for REFIN2(±). This reference input can be anywhere between AV SS and AVDD – 0.5 V. 18 REFOUT Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin. 19 AV SS Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power mode. AVSS can be taken below 0 V to provide a dual power supply to the AD7124-4-EP . For example, AVSS can be tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V supply to the ADC. 20 REGCAPA Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 μF capacitor. 21 PSW Low-Side Power Switch to AVSS. 22 AV DD Analog Supply Voltage, Relative to AVSS. 23 SYNC Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog modulators when using a number of AD7124-4-EP devices. When SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. 24 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.

15 UNITS

Figure 3. Input Referred Offset Error vs. Temperature (Gain = 8, Full Power Mode) Figure 4. Input Referred Offset Error vs. Temperature (Gain = 8, Mid Power Mode) Figure 5. Input Referred Offset Error vs. Temperature (Gain = 8, Low Power Mode) Figure 6. Input Referred Offset Error vs. Temperature (Gain = 16, Full Power Mode) Figure 7. Input Referred Offset Error vs. Temperature (Gain = 16, Mid Power Mode) Figure 8. Input Referred Offset Error vs. Temperature (Gain = 16, Low Power Mode)

Figure 9. Input Referred Offset Error vs. Temperature (Gain = 1, Analog Input Figure 10. Input Referred Gain Error vs. Temperature (Gain = 1) Figure 11. Input Referred Gain Error vs. Temperature (Gain = 8) Figure 12. Input Referred Gain Error vs. Temperature (Gain = 16) Figure 13. Internal Reference Voltage vs. Temperature Figure 14. Excitation Current Drift (500 μA)

Figure 15. Excitation Current Drift Matching (500 μA) Figure 16. Analog Current vs. Temperature (Full Power Mode) Figure 17. Analog Current vs. Temperature (Mid Power Mode) Figure 18. Analog Current vs. Temperature (Low Power Mode)

Figure 19. Digital Current vs. Temperature

6 UNITS

Figure 20. Temperature Sensor Accuracy Figure 21. Internal Oscillator Error vs. Temperature

6.40 BSC

0.10 COPLANARITY

Figure 22. 24-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the prop erty of their respective owners.