AD7112 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC2MOS LOGDAC Dual Logarithmic D/A Converter AD7112* Tel: 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAM 17-BIT DAC AAD7112 OUT A AGNDDGNDCS WR 17-BIT LATCH 1717-BIT LATCH 17-BIT DAC B R FB A OUT B R FB B DECODE LOGIC VIN B VIN A DAC A/ DAC B CONTROL LOGIC 8-BIT BUFFER DB0 DB7 VDD
FEATURES
Dynamic Range: 88.5 dB Resolution: 0.375 dB On-Chip Data Latches for Both DACs Four-Quadrant Multiplication +5 V Operation Pin Compatible with AD7528 Low Power
APPLICATIONS
The LOGDAC® AD7112 is a monolithic dual multiplying D/A converter featuring wide dynamic range and excellent DAC-to- DAC matching. Both DACs can attenuate an analog input sig- nal over the range 0 dB to 88.5 dB in 0.375 dB steps. It is available in skinny 0.3" wide 20-pin DIPs and in 20-terminal surface mount packages. The degree of attenuation in either channel is determined by the 8-bit word applied to the onboard decode logic. This 8-bit word is decoded into a 17-bit word which is then loaded into one of the 17-bit data latches, determined by DACA/DACB. The fine step resolution over the entire dynamic range is due to the use of these 17-bit DACs. The AD7112 is easily interfaced to a standard 8-bit MPU bus via an 8-bit data port and standard microprocessor control lines. It should be noted that the AD7112 is exactly pin-compatible with the AD7528, an industry standard dual 8-bit multiplying DAC. This allows an easy upgrading of existing AD7528 de- signs which would benefit both from the wider dynamic range and the finer step resolution offered by the AD7112. The AD7112 is fabricated in Linear Compatible CMOS (LC 2MOS), an advanced, mixed technology process that com- bines precision bipolar circuits with low power CMOS logic. *Protected by U.S. Patent No. 4521764. LOGDAC is a registered trademark of Analog Devices, Inc. PRODUCT HIGHLIGHTS 1. DAC-to-DAC Matching: Since both of the AD7112 DACs are fabricated at the same time on the same chip, precise matching and tracking between the two DACs is inherent. 2. Small Package: The AD7112 is available in a 20-pin DIP and a 20-terminal SOIC package. 3. Fast Microprocessor Interface: The AD7112 has bus inter- face timing compatible with all modern microprocessors.
REV. 0–2– AD7112–SPECIFICATIONS (VDD = +5 V 6 5%; OUT A = OUT B = AGND = DGND = 0 V; V IN A = VIN B = 10 V. Output amplifier AD712 except where noted. All specifications T MIN to TMAX unless otherwise noted.) C Version1 B Version TA =T A =T A =T A = Parameter +25 8CT MIN, TMAX +258CT MIN, TMAX Units Conditions/Comments ACCURACY Resolution 0.375 0.375 0.375 0.375 dB Accuracy Relative to Guaranteed Attenuation 0 dB Attenuation Ranges for Specified Step Sizes. 0.375 dB Steps: Accuracy ≤ ± 0.17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min Monotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min 0.75 dB Steps: Accuracy ≤ ± 0.35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min Monotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1.5 dB Steps: Accuracy ≤ ± 0.7 dB 0 to 54 0 to 48 0 to 48 0 to 42 dB min Monotonic Full Range 0 to 78 0 to 85.5 0 to 72 dB min Full Range Is 0 dB to 88.5 dB. 3.0 dB Steps: Accuracy ≤ ± 1.4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min Monotonic Full Range Full Range Full Range Full Range dB min 6.0 dB Steps: Accuracy ≤ ± 2.7 dB 0 to 72 0 to 60 0 to 60 0 to 60 dB min Monotonic Full Range Full Range Full Range Full Range dB min Gain Error ± 0.1 ± 0.15 ± 0.15 ± 0.2 dB max Measured Using R FB A, RFB B. Both DAC Registers Loaded With All 0s. Output Leakage Current OUT A, OUT B ± 50 ± 400 ± 50 ± 400 nA max Input Resistance, VIN A, VIN B 9/15 9/15 9/15 9/15 k Ω min/max Typically 12 k Ω . Input Resistance Match ± 1 ± 1 ± 2 ± 2 % max Feedback Resistance, LOGIC INPUTS CS, WR, DAC A/DAC B, DB0–DB7 Input Low Voltage, V INL 0.8 0.8 0.8 0.8 V max Input High Voltage, V INH 2.4 2.4 2.4 2.4 V min Input Leakage Current ± 1 ± 10 ± 1 ± 10 µA max Input Capacitance2 10 10 10 10 pF max POWER REQUIREMENTS 2 2 2 2 mA max Logic Inputs = V IL or VIH 2 2 2 2 mA max Logic Inputs = 0 V or V DD NOTES lTemperature range as follows: B, C Versions: –40 °C to +85°C. 2Guaranteed by design, not production tested. 3The part will function with V DD = 5 V ± 10% with degraded performance. Specifications subject to change without notice.
REV. 0 –3– TIMING SPECIFICATIONS1 Parameter T A = +258CT A = –408C to +858C Units Conditions/Comments CS to WR Setup Time t CS 0 0 ns min See Figure 3. CS to WR Hold Time t CH 0 0 ns min DAC Select to WR Setup Time t AS 4 4 ns min DAC Select to WR Hold Time t AH 0 0 ns min Data Valid to WR Setup Time t DS 55 55 ns min Data Valid to WR Hold Time t DH 10 10 ns min WR Pulse Width t WR 53 53 ns min NOTES 1Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS1 TA = TA = –40 8C to Parameter +25 8C +85 8C Units Conditions/Comments DC Supply Rejection Δ Gain/Δ VDD 0.001 0.005 dB/% max Δ VDD = ± 5%. Input Code = 00000000 Digital-to-Analog Glitch Impulse 10 10 nV s typ Measured with AD843 as output amplifier for input code transition 10000000 to 00000000. Output Capacitance, COUT A, COUT B 50 50 pF max AC Feedthrough VIN A to OUT A –94 –90 dB max V IN A, VIN B = 6 V rms at 1 kHz. DAC Registers loaded with all 1s. VIN B to OUT B –94 –90 dB max Channel-to-Channel Isolation VIN A to OUT B –87 –87 dB typ V IN A = 6 V rms at 10 kHz sine wave, VIN B = 0 V. DAC Registers loaded with all 0s. VIN B to OUT A –87 –87 dB typ V IN B = 6 V rms at 10 kHz sine wave, VIN A = 0 V. DAC Registers loaded with all 0s. Digital Feedthrough 1 1 nV s typ Me asured with input code transitions of all 0s to all 1s. Output Noise Voltage Density (30 Hz to 50 kHz) 15 15 nV/ √Hz typ Measured between R FB A and OUT A or between RFB B and OUT B. Total Harmonic Distortion –91 –91 dB typ V IN A = VIN B = 6 V rms at 1 kHz. DAC Registers loaded with all 0s. NOTES 1Guaranteed by design, not production tested. Specifications subject to change without notice. (VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = O V; V IN A = VIN B = 10 V) (VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = 0 V; V IN A = VIN B = 10 V. Output amplifier AD712 except where noted.)
REV. 0–4– ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range Lead Temperature (Soldering) *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7112 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TERMINOLOGY RESOLUTION: Nominal change in attenuation when moving between two adjacent codes. MONOTONICITY: The device is monotonic if the analog out- put decreases or remains constant as the wdigital code in- creases. FEEDTHROUGH ERROR: That portion of the input signal which reaches the output when all digital inputs are high. OUTPUT CAPACITANCE: Capacitance from OUT A or OUT B to ground. GAIN ERROR: Gain error results from a mismatch between RFB (the feedback resistance) and the R-2R ladder resistance. Its effect in a LOGDAC is to produce a constant additive at- tenuation error in dB over the whole range of the DAC. ACCURACY: The difference (measured in dB) between the ideal transfer function as listed in Table I and the actual trans- fer function as measured with the device. DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending on whether the glitch is measured as a current or voltage signal. Glitch im- pulse is measured with V IN = AGND.
ORDERING INFORMATION
Temperature Accuracy Package Model Range Range Option* AD7112BN –40 °C to +85°C 0 dB to 60 dB N-20 AD7112CN –40 °C to +85°C 0 dB to 72 dB N-20 AD7112BR –40 °C to +85°C 0 dB to 60 dB R-20 AD7112CR –40 °C to +85°C 0 dB to 72 dB R-20 *N = Plastic DIP; R = SOIC. PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1 AGND Analog Ground. 2 OUT A Current Output Terminal of DAC A. 3R FB A Feedback Resistor for DAC A. 4V IN A Reference Input to DAC A 5 DGND Digital Ground.
6 DAC A/ Selects Which DAC Can Accept Data from
DAC B Input Port. 7–14 DB7–DB0 8 Data Inputs. 15 CS Chip Select Input, Active Low. 16 WR Write Input, Active Low. 17 V DD Power Supply Input 5 V ± 5%. 18 V IN B Reference Input to DAC B. 19 R FB B Feedback Resistor for DAC B. 20 OUT B Current Output Terminal of DAC B. PIN CONFIGURATION DIP/SOIC AGND OUT A DGND (MSB) DB7 DAC A/DAC B DB6 DB5 DB4 R FB A VIN A OUT B R FB B VIN B VDD DB0 (LSB) DB1 DB2 DB3 TOP VIEW (Not to Scale) AD7112 WR CS
configuration for the AD7112. to 0 dB for all possible input codes. Figure 1. Simplified D/A Circuit of 1/2 AD7112 accuracy and monotonic ranges for all grades of the AD7112.
- ONLY ONE DAC IS SHOWN FOR CLARITY.
- DATA INPUT CONNECTIONS ARE OMITTED.
- C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN
Figure 2. Typical Circuit Configuration
1111 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
DAC. See the Mode Selection Table below. When CS and WR are both low the DAC is in the write mode. its analog output responds to activity on DB0–DB7. L = Low State, V IL; H = High State, V IH; X = Don’t Care.
- ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
- CONTROL TIMING MEASUREMENT REFERENCE LEVEL = (V IH + VIL) / 2
Figure 3. Write Cycle Timing Diagram ground (star ground) separate from the logic system ground. paths and also guards the analog circuitry from digital noise. by the characteristics of the output amplifier and not the AD7112. current vs. temperature is shown in Figure 11. maximum usable range will be affected. amplifier selection, circuit grounding, etc. of less than 10 nA be used (e.g., AD712) to minimize this offset.
REV. 0–12– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Plastic DIP (N-20) 0.280 (7.11) 0.240 (6.10) 1.060 (26.90) 0.925 (23.50) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) PIN 1 101 1120 0.210 (5.33) MAX SEATING PLANE 20-Pin SOIC (R-20) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) 0.0157 (0.40) 0.1043 (2.65) 0.0091 (0.23) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) 0.5118 (13.00) 0.4961 (12.60) 1 10 20 11 PIN 1 0°- 8° 0.0291 (0.74) 0.0098 (0.25)X 45° C1692–10–7/92PRINTED IN U.S.A.