AD7111 AD | Alldatasheet
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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC2MOS LOGDAC Logarithmic D/A Converter AD7111/AD7111A Tel: 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAMS 17-BIT DAC 17-BIT LATCH DECODE LOGIC 8-BIT BUFFER CONTROL LOGIC AD7111 IOUT AGND R FB VDD VIN DGNDCS WR D0 – D7 17-BIT DAC 17-BIT LATCH DECODE LOGIC 8-BIT BUFFER CONTROL LOGIC AD7111A IOUT AGND R FB VDD VIN DGNDCS WR D0 – D7
FEATURES
Dynamic Range: 88.5 dB Resolution: 0.375 dB On-Chip Data Latches +5 V Operation AD7111A Pin Compatible with AD7524 Low Power
APPLICATIONS
Digitally Controlled AGC System GENERAL DESCRIPTION The LOGDAC AD7111/AD7111A are monolithic multiplying D/A converters featuring wide dynamic range in a small pack- age. Both DACs can attenuate an analog input signal over the range 0 dB to 88.5 dB in 0.375 dB steps. They are available in 16-pin DIPs and SOIC packages. The AD7111 is also available in a 20-terminal LCCC package. The degree of attenuation across the DAC is determined by an 8-bit word applied to the onboard decode logic. This 8-bit word is decoded into a 17-bit word which is then applied to a 17-bit R-2R ladder. The very fine step resolution, which is available over the entire dynamic range, is due to the use of this 17-bit DAC. The AD7111/AD7111A are easily interfaced to a standard 8-bit MPU bus via an 8-bit data port and standard microprocessor control lines. The AD7111 WR input is edge triggered and re- quires a rising edge to load new data to the DAC. The AD7111A WR is level triggered to allow transparent operation of the latches, if required. It should also be noted that the AD7111A is exactly pin and function-compatible with the AD7524, an in- dustry standard 8-bit multiplying DAC. This allows an easy up- grading of existing AD7524 designs which would benefit both from the wider dynamic range and the finer step resolution of- fered by the AD7111A. The AD7111/AD7111A are fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. LOGDAC is a registered trademark of Analog Devices, Inc. PRODUCT HIGHLIGHTS 1. Wide Dynamic Range: 0 dB to 88.5 dB attenuation range in 0.375 dB steps. 2. Small Package: The AD7111/AD7111A are available in 16-pin DIPs and SOIC packages. 3. Transparent Latch Operation: By tying the CS and WR in- puts low, the DAC latches in the AD7111A can be made transparent. 4. Fast Microprocessor Interface: Data setup times of 25 ns and write pulse width of 57 ns make the AD7111A compatible with modern microprocessors.
AD7111L/C/U Grades AD7111K/B/T Grades Parameter T A = +258CT A = TMIN, TMAX TA = +258CT A = TMIN, TMAX Units Conditions/Comments NOMINAL RESOLUTION 0.375 0.375 0.375 0.375 dB ACCURACY RELATIVE TO 0 dB ATTENUATION 0.375 dB Steps: Accuracy ≤ ± 0.17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min Guaranteed Attenuation Ranges Monotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min for Specified Step Sizes 0.75 dB Steps: Accuracy ≤ ± 0.35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min Monotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1.5 dB Steps: Accuracy ≤ ± 0.7 dB 0 to 54 0 to 48 0 to 42 0 to 42 dB min Full Range Is from 0 dB Monotonic Full Range 0 to 78 0 to 85.5 0 to 72 dB min to 88.5 dB 3.0 dB Steps: Accuracy ≤ ± 1.4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min Monotonic Full Range Full Range Full Range Full Range dB min 6.0 dB Steps: Accuracy ≤ ± 2.7 dB 0 to 72 0 to 60 0 to 60 0 to 48 dB min Monotonic Full Range Full Range Full Range Full Range dB min GAIN ERROR ± 0.1 ± 0.15 ± 0.15 ± 0.20 dB max VIN INPUT RESISTANCE 9/11/15 9/11/15 7/11/18 7/11/18 k Ω min/typ/max DIGITAL INPUTS VIH (Input High Voltage) 2.4 2.4 2.4 2.4 V min VIL (Input Low Voltage) 0.8 0.8 0.8 0.8 V max Input Leakage Current ± 1 ± 10 ± 1 ± 10 µA max Digital Inputs = V DD SWITCHING CHARACTERISTICS 1 tCS 0 0 0 0 ns min Chip Select to Write Setup Time tCH 0 0 0 0 ns min Chip Select to Write Hold Time tWR 350 500 350 500 ns min Write Pulse Width tDS 175 250 175 250 ns min Data Valid to Write Setup Time tDH 10 10 10 10 ns min Data Valid to Write Hold Time tRFSH 3 4.5 3 4.5 µs min Refresh Time POWER SUPPLY VDD +5 +5 +5 +5 V IDD 1 4 1 4 mA max Digital Inputs = V IL or VIH 500 1000 500 1000 µA max Digital Inputs = 0 V or V DD; See Figure 6 NOTE 1Sample tested at +25 °C to ensure compliance. Specifications subject to change without notice. AD7111–ELECTRICAL CHARACTERISTICS REV. 0–2– AD7111/AD7111A–SPECIFICATIONS (VDD = +5 V, VIN = –10 V dc, I OUT = AGND = DGND = O V output amplifier AD711 except where noted) AC PERFORMANCE CHARACTERISTICSThese characteristics are included for design guidance only and are not subject to test. VDD = +5 V, VIN = –10 V dc except where noted, I OUT = AGND = DGND = O V, output amplifier AD711 except where noted. AD7111L/C/U Grades AD7111K/B/T Grades Parameter T A = +258CT A = TMIN, TMAX TA = +258CT A = TMIN, TMAX Units Conditions/Comments DC Supply Rejection, ΔGain/ΔVDD 0.001 0.005 0.001 0.005 dB per % max ΔVDD = ± 10%, Input Code = 00000000 Propagation Delay 3.0 4.5 3.0 4.5 µs max Full-Scale Change Measured from WR Going High, CS = 0 V Digital-to-Analog Glitch Impulse 100 100 nV secs typ Measured with AD843 as Output Amplifier for Code Transition 10000000 to 00000000 C1 of Figure 1 is 0 pF Output Capacitance, Pin 1 185 185 185 185 pF max Input Capacitance, Pin 15 and Pin 16 7 7 7 7 pF max Feedthrough at 1 kHz –94 –72 –94 –68 dB max Total Harmonic Distortion –91 –91 –91 –91 dB typ V IN = 6 V rms at 1 kHz Output Noise Voltage Density 70 70 70 70 nV/ √Hz max Includes AD711 Amplifier Noise Digital Input Capacitance 7 7 7 7 pF max Specifications subject to change without notice.
REV. 0 –3– AD7111A–ELECTRICAL CHARACTERISTICS AD7111AC Grade AD7111AB Grade Parameter T A = +258CT A = TMIN, TMAX TA = +258CT A = TMIN, TMAX Units Conditions/Comments NOMINAL RESOLUTION 0.375 0.375 0.375 0.375 dB ACCURACY RELATIVE TO 0 dB ATTENUATION 0.375 dB Steps: Accuracy ≤ ± 0.17 dB 0 to 36 0 to 36 0 to 30 0 to 30 dB min Guaranteed Attenuation Ranges Monotonic 0 to 54 0 to 54 0 to 48 0 to 48 dB min for Specified Step Sizes 0.75 dB Steps: Accuracy ≤ ± 0.35 dB 0 to 48 0 to 42 0 to 42 0 to 36 dB min Monotonic 0 to 72 0 to 66 0 to 72 0 to 60 dB min 1.5 dB Steps: Accuracy ≤ ± 0.7 dB 0 to 54 0 to 48 0 to 48 0 to 42 dB min Full Range Is from 0 dB Monotonic Full Range 0 to 78 0 to 85.5 0 to 72 dB min to 88.5 dB 3.0 dB Steps: Accuracy ≤ ± 1.4 dB 0 to 66 0 to 54 0 to 60 0 to 48 dB min Monotonic Full Range Full Range Full Range Full Range dB min 6.0 dB Steps: Accuracy ≤ ± 2.7 dB 0 to 72 0 to 60 0 to 60 0 to 48 dB min Monotonic Full Range Full Range Full Range Full Range dB min GAIN ERROR ± 0.1 ± 0.15 ± 0.15 ± 0.20 dB max VIN INPUT RESISTANCE 9/11/15 9/11/15 7/11/18 7/11/18 k Ω min/typ/max DIGITAL INPUTS VIH (Input High Voltage) 2.4 2.4 2.4 2.4 V min VIL (Input High Voltage) 0.8 0.8 0.8 0.8 V max Input Leakage Current ± 1 ± 10 ± 1 ± 10 µA max Digital Inputs = V DD SWITCHING CHARACTERISTICS 1 tCS 0 0 0 0 ns min Chip Select to Write Setup Time tCH 0 0 0 0 ns min Chip Select to Write Hold Time tWR 57 57 57 57 ns min Write Pulse Width tDS 25 25 25 25 ns min Data Valid to Write Setup Time tDH 10 10 10 10 ns min Data Valid to Write Hold Time POWER SUPPLY VDD +5 +5 +5 +5 V Digital Inputs = V IL or VIH IDD 1 2 1 2 mA max CS = WR = 0 V 1 1 1 1 mA max Digital Inputs = 0 V or V DD; See Figure 6 NOTE 1Sample tested at +25 °C to ensure compliance. Specifications subject to change without notice. (VDD = +5 V, VIN = –10 V dc, I OUT = AGND = DGND = O V output amplifier AD711 except where noted) AC PERFORMANCE CHARACTERISTICSThese characteristics are included for design guidance only and are not subject to test. VDD = +5 V, VIN = –10 V dc except where noted, I OUT = AGND = DGND = O V, output amplifier AD711 except where noted. AD7111AC Grade AD7111AB Grade Parameter T A = +258CT A = TMIN, TMAX TA = +258CT A = TMIN, TMAX Units Conditions/Comments DC Supply Rejection, ΔGain/ΔVDD 0.001 0.005 0.001 0.005 dB per % max Δ VDD = ± 10%, Input Code = 00000000 Propagation Delay 1 1.5 1 1.5 µs max Full-Scale Change Measured from WR Going High, CS = 0 V Digital-to-Analog Glitch Impulse 10 20 10 20 nV secs typ Measured with AD843 as Output Amplifier for Code Transition 10000000 to 00000000 C1 of Figure 1 is 0 pF Output Capacitance, Pin 1 50 50 50 50 pF max Input Capacitance, Pin 15 and Pin 16 7 7 7 7 pF max Feedthrough at 1 kHz –94 –90 –92 –90 dB max Total Harmonic Distortion –91 –91 –91 –91 dB typ V IN = 6 V rms at 1 kHz Output Noise Voltage Density 70 70 70 70 nV/ √Hz max Includes AD711 Amplifier Noise Digital Input Capacitance 7 7 7 7 pF max Specifications subject to change without notice.
REV. 0–4– ORDERING GUIDES AD7111A ORDERING GUIDE Specified Temperature Accuracy Package Model Range Range Option 1 AD7111ABN –40 °C to +85°C 0 dB to 60 dB N-16 AD7111ACN –40 °C to +85°C 0 dB to 72 dB N-16 AD7111ABR –40 °C to +85°C 0 dB to 60 dB R-16 AD7111ACR –40 °C to +85°C 0 dB to 72 dB R-16 NOTE 1N = Plastic DIP; R = SOIC. Operating Temperature Range *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Lead Temperature (Soldering) WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7111/AD7111A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ACCURACY: The difference (measured in dB) between the ideal transfer function as listed in Table I and the actual transfer function as measured with the device. OUTPUT CAPACITANCE: Capacitance from I OUT to ground. DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with V IN = AGND. PROPAGATION DELAY: This is a measure of the internal delays of the circuit and is defined as the time from a digital in- put change to the analog output current reaching 90% of its final value. AD7111 ORDERING GUIDE Specified Temperature Accuracy Package Modell Range Range Option 2 AD7111KN 0 °C to +70°C 0 dB to 60 dB N-16 AD7111BQ –40 °C to +85°C 0 dB to 60 dB Q-16 AD7111LN 0 °C to +70°C 0 dB to 72 dB N-16 AD7111CQ –40 °C to +85°C 0 dB to 72 dB Q-16 AD7111UQ/883B –55 °C to +125°C 0 dB to 72 dB Q-16 AD7111TE/883B –55 °C to +125°C 0 dB to 60 dB E-20A NOTES 1To order MIL-STD-883B, Class B processed parts, add /883B to part number. Contact local sales office for military data sheet and availability. 2N = Plastic DIP; Q = Cerdip; E = LCCC; R = SOIC. TERMINOLOGY RESOLUTION: Nominal change in attenuation when moving between two adjacent codes. MONOTONICITY: The device is monotonic if the analog out- put decreases (or remains constant) as the digital code increases. FEEDTHROUGH ERROR: That portion of the input signal which reaches the output when all digital inputs are high. See section on Applications. OUTPUT LEAKAGE CURRENT: Current which appears on the I OUT terminal with all digital inputs high. TOTAL HARMONIC DISTORTION: A measure of the harmonics introduced by the circuit when a pure sinusoid is applied to the input. It is expressed as the harmonic energy divided by the fundamental energy at the output.
transparent operation of the latches if required. 0 dB for all possible input codes. Figure 1. Typical Circuit Configuration tonic behavior depends upon the attenuation step size used.