AD71028

AD71028 Dual Digital BTSC Encoder with Integrated DAC Data Sheet (REV. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

2 complete independent BTSC encoders Pilot tone generator Includes subcarrier modulation Typical 23 dB to 27 dB separation, 16 dB minimum Signal bandwidth of 14 kHz Phat-StereoTM algorithm for stereo image enhancement Dialog enhancement function for playing wide dynamic range video sources over built-in TV speakers Includes L-R dual-band compressor SPI® port for control of modes and effects Differential output for optimum performance DAC performance: 92 dB dynamic range, –92 dB THD+N Output level control for setting aural carrier deviation Flexible serial data port with right-justified, left-justified, I 2S compatible, and DSP serial port modes 48-lead LQFP plastic package

APPLICATIONS

Digital set-top box BTSC encoder PRODUCT OVERVIEW The AD71028 dual digital BTSC encoder provides two complete digital BTSC encoder channels, including the pilot-tone generation and subcarrier mixing functions. Two built-in high performance DACs are provided to output the BTSC baseband composite signal. The output of the AD71028 can be connected with minimal external circuitry to the input of a 4.5 MHz aural FM modulator. In addition to the BTSC encoders, the AD71028 also includes a stereo image enhancement function, Phat Stereo, to increase the sense of spaciousness available from closely spaced TV loudspeakers. A dialog enhancement algorithm is also included to solve the problem of playing wide dynamic range sources over limited-performance TV speakers and amplifiers. An extensive SPI port allows click-free parameter updates. The AD71028 also includes ADI’s patented multibit Σ-∆ DAC architecture. This architecture provides 92 dB SNR and THD+N of –92 dB. FUNCTIONAL BLOCK DIAGRAM SERIAL INPUT A SERIAL INPUT B SPI I/O GROUP SPI PORT PLL DIVIDERS PLL DIVIDERS SERIAL INPUT CLOCK DOUBLER CLOCK DOUBLER SERIAL INPUT CONTROL REGISTERS PARAMETER RAM BTSC ENCODER CORE A BTSC ENCODER CORE B BTSC ENCODED OUTPUT A BTSC ENCODED OUTPUT B ANALOG BIAS CLOCK SIGNAL GROUP DAC DAC BIAS 04482-0-001 AD71028 Figure 1. Functional Block Diagram

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED Supply Voltages (AVDD, DVDD) 5.0 V Ambient Temperature 25°C Input Clock 12.288 MHz Input Signal 1 kHz, 0 dBFS Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 14 kHz Word Width 24 Bits Load Capacitance 50 pF Input Voltage HI 2.4 V Input Voltage LO 0.4 V DAC ANALOG PERFORMANCE Table 1. Parameter Min Typ Max Unit Resolution 24 Bits Dynamic Range (20 Hz to 14 kHz, –60 dB Input) (Encoded Output, Left = Right) 85 92 1 dB Total Harmonic Distortion + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz) VIN = 0 dB –85 –92 1 dB Differential Output Range (± Full Scale, Left = Right) 1.7 V p-p 1Measurement of encoded BTSC signal, not a measurement of end-to-end system. BTSC ENCODER PERFORMANCE Table 2. Parameter Min Typ Max Unit Channel Separation1

30 Hz to 500 Hz 27 dB

500 Hz to 5 kHz 23 dB

5 kHz to 13.5 kHz 16 dB Frequency Response1 30 Hz to 10 kHz +0.5 –1.0 dB 30 Hz to 13.5 kHz +0.5 –1.5 dB 1These specifications are measured with a –25 dB, 1 kHz input signal. DIGITAL I/O Table 3. Parameter Min Typ Max Unit Input Voltage HI (VIH) 2.1 V Input Voltage LO (VIL) 0.8 V Input Leakage (IIH @ VIH = 2.4 V) 10 µA Input Leakage (IIL @ VIL = 0.8 V) 10 µA High Level Output Voltage (VOH) IOH = 2 mA DVDD – 0.5 V Low Level Output Voltage (VOL) IOL = 2 mA 0.4 V

Rev. 0 | Page 4 of 20 POWER Table 4. Parameter Min Typ Max Unit Supplies Voltage, Analog and Digital 4.5 5 5.5 V Analog Current 31 37 mA Digital Current 97 110 mA Dissipation Operation—Both Supplies 640 mW Operation—Analog Supplies 155 mW Operation—Digital Supplies 485 mW TEMPERATURE RANGE Table 5. Parameter Min Typ Max Unit Specifications Guaranteed 25 °C Functionality Guaranteed 0 70 °C Storage –55 +125 °C DIGITAL TIMING Table 6. Parameter Min Typ Max Unit tDMD MCLK Recommended Duty Cycle @ 12.288 MHz (256 × fS and 512 × fS Modes) 40 60 % tDBL BCLK Low Pulse Width 25 ns tDBH BCLK High Pulse Width 10 ns tDLS LRCLK Setup 0 ns tDLH LRCLK Hold 10 ns tDDS SDATA Setup 0 ns tDDH SDATA Hold 10 ns tCCL CCLK Low Pulse Width 10 ns tCCH CCLK High Pulse Width 10 ns tCLS CLATCH Setup 10 ns tCLH CLATCH Hold 20 ns tCLD CLATCH High Pulse Width 10 ns tCDS CDATA Setup 0 ns tCDH CDATA Hold 10 ns tRLP Reset LO Pulse Width 10 ns

Table 7. AD71028 Stress Ratings Table 8. Package Characteristics (48-Lead LQFP) degradation or loss of functionality.

Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP) Table 9. Pin Function Descriptions

1 DIV2_PA OUT CLK27_PA clock (Pin 40) Divided by 1125

2 DIV1_PB OUT PLL_PB Clock (Pin 46) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)

3 DIV2_PB OUT CLK27_PB Clock (Pin 41) Divided by 1125

8 ODVDD Digital Supply for Output Buffers

11 COUT OUT SPI Readback

12 CDATA IN SPI Control Data Input

14 CCLK IN SPI Serial Bit Clock

15 CLATCH IN SPI Control Latch Signal

18 RESETB IN Reset Signal fo r Both Processors, Active Low

19 SDATA_PA IN Data In put to Processor A

20 BCLK_PA IN Bit Clock Signal for Serial Data Input to Processor A

21 LRCLK_PA IN Left/Right Framing Sign al for Data Input to Processor A

22 SDATA_PB IN Data Input to Processor B

23 BCLK_PB IN Bit Clock Signal for Serial Data Input to Processor B

24 LRCLK_PB IN Left/Right Framing Sign al for Data Input to Processor B

29 OUTA– OUT Negative Analog Output, Processor A

30 OUTA+ OUT Positive Analog Output, Processor A

34 OUTB+ OUT Positive Analog Output, Processor B

35 OUTB– OUT Negative Analog Output, Processor B

37 REFCAP IN Connection Point for 10 µF VREF Filter Capacitor

38 FILTCAP IN Connection for Noise Reduction Capacitor

Rev. 0 | Page 7 of 20 Pin No. Mnemonic Input/Output Description

40 CLK27_PA IN Input for 27 MHz Video Reference Clock, Processor A

41 CLK27_PB IN Input for 27 MHz Video Reference Clock, Processor B

42 PLL_PA IN Input from External PLL, Processor A

43 MCLK_PA IN Clock Input to Processor A

46 PLL_PB IN Input from External PLL, Processor B

47 MCLK_PB IN Clock Input to Processor B

48 DIV1_PA OUT PLL_PA Clock (Pin 42) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)

Rev. 0 | Page 8 of 20 The AD71028 is comprised of two independent digital-input BTSC encoders. The two processors allow two completely asynchronous BTSC channels to be encoded, each with its own clock signals. Figure 1 shows the block diagram of the device. Signal processing parameters are stored in a 256-location parameter RAM, which is initialized on power-up by an internal boot ROM. The values stored in the parameter RAM control all the filter coefficients, mixing, and dynamics processing code used in the BTSC algorithm. The AD71028 has an SPI port that supports complete read/ write capability of the parameter RAM, as well as a control port and several other registers that allow the various signal proces- sing parameters to be controlled. The AD71028 can run as a standalone processor without SPI control. The AD71028 has a very flexible serial data input port that allows for glueless interconnection to a variety of signal sources. The AD71028 can be configured in left-justified, I2S, right- justified, or DSP serial port compatible modes. It can support 16, 20, and 24 bits in all modes. The AD71028 accepts serial audio data in MSB first, twos complement format. The AD71028 operates from a single 5 V power supply. It is fab- ricated on a single monolithic integrated circuit and is housed in a 48-lead LQFP package for operation over the 0°C to 70°C temperature range. PIN FUNCTIONS Pin names and functions are shown below. Note that pins with a “_PA ” designation are connected to Processor A, while those with a “_PB” designation are connected to Processor B. All input pins have a logic threshold compatible with TTL input levels, and may therefore be used in systems with 3.3 V logic. All digital output levels are controlled by the ODVDD pin, which may range from 2.7 V to 5.5 V , for compatibility with a wide range of external devices. LRCLK_PA, LRCLK_PB Left/right clocks for framing the input data. The interpretation of the LRCLK changes according to the serial mode, set by writing to the control registers. BCLK_PA, BCLK_PB Serial bit clocks for clocking in the serial data. The interpreta- tion of BCLK changes according to the serial mode, which is set by writing to the control registers. SDATA_PA, SDATA_PB Serial data inputs to each processor. The serial format is selected by writing to Bits <3:0> of the control registers. MCLK_PA, MCLK_PB Master clock inputs. The master clock frequency must be either 256 × f S or 512 × fS, where fS is the input sampling frequency. If the DOUBLE pin is high, an internal clock doubler is used to take a 256 × f S input clock and produce the 512 × fS internal clock required by the DSP core. If the DOUBLE pin is low, the frequency of the input clock must be set to 512 × f S. In case these clock signals are not available, a simple external PLL may be used to generate the master clock signals. On-chip dividers are provided to simplify this task. CDATA Serial data in for the SPI control port. See the SPI Port section for more information on SPI port timing. COUT Serial data output. This is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. See the SPI Port section for more information on SPI port timing. CCLK SPI bit-rate clock. This pin may either run continuously or be gated in between SPI transactions. See the SPI Port section for more information on SPI port timing. CLATCH SPI latch signal. This signal must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. Detailed SPI timing informa- tion can be found in the SPI Port section. RESETB Active-low reset signal. After RESETB transitions from low to high, the AD71028 goes through an initialization sequence where the parameter RAMs are initialized with the contents of the on-board boot ROM. All SPI registers are set to 0, and the data RAMs are also zeroed. The initialization is complete after 1024 MCLK cycles. New values should not be written to the SPI port until the initialization is complete. DOUBLE When this pin is set high, the internal clock doubler is turned on so a 256 × fS MCLK can be input to the AD71028. PLL_PA, PLL_PB PLL clock input pins for Processor A and Processor B. These pins are connected to an internal divide-by-1024 circuit (or divide-by-512 if DOUBLE is high). This makes it possible to use an inexpensive external PLL to generate the system clock. If an external PLL is used, this pin should also be connected to the appropriate MCLK_PA or MCLK_PB pin.

Rev. 0 | Page 9 of 20 CLK27_PA, CLK27_PB Input pins to the divide-by-1125 block. If an external PLL is used to generate the audio master clock, the 27 MHz video master clock may be applied to these pins where it is divided by 1125 to produce a 24 kHz feedback clock to the external PLL phase detector. DIV1_PA, DIV1_PB Output of divide-by-1024 circuit. Divides the master clock signal by 1024 (or 512 when DOUBLE is asserted). Used to interface to external PLL. DIV2_PA, DIV2_PB Output of divide-by-1125 circuit. Divides the master-clock signal by 1125. Used to interface to external PLL. The output signal is a pulse with a duration of one master clock, and should therefore be used with edge-triggered phase detectors. REFCAP Analog reference voltage input. The nominal REFCAP input voltage is 2.5 V; the analog gain scales directly with the voltage on this pin. Any ac signal on this pin will cause distortion, and therefore a large decoupling capacitor should be used to ensure that the voltage on REFCAP is clean. The input impedance of REFCAP is greater than 1 MΩ. FILTCAP Filter cap point. This pin is used to reduce the noise on an internal biasing point in order to provide the highest performance. It may not be necessary to connect this pin, depending on the quality of the layout and grounding used in the application circuit. DVDD Digital VDD for core. 5 V nominal. ODVDD Digital VDD for all digital outputs. Variable from 2.7 V to 5.5 V . DGND Digital ground. AVDD Analog VDD. 5 V nominal. Bypass capacitors should be placed close to the pins and connected directly to the analog ground plane. AGND Analog ground. OUTA+, OUTA– Differential analog outputs for Processor A. The nominal output voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This level may be adjusted by writing to SPI location 258. OUTB+, OUTB– Differential analog outputs for Processor B. The nominal output voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This level may be adjusted by writing to SPI location 770.

Figure 3. Signal Processing Flow frequency so that it sits above the audio band (Figure 3). “matrix”) can be used to recover the L and R signal. grammed to match these standards as accurately as possible. and the input to the FM modulator.

Figure 5. Sample of SPI Write Format (Single-Write Mode) Figure 6. Sample of SPI Read Format (Single-Read Mode) contact ADI if modifications to the BTSC filters are required. basic format, shown in Figure 5. Figure 6 shows the read format. The Wb/R bit is low for a write and high for a read operation. bytes varies according to the register or memory being accessed. operation is given in the SPI Read/Write Data Formats section. Table 11. SPI Port Address Decoding

256 SPI Control Register Processor A Write: 11 Bits, Read: N/A

257 Reserved

258 Output Level Processor A Write: 22 Bits, Read: N/A

259 Stereo Spreading Control Processor A Write: 22 Bits, Read: N/A

260 Dialog Enhancement Control Processor A Write: 22 Bits, Read: N/A

768 SPI Control Register Processor B Write: 22 Bits, Read: N/A

769 Reserved

770 Output Level Processor B Write: 22 Bits, Read: N/A

771 Stereo Spreading Control Processor B Write: 22 Bits, Read: N/A

772 Dialog Enhancement Control Processor B Write: 22 Bits, Read: N/A

Dialog Enhancement Register section of this data sheet. transfers. Table 12 documents the contents of this register. Bits 4:5 and 8:10 are reserved and should be set to 0 at all times. The audio signal is muted with Bit 7 of the control register. sumption is reduced to a low level when this bit is asserted. Reset can only be asserted using the external reset pin. Table 12. Control Register Contents

10 Reserved, Set to 0

9 Reserved, Set to 0

8 Reserved, Set to 0

7 Soft Mute (1 = Start Mute Sequence)

6 Soft Power-Down (1 = Power-Down)

The output level register controls the overall BTSC output level.

1. This register is used in conjunction

overall volume level of the audio signal. clipping on full-scale signal peaks, especially at low frequencies. passages from overloading the speakers or amplifiers.

9.00 BSC

0.08 MAX

Figure 13. 48-Lead Low Profile Quad Flatpack [LQFP]

Rev. 0 | Page 18 of 20 NOTES

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Rev. 0 | Page 20 of 20 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04482–0–1/04(0)