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REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD706 Dual Picoampere Input Current Bipolar Op Amp

FEATURES

100 /H9262V Max Offset Voltage 1.5 /H9262V//H11543C Max Offset Drift 200 pA Max Input Bias Current 0.5 /H9262V p-p Voltage Noise, 0.1 Hz to 10 Hz 750 /H9262A Supply Current Available in 8-Lead Plastic Mini-DlP and Surface-Mount (SOIC) Packages Available in Tape and Reel in Accordance with EIA-481A Standard Quad Version: AD704

APPLICATIONS

Low Frequency Active Filters Precision Instrumentation Precision Integrators CONNECTION DIAGRAM Plastic Mini-DIP (N) and Plastic SOIC (R) Packages TOP VIEW OUTPUT –IN /H11545IN V/H11545 OUTPUT –IN /H11545INV– AD7061 AMPLIFIER 1 AMPLIFIER 2 GENERAL DESCRIPTION The AD706 is a dual, low power, bipolar op amp that has the low input bias current of a JFET amplifier, but which offers a significantly lower I B drift over temperature. It utilizes superbeta bipolar input transistors to achieve picoampere input bias current levels (similar to FET input amplifiers at room temperature), while its I B typically only increases by 5 /H11003 at 125 °C (unlike a JFET amp, for which I B doubles every 10 °C for a 1000 /H11003 increase at 125 °C). The AD706 also achieves the microvolt offset voltage and low noise characteristics of a precision bipolar input amplifier. Since it has < 200 pA of bias current, the AD706 does not require the commonly used “balancing” resistor. Furthermore, the current noise is only 50 fA/ √Hz, which makes this amplifier usable with very high source impedances. At 600 /H9262A max supply current (per amplifier), the AD706 is well suited for today’s high density boards. The AD706 is an excellent choice for use in low frequency active filters in 12-bit and 14-bit data acquisition systems, in precision instrumentation, and as a high quality integrator. The AD706 is internally compensated for unity gain and is available in five performance grades. The AD706J is rated over the commercial temperature range of 0°C to +70°C. The AD706A is rated for the extended industrial temperature range of –40 °C to +85 °C. The AD706 is offered in two varieties of an 8-lead package: plastic mini-DIP and surface-mount (SOIC). PRODUCT HIGHLIGHTS 1. The AD706 is a dual low drift op amp that offers JFET level input bias currents, yet has the low I B drift of a bipolar amplifier. It may be used in circuits using dual op amps such as the LT1024. 2. The AD706 provides both low drift and high dc precision. 3. The AD706 can be used in applications where a chopper amplifier would normally be required but without the chopper’s inherent noise. TEMPERATURE – /H11543C 100

0.01 TYPICAL IB – nA

0.1 –55 +125 +25 +110 TYPICAL JFET AMP AD706 Figure 1. Input Bias Current vs. Temperature

REV. E–2– AD706–SPECIFICATIONS(@ TA = +25/H11543C, VCM = 0 V and /H1155015 V dc, unless otherwise noted.) AD706J/A Parameter Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE Initial Offset 30 100 µV Offset T MIN to TMAX 40 150 µV vs. Temperature, Average TC 0.2 1.5 µV/°C vs. Supply (PSRR) V S = ±2 V to ± 18 V 110 132 dB TMIN to TMAX VS = ±2.5 V to ±18 V 106 126 dB Long Term Stability 0.3 µV/Month INPUT BIAS CURRENT1 VCM = 0 V 50 200 pA VCM = ±13.5 V 250 pA vs. Temperature, Average TC 0.3 pA/ °C TMIN to TMAX VCM = 0 V 300 pA TMIN to TMAX VCM = ±13.5 V 400 pA INPUT OFFSET CURRENT V CM = 0 V 30 150 pA VCM = ±13.5 V 250 pA vs. Temperature, Average TC 0.6 pA/ °C TMIN to TMAX VCM = 0 V 80 250 pA TMIN to TMAX VCM = ±13.5 V 80 350 pA MATCHING CHARACTERISTICS Offset Voltage 150 µV TMIN to TMAX 250 µV Input Bias Current2 300 pA TMIN to TMAX 500 pA Common-Mode Rejection 106 dB TMIN to TMAX 106 dB Power Supply Rejection 106 dB TMIN to TMAX 104 dB Crosstalk (Figure 2a) @ f = 10 Hz RL = 2 kΩ 150 dB FREQUENCY RESPONSE Unity Gain Crossover Frequency 0.8 MHz Slew Rate G = –1 0.15 V/ µs TMIN to TMAX 0.15 V/ µs INPUT IMPEDANCE Differential 40||2 M Ω||pF Common Mode 300||2 G Ω||pF INPUT VOLTAGE RANGE Common-Mode Voltage ±13.5 ± 14 V Common-Mode Rejection Ratio V CM = ±13.5 V 110 132 dB TMIN to TMAX 108 128 dB INPUT CURRENT NOISE 0.1 Hz to 10 Hz 3 pA p-p f = 10 Hz 50 fA/ √Hz INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 0.5 µV p-p f = 10 Hz 17 nV/ √Hz f = 1 kHz 15 22 nV/ √Hz OPEN-LOOP GAIN V O = ±12 V RLOAD = 10 kΩ 200 2000 V/mV TMIN to TMAX 150 1500 V/mV VO = ±10 V RLOAD = 2 kΩ 200 1000 V/mV TMIN to TMAX 150 1000 V/mV OUTPUT CHARACTERISTICS Voltage Swing R LOAD = 10 kΩ± 13 ± 14 V TMIN to TMAX ±13 ± 14 V Current Short Circuit ± 15 mA Capacitive Load Drive Capability Gain = +1 10,000 pF

REV. E AD706 –3– SPECIFICATIONS (continued) AD706J/A Parameter Conditions Min Typ Max Unit POWER SUPPLY Rated Performance ± 15 V Operating Range ±2.0 ±18 V Quiescent Current, Total 0.75 1.2 mA TMIN to TMAX 0.8 1.4 mA TRANSISTOR COUNT Number of Transistors 90 NOTES 1Bias current specifications are guaranteed maximum at either input. 2Input bias current match is the difference between corresponding inputs (I B of –IN of Amplifier 1 minus I B of –IN of Amplifier 2). CMRR match is the difference between V V OS1 CM for Amplifier 1 and V V OS2 CM for Amplifier 2, expressed in dB. PSRR match is the difference between V V OS1 SUPPLY for Amplifier 1 and V V OS2 SUPPLY for Amplifier 2, expressed in dB. All min and max specifications are guaranteed. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Internal Power Dissipation Operating Temperature Range NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 8-Lead Plastic Package: θJA = 100°C/W 8-Lead Small Outline Package: θJA = 155°C/W 3The input pins of this amplifier are protected by back-to-back diodes. If the differential voltage exceeds ± 0.7 V, external series protection resistors should be added to limit the input current to less than 25 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD706 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Model Range Description Option AD706JN 0 °C to 70°C Plastic DIP N-8 AD706JR 0 °C to 70°C SOIC R-8 AD706JR-REEL 0 °C to 70°CT ape and Reel R-8 AD706JR-REEL7 0 °C to 70°CT ape and Reel R-8 AD706AR –40 °C to +85°C SOIC R-8 AD706AR-REEL –40 °C to +85°CT ape and Reel R-8 AD706AR-REEL7 –40 °C to +85°CT ape and Reel R-8 AD706ARZ-REEL* –40°C to +85°CT ape and Reel R-8 *Lead-free part. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. 4 5 OUTPUT A –INPUT A +INPUT A –VS 0.074 (1.88) OUTPUT B –INPUT B +INPUT B 0.118 (3.00) +VS

REV. E–4– AD706–Typical Performance Characteristics SAMPLE SIZE: 3000 INPUT OFFSET VOLTAGE – /H9262V NUMBER OF UNITS 1000 –80 –40 0 40 80 400 200 600 800 TPC 1. Typical Distribution of Input Offset Voltage SUPPLY VOLTAGE – /H11550Volts /H11545VS 0 51 0 1 5 2 0 –1.5 –1.0 –0.5 /H115451.0 /H115450.5 /H115451.5 INPUT COMMON-MODE VOLTAGE LIMIT – Volts (REFERRED TO SUPPLY VOLTAGES) –VS TPC 4. Input Common-Mode Voltage Range vs. Supply Voltage OFFSET VOLTAGE DRIFT – /H9262V//H11543C 200 120 160 SAMPLE SIZE: 375 –55/H11543C TO /H11545125/H11543C NUMBER OF UNITS TPC 7. Typical Distribution of Offset Voltage Drift INPUT BIAS CURRENT – pA NUMBER OF UNITS 1000 –160 –80 0 80 160 400 200 600 800 SAMPLE SIZE: 5100 TPC 2. Typical Distribution of Input Bias Current FREQUENCY – Hz OUTPUT VOLTAGE – Volts p-p 01k 10k 1M 100k TPC 5. Large Signal Frequency Response WARM-UP TIME – Minutes 0 123 4 1CHANGE IN OFFSET VOLTAGE – /H9262V TPC 8. Change in Input Offset Voltage vs. Warm-Up Time INPUT OFFSET CURRENT – pA NUMBER OF UNITS 1000 –120 –60 0 60 120 400 200 600 800 SAMPLE SIZE: 2400 TPC 3. Typical Distribution of Input Offset Current SOURCE RESISTANCE – /H9024 OFFSET VOLTAGE DRIFT – /H9262V//H11543C 100 0.11k 10k 100M 1.0 100k 1M 10M SOURCE RESISTANCE MAY BE EITHER BALANCED OR UNBALANCEDFOR INDUSTRIAL TEMPERATURE RANGE TPC 6. Offset Voltage Drift vs. Source Resistance COMMON-MODE VOLTAGE – Volts –60 –15 –10 –5 0 5 INPUT BIAS CURRENT – pA –20 –40 NEGATIVE IB POSITIVE IB TPC 9. Input Bias Current vs. Common-Mode Voltage (Default Conditions: /H115505 V, CL = 5 pF, G = 2, Rg = Rf = 1 kΩ, RL = 2 kΩ, VO = 2 V p-p, Frequency = 1 MHz, T A = 25/H11543C)

REV. E AD706 –5– FREQUENCY – Hz 1000 100 111 0 1000100 VOLTAGE NOISE – nV//H20906Hz TPC 10. Input Noise Voltage Spectral Density SUPPLY VOLTAGE – /H11550 Volts 1000 600 0 51 0 1 5 2 0 800 900 700QUIESCENT CURRENT – /H9262A +125/H11543C –55/H11543C +25/H11543C TPC 13. Quiescent Supply Current vs. Supply Voltage LOAD RESISTANCE – k/H9024 OPEN-LOOP VOLTAGE GAIN 10M 100k12 4 6 8 1 0 100 +125/H11543C +25/H11543C –55/H11543C TPC 16. Open-Loop Gain vs. Load Resistance vs. Load Resistance FREQUENCY – Hz 1000 100 111 0 1000100 CURRENT NOISE – fA//H20906Hz 100/H9024 10k/H9024 20M/H9024 VOUT TPC 11. Input Noise Current Spectral Density FREQUENCY – Hz 160 0.1 11 0 100 10k 120 140 100 100k CMRR – dB60 TPC 14. Common-Mode Rejection Ratio vs. Frequency FREQUENCY – Hz 140 –20 0.01 0.1 1 10 1k 100 120 10k 100 OPEN-LOOP VOLTAGE GAIN – dB 100k 10M GAIN PHASE 120 150 180 PHASE SHIFT – Degrees 210 240 TPC 17. Open-Loop Gain and Phase Shift vs. Frequency TIME – Seconds 0 5 10 0.5/H9262V TPC 12. 0.1 Hz to 10 Hz Noise Voltage FREQUENCY – Hz 180 0.1 11 0 100 10k 140 160 120 100k 100 PSRR – dB + PSRR – PSRR TPC 15. Power Supply Rejection Ratio vs. Frequency SUPPLY VOLTAGE – /H11550 Volts +VS 0 51 0 1 5 2 0 –1.5 –1.0 –0.5 +1.0 +0.5 +1.5 OUTPUT VOLTAGE SWING – Volts (REFERRED TO SUPPLY VOLTAGES) –VS TPC 18. Output Voltage Swing vs. Supply Voltage

Figure 7. 1 Hz, 4-Pole Active Filter

1 Hz, 4-Pole, Active Filter

high temperatures, as shown by Figure 8. Figure 8. VOS vs. Temperature Performance

REV. E AD706 –9– OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) /H11547 45/H11543 8/H11543 0/H11543 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122)COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) SEATING PLANE 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) BSC 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA 0.015 (0.38) MIN

REV. E–10– AD706

Revision History

10/03–Data Sheet changed from REV. D to REV. E 10/02–Data Sheet changed from REV. C to REV. D

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