AD7001

AD7001 AD | Alldatasheet

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FEATURES GENERAL DESCRIPTION Single +5 V Supply The AD7001 is a complete low power, LC?MOS, input/output Single Channel 8-Bit A/D Converter port with single +5 V power supply. The part is designed to

2.16 MHz Sampling Rate perform the conversion of I and Q signals in the transmit and

Receive Difference Amplifier receive data paths of Pan-European Digital Cellular Telephone Programmable Gain Amplifier (GSM) systems. However, the device can be used in any appli- Two 10-Bit D/A Converters cation requiring fast and accurate signal conversion in the sub- 2 MHz Throughput Rate 600 kHz band. Simultaneous Update Mode Besides providing two high accuracy 10-bit digital-to-analog 4th Order Antialias Filters converters in the transmit path and a single fast analog-to-digital Single Serial Auxiliary 8-Bit D/A Converter converter in the receive path, the part also provides antialiasing past Interface Port filters and signal conditioning functions. ‘ower Down Mode(s) A single serial 8-bit DAC is included for such functions as AFC, On-Chip Voltage Reference ‘AGC ier signal shaping in the IF/RF ion of the syst 44-Pin POFP or carrier signal shaping in the portion of ie system. All logic necessary for control of this device is contained on APPLICATIONS board. A fast data bus allows easy interface with all commonly pisital Collar Telephony available microprocessors. 'rivate Mobile Telephony ars ‘ 1 Satellite Baseband Digitization As it is a necessity for all GSM mobile systems to use the lowest 4 h possible power, the device has power down options for both the Radar Signal Processing transmit path and the receive path which are independent of Signal Generation and Acquisition each other. The AD7001 is housed in a space efficient 44-pin PQEP (Plastic Quad Flatpack). FUNCTIONAL BLOCK DIAGRAM vootx voor: TEST O—O—O restmose & me 1 — = nd ‘AUX DATA = [ian | A mc O PxA = Te tS ne axwates © [user | wz van 7: © Cae] © aonorx ‘OGND Rx © aano Ax d o—O 6—0 O O TUKOKG REF AKSTROBE GLK ODATA POWER-UPTx _POWER-UP Rr our REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties otherwise under any patent or patent rights of Analag Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD7001 — SPECIFICATIONS (op TX = Vpp Rx = +5 V + 7%; Test = AGNDTx = AGNDRx = DGNDTx = DGNDRx = 0 V; T, = Twn tO Tax, POWER-UP Tx = POWER-UP Rx = 0 V, unless otherwise noted) Parameter Units Test Conditions/Comments ADC SPECIFICATIONS POWER-UP Rx = Vpp Resolution 8 Bits Signal Input Range Vper + Vpep2 | Volts PGA =1 Vrer =Vrer/4 | Volts PGA = 2 Vaer +Vper/8 | Volts PGA = 4; All Biased on Veer Sampling Rate 2.17 MSPS. DC Accuracy Integral Nonlinearity +15 LSB max PGA = 1, 20r4 Differential Nonlinearity +15 LSB max PGA = 1, 20r4 Offset Error Tum to Tax +3 LSB max PGA = 1 Tums 0 Tmax +5 LSB max PGA = 2 Tyan to Tuax +10 LSB max PGA = 4 Full-Scale Error Positive and Negative Tranto Tax +6 LSB max PGA =1 Twn to Tax +8 LSB max PGA = 2 Tuan 10 Tax +10 LSB max PGA = 4 Input Resistance (DC) 5 kQ min Input Capacitance 20 pF typ Dynamic Specifications Vin = 500 kHz Full-Scale Sine Wave, Signal-to-Noise Ratio 40 dB min fsampte = 2.16 MHz; PGA = 1, 2 or 4 Peak Spurious Noise —40 dB max PGA = 1, 2or4 Total Harmonic Distortion —40 dB max PGA = 1, 2064 Gain Accuracy +05 dB max PGA = 1 +0.75 dB max PGA = 2 +15 dB max PGA = 4 Coding Binary Power-Down Option Yes POWER-UP Rx = 0V DIFFERENCE AMPLIFIER SPECIFICATIONS POWER-UP Rx = Vpp Differential Gain 19.5 dB min Vin = 474 kHz + 80 kHz; Biased on Varp 21.5 dB max Input Common-Mode Rejection Ratio 40 dB min RxA = RxB = 0.4 V p-p @ 500 kHz Distortion —40 dB max Vour = 1 V p-p @ 500 kHz; Biased on Vacr Input Impedance RxA to REF OUT 20/60 kQ min/‘max 40 kO Typical RxB to REF OUT 10/40 kQ min/max 25 kQ Typical RxA to RxB 3/10 kQ min/max 6.5 kQ Typical Output Offset +20 mV max At RxC When Inputs Are Floating. Power-Down Option Yes POWER-UP Rx = 0V SIGNAL DAC SPECIFICATIONS POWER-UP Rx = Vpp Resolution 10 Bits Number of Channels 2 Update Rate 2.17 MSPS DC Accuracy Integral Nonlinearity +1 LSB typ Differential Nonlinearity +1 LSB typ Output Signal Range Vaer +Vaer2 | Volts Biased on Vey; 10 k/20 pF Load Offset Error +50 mV max 10 0000 0000 Loaded to DAC Dynamic Specifications Gain Accuracy +05 dB max Measure at 66.65 kHz ITx and QTx Gain Matching +0.1 dB max Generating 66.65 kHz Sine Waves Differential Group Delay 200 ns max Measured Relative to the Absolute Group Delay at 10 kHz in the Frequency Band 10 kHz-200 kHz ITx and QTx Phase Matching +1 ° max Measured at 66.65 kHz -2- REV.A

Parameter Test Condtions/Comment GMSK Spectrum Mask Refer to Figure 1 100 kHz +0.5 dB min 200 kHz —30 dB min 250 kHz —33 dB min 400 kHz —60 dB min 600 kHz -70 dB min 1200 kHz —70 dB min >4200 kHz —60 dB min GMSK Phase Trajectory Error 0.7 ° RMS typ 1.5 ° Peak typ LP Filter Response 300 kHz -3 dB typ

1 MHz —20 dB typ

2 MHz 44 dB typ

SNR + THD (0 MHz-1.08 MHz) Producing 66.65 kHz Sine Wave with 2.17 MHz Taaw to Tax 52 dB min Updated Rate Peak Spurious Noise (0 MHz-6.5 MHz) —70 dB typ Coding Binary Power-Down Option Yes POWER-UP Tx = 0 V AUXILIARY DAC SPECIFICATIONS POWER-UP Tx = Vpp Resolution 8 Bits DC Accuracy Integral Nonlinearity” 22 LSB max Differential Nonlinearity” +1 LSB max Guaranteed Monotonic Offset Error 12541 LSB max Full-Scale Error +60 mV max Output Signal Range 0 t0 2.5 Volts Output Impedance: 2 kQ max Ig~wx = 250 pA

20 OQ typ Tsource = 250 nA

850 OQ typ Tgwx = 250 pA

Power-Down Option Yes POWER-UP Tx = 0 V REFERENCE SPECIFICATIONS Veer, Reference Output 2.4/2.6 V min/V max Reference Variation* 25 mV max LOGIC INPUTS Vine» Input High Voltage Vpp0.9 V min Vint» Input Low Voltage 0.9 V max Tin Input Current 10 pA max Cin» Input Capacitance 10 pF max LOGIC OUTPUTS Vox» Output High Voltage 4.0 V min Hour] = 200 pA Voz» Output Low Voltage 0.4 V max Hour! = 1.6 mA POWER SUPPLIES Vpp 4.65/5.35 V min/V max Ipp All Sections 62 mA max ADC and Diff Amp Active* 40 mA max POWER-UP Tx = 0V Signal DACs and AUX DAC Active® 22 mA max POWER-UP Rx = 0 V All Sections Powered Down® 2.0 mA max POWER-UP Tx = POWER-UP Rx = 0V NOTES ‘Operating temperature ranges as follows: A Version; —25°C to +85°C. AUX DAC de linearity is measured between codes 5 and 255, see terminology. ‘Variation of the Reference between different POWER-UP Tx and POWER-UP Rx modes, “Measured while the digital inputs to the transmit interface are static. ‘Measured while the digital inputs to the receive interface are static. “Measured while the digital inputs are equal to 0 V or Vpp- Specifications subject to change without notice. REV.A -3-

on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper L, .

1 Tx Section Operational, Rx Section Powered Down | 22 mA

1 All Sections Operational 62 mA

2 TO OUTPUT

250 FREQUENCY - kHz

Figure 1. AD7001 Transmit GMSK Spectrum Mask Figure 2. Load Circuit for Access Time Test

TERMINOLOGY Differential Group Delay Signal Input Range Absolute group delay is the rate of change of phase versus fre- The input signal range for Rx SIGNAL is biased about Vazy. It quency, dé/df. For the AD7001, differential group delay is the can go +Vpep/2s +Vpep/4 or =Ver/8 volts (depending on the —_ absolute group delay in a specified band relative to the absolute PGA setting) about this point. group delay at 10 kHz. The specified band for the AD7001 is Auxiliary DAC Linearity 10 kHz-200 kHz. The AUX DAC output amplifier can have an internal negative Group Delay Between Channels offset, even though the part operates from a single (5 V) supply. _ This is the difference between the group delay of the I and Q However, because the negative rail is 0 V, the output cannot channels and is a measure of the phase matching characteristics actually go below ground, resulting in the transfer function of the two. shown below. This “Knee” is an offset effect, not a linearity a error, and the transfer function would have followed the dotted ys s eae Sees nal range for the transmit channel section line if the output voltage could have gone negative. and the auxiliary DAC section. For the transmit channel the Normally, linearity is measured between zero (all 0s) and full span is +1.25 volts centered on Vpgp and for the auxiliary DAC scale (all 1s) after offset and full scale have been adjusted out, section it is 0 to + Vppr. but this is not possible with the AD7001 AUX DAC if the offset Qutput Signal Full-Scale Accuracy is negative. Instead, linearity of the AUX DAC is measured This is the accuracy of the full scale output (all 1s loaded to the between full scale and the lowest code which is guaranteed t DACs) on the transmit channel and is expressed in dBs. produce a positive output voltage. This code is calculated from the maximum specification for negative offset. For the AD7001 DAC Offset Error . . . AUX DAC the linearity is measured between codes 5 and 255. This is the amount of offset in the transmit DACs and the auxil- iary DACs and is expressed in mVs for the transmit section and in LSBs for the auxiliary section. AUXDAC Full-Scale Error This is a measure of the output error between an ideal full-scale AUXDAC output of 2.5 V and the measured output when all 1s are OuTPUT loaded. VOLTAGE Output Impedance This is a measure of the drive capability of the auxiliary DAC + output and is expressed in kQs. NEGATIVE DAC CODE GMSK Spectrum Mask OFFSET a This is the output spectrum of the I and Q transmit channels 27 when transmitting a random sequence of data bits using GMSK modulation, as specified in the GSM standard, using a bit trun- Effect of Negative Offset cation of +6 bit periods. GMSK Phase Trajectory Error Bias Offset Error ‘This is a measure of the phase error between the transmitted This is the offset error (in LSBs) in the DAC or ADC and is phase of an ideal GMSK modulator and the actual phase trans- measured with respect to Veer. mitted by the AD7001, when transmitting a random sequence of Signal-to-Noise Ratio data bits. It is specified as a peak phase error and also as a rms Signal-to-noise ratio (SNR) is the measured signal to noise at the Phase error. output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f,/2), excluding de. SNR is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. The theoretical SNR for a sine wave is given by: SNR = (6.02 N+ 1.76) dB REV.A 5.

All input signals are specified with tr= f= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. °t, is measured with the load circuit of Figure 1 and is defined as the time required for an output to cross 0.8 V or 2.4 V. true bus relinquish time of the part and as such is independent of external bus loading capacitances. Figure 3. ADC Timing Diagram

All input signal rise and fall times measured from 10% to 90% of +5 V; tr = tf = 10 ns. Figure 4. PGA Timing Diagram

t2 100 ps min POWER-UP Tx to Tx STROBE Setup Time. +All input signal rise and fall times measured from 10% to 90% of +5 V3 tr = tf = 20 ns. Figure 5. Signal DAC Timing Diagram

All input signal rise and fall times measured from 10% to 90% of +5 V; tr = tf = 20 ns. Figure 6. Auxiliary DAC Timing Diagram

‘The AD7001 auxiliary DAC is a voltage mode DAC, consisting _ a. of new serial data, this prevents the AUX DAC output from differential amplifier and the ADC channel. when loading the gueitiany ac Aux DATA is latched on the or 4 depending on the value loaded into the 2-bit PGA register. brought high to update the AUX DAC output. inthe following section. 8-bit analog to digital converter (ADC) combined with an register. Table II illustrates the truth table for the PGA setting. Figure 16. Operation of the Differential Amplifier

power has initially been applied to the part. The PGA can be other analog circuit in the in the IF section. band of 150 ns before and 300 ns after POWER-UP Rx going nected after the 100 0 series resistance. high is sufficient for correct operation. ae . . vided to allow the receive circuity to become fully powered up. Rx-STROBE can now be activated to initiate ADC conversions.

00.00 Bee

Figure 17. ADC Transfer Function eg a Rx SIGNAL, the first two conversions can be used to measure Figure 19. Typical Plot of Reference Variation vs. subtracted, by the user, from subsequent ADC conversions. switching from Vipy to the RX A and RX B input pins.

34 Vop Tx Positive Power Supply for transmit section. 22 Vpp Rx Positive Power Supply for receive section. Both Vpp pins must be tied together. 32 AGND Tx Analog Ground for transmit section. 23 AGND Rx Analog Ground for receive section. Both AGND pins must be tied together. 42 DGND Tx Digital Ground for transmit section. 13 DGND Rx Digital Ground for receive section. Both DGND pins must be tied together. ANALOG SIGNAL AND REFERENCE 28 REF OUT Reference Output, this is 2.5 V nominal. 24 Rx SIGNAL Analog Input for receive channel. 30 ITx Analog Output Voltage from the I transmit channel. This output comes from a 10-bit DAC and is filtered by a 4th order Bessel low-pass filter. 33 QTx Analog Output Voltage from the Q Transmit channel. This output comes from a 10-bit DAC and is filtered by a 4th order Bessel low-pass filter. 29 AUX DAC Analog Output Voltage from the 8-bit Auxiliary DAC. This output comes from a buffer amplifier. 27 RxA Analog Input for the inverting input of the differential amplifier. 26 RxB Analog Input for the noninverting input of the differential amplifier. 25 RxC Analog Output Voltage from the differential amplifier. TRANSMIT INTERFACE AND CONTROL 5 Tx STROBE Transmit Strobe, Digital Input. Tx STROBE transfers the contents of both the I and Q Latches, on a rising edge, to the I and Q 10-bit DACs, respectively. This is used to update both 10-bit DACs simultancously after the I and Q latches have been loaded via a single 10-bit port. 4 I DAC I Latch Update, Digital Input. I DAC is used to update the I latch via DX9-DX0. This is an edge triggered latch, DX9-DX0 are latched on the rising edge of I DAC. 3 Q DAC Q Latch Update, Digital Input. Q DAC is used to update the Q latch via DX9-DX0. This is an edge triggered latch, DX9-DX0 are latched on the rising edge of Q DAC. 2,1 DX9, DX8 Transmit Data Bit 9 and Data Bit 8, digital inputs. DX9 is the most significant bit (MSB). 44, 43 DX7, DX6 Transmit Data Bit 7 and Data Bit 6, digital inputs. 41-36 DX5-DX0 Transmit Data Bits 5 to 0, digital inputs. DX0 is the least significant bit (LSB). 7 AUX CLOCK Auxiliary Clock, edge triggered digital input. Serial data bits are latched on the rising edge AUX CLOCK when AUX LATCH is low. AUX CLOCK must be a gated clock, which is only active when data is being loaded into the serial register 6 AUX DATA Auxiliary Data, digital input. This data input is used in conjunction with AUX CLOCK and AUX LATCH to load the 8-bit Auxiliary DAC register. 8 AUX LATCH Level triggered Digital Input. AUX LATCH controls the transfer of data between the AUX DAC serial register and the AUX DAC latch. When high, the AUX DAC latch is transparent. Data is latched when AUX LATCH is brought low. 35 POWER-UP Tx Power-Up Transmit, Digital Input. When this goes low the transmit section goes into standby mode, drawing minimum current. RECEIVE INTERFACE AND CONTROL, 18 Rx STROBE Receive Strobe, Digital Input. Rx STROBE initiates an ADC conversion, at the end of which DR7-DRO are updated. 9-12 DR7-DR4 Receive Data Bits 7 to 4, Digital Outputs. DR7 is the most significant bit (MSB). 14-17 DR3-DRO Receive Data Bits 3 to 0, Digital Outputs. DRO is the least significant bit (LSB). 20 GCLK PGA Clock, Digital Input. GDATA bits are latched on the falling edge of GCLK. The PGA must be loaded using 8 GCLKs, the last two bits that are loaded are used to set the PGA. 21 GDATA Programmable Gain Data, Digital Input. This input is used in conjunction with GCLK to set the gain for the PGA. 19 POWER-UP Rx Power-Up Receive, Digital Input. When this goes low the receive section goes into standby mode, drawing minimal current. 31 TEST Test mode, Digital Input. This pin is used to put the device into a special factory test mode. For normal device operation this pin must be tied to DGND. -14— REV.A

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