AD698APZ AD | Alldatasheet
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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Universal LVDT Signal Conditioner AD698 © Analog Devices, Inc., 1995 Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
Single Chip Solution, Contains Internal Oscillator and Voltage Reference No Adjustments Required Interfaces to Half-Bridge, 4-Wire LVDT DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Unipolar or Bipolar Output Will Also Decode AC Bridge Signals Outstanding Performance Linearity: 0.05% Output Voltage: 611 V Gain Drift: 20 ppm/ 8C (typ) Offset Drift: 5 ppm/ 8C (typ) PRODUCT DESCRIPTION The AD698 is a complete, monolithic Linear Variable Differen- tial Transformer (LVDT) signal conditioning subsystem. It is used in conjunction with LVDTs to convert transducer mechan- ical position to a unipolar or bipolar dc voltage with a high de- gree of accuracy and repeatability. All circuit functions are included on the chip. With the addition of a few external passive components to set frequency and gain, the AD698 converts the raw LVDT output to a scaled dc signal. The device will operate with half-bridge LVDTs, LVDTs connected in the series op- posed configuration (4-wire), and RVDTs. The AD698 contains a low distortion sine wave oscillator to drive the LVDT primary. Two synchronous demodulation channels of the AD698 are used to detect primary and second- ary amplitude. The part divides the output of the secondary by the amplitude of the primary and multiplies by a scale factor. This eliminates scale factor errors due to drift in the amplitude of the primary drive, improving temperature performance and stability. The AD698 uses a unique ratiometric architecture to eliminate several of the disadvantages associated with traditional ap- proaches to LVDT interfacing. The benefits of this new cir- cuit are: no adjustments are necessary; temperature stability is improved; and transducer interchangeability is improved. The AD698 is available in two performance grades: Grade Temperature Range Package AD698AP –40 °C to +85°C 28-Pin PLCC AD698SQ –55 °C to +125°C 24-Pin Cerdip PRODUCT HIGHLIGHTS 1. The AD698 offers a single chip solution to LVDT signal conditioning problems. All active circuits are on the mono- lithic chip with only passive components required to com- plete the conversion from mechanical position to dc voltage. 2. The AD698 can be used with many different types of posi- tion sensors. The circuit is optimized for use with any LVDT, including half-bridge and series opposed, (4 wire) configurations. The AD698 accommodates a wide range of input and output voltages and frequencies. 3. The 20 Hz to 20 kHz excitation frequency is determined by a single external capacitor. The AD698 provides up to 24 volts rms to differentially drive the LVDT primary, and the AD698 meets its specifications with input levels as low as 100 millivolts rms. 4. Changes in oscillator amplitude with temperature will not af- fect overall circuit performance. The AD698 computes the ratio of the secondary voltage to the primary voltage to deter- mine position and direction. No adjustments are required. 5. Multiple LVDTs can be driven by a single AD698 either in series or parallel as long as power dissipation limits are not exceeded. The excitation output is thermally protected. 6. The AD698 may be used as a loop integrator in the design of simple electromechanical servo loops. 7. The sum of the transducer secondary voltages do not need to be constant. FUNCTIONAL BLOCK DIAGRAM A B AMP OSCILLATOR VOLTAGE REFERENCE A B FILTER AMP AD698
AD698–SPECIFICATIONS REV. B–2– (@ TA = +258C, VCM = 0 V, and V+, V– = 615 V dc, unless otherwise noted) AD698SQ AD698AP Parameter Min Typ Max Min Typ Max Unit TRANSFER FUNCTION1 VOUT = A B × 500 µA × R2 V OVERALL ERROR TMIN to TMAX 0.4 1.65 0.4 1.65 % of FS SIGNAL OUTPUT CHARACTERISTICS Output Voltage Range 611 611 V Output Current, TMIN to TMAX 11 11 mA Short Circuit Current 20 20 mA Nonlinearity
2 TMIN to TMAX 75 6500 75 6500 ppm of FS
Gain Error3 0.1 61.0 0.1 61.0 % of FS Gain Drift 20 6100 20 6100 ppm/°C of FS Output Offset 0.02 61 0.02 61 % of FS Offset Drift 5 625 5 625 ppm/°C of FS Excitation Voltage Rejection 4 100 100 ppm/dB Power Supply Rejection ( ± 12 V to ± 18 V) PSRR Gain 50 300 50 300 ppm/V PSRR Offset 15 100 15 100 ppm/V Common-Mode Rejection ( ± 3 V) CMRR Gain 25 100 25 100 ppm/V CMRR Offset 2 100 2 100 ppm/V Output Ripple5 4 4 mV rms EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz) Excitation Voltage Range 2.1 24 2.1 24 V rms Excitation Voltage (Resistors Are 1% Absolute Values) (R1 = Open)6 1.2 2.15 1.2 2.15 V rms (R1 = 487 Ω ) 14 21.2 14 21.2 V rms Excitation Voltage TC 7 100 100 ppm/ °C Output Current 30 50 30 50 mA rms TMIN to TMAX 40 40 mA rms Short Circuit Current 60 60 mA DC Offset Voltage (Differential, R1 = 12.7 k Ω ) TMIN to TMAX 30 6100 30 6100 mV Frequency 20 20 k 20 20 k Hz Frequency TC 200 200 ppm/ °C Total Harmonic Distortion –50 –50 dB SIGNAL INPUT CHARACTERISTICS A/B Ratio Usable Full-Scale Range 0.1 0.9 0.l 0.9 Signal Voltage B Channel 0.1 3.5 0.1 3.5 V rms Signal Voltage A Channel 0.0 3.5 0.0 3.5 V rms Input Impedance 200 200 k Ω Input Bias Current (BIN, AIN) 1 5 1 5 µA Signal Reference Bias Current 2 10 2 10 µA Excitation Frequency 0 20 k 0 20 k Hz POWER SUPPLY REQUIREMENTS Operating Range 13 36 13 36 V Dual Supply Operation ( ± 10 V Output) ± 13 ± 13 V Single Supply Operation 0 V to +10 V Output 17.5 17.5 V 0 V to 10 V Output 17.5 17.5 V Current (No Load at Signal and Excitation Outputs) 12 15 12 15 mA TMIN to TMAX 18 18 mA OPERATING TEMPERATURE RANGE –55 +125 –40 +85 °C
REV. B –3– NOTES 1A and B represent the Mean Average Deviation (MAD) of the detected sine waves V A and VB. The polarity of V OUT is affected by the sign of the A comparator, i.e., multiply VOUT × +1 for ACOMP+ > ACOMP–, and VOUT × –1 for ACOMP– > ACOMP+. 2Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage. 3See Transfer Function. 4For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm. 5Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output ripple. See Figures 7, 8 and 13. 6R1 is shown in Figures 7, 8 and 13. 7Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698. 8From TMIN to TMAX the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall error for the AD698AP from T MIN to TMAX is calculated as follows: Overall Error = Gain Error at +25 °C (± 0.2% Full Scale) + Gain Drift from –40 °C to +25°C (20 ppm/°C × 65°C) + Offset Drift from –40 °C to +25°C (5 ppm/ °C × 65°C) = ± 0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ORDERING GUIDE Model Package Description Package Option AD698AP 28-Pin PLCC P-28A AD698SQ 24-Pin Double Cerdip Q-24A CONNECTION DIAGRAMS 28-Pin PLCC 28 27 261234 12 13 14 15 16 17 18 TOP VIEW (Not to Scale) LEV1 LEV2 FREQ1 NC NC SIG REF SIG OUT FEEDBACK OUT FILT NC = NO CONNECT AD698 BFILT1 BFILT2 AFILT1 AFILT2 +ACOMP FREQ2 NC EXC2 EXC1 –VS +VS NC –BIN +BIN –AIN +AIN –ACOMP OFF1 OFF2 24-Pin Cerdip TOP VIEW (Not to Scale) AD698 –VS SIG REF OFFSET2 OFFSET1 S EXC1 EXC2 LEV1 OUT FILT FEEDBACK SIG OUTLEV2 FREQ1 FREQ2 BFILT1 BFILT2 –BIN –ACOMP AFILT2 AFILT1 +BIN –AIN +ACOMP +AIN WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD698 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS Storage Temperature Range Operating Temperature Range Power Dissipation Derates above +65 °C THERMAL CHARACTERISTICS θJC θJA P Package 30 °C/W 60 °C/W Q Package 26 °C/W 62 °C/W
transducer is used. In general follow the guidelines below. which can be implemented by adding external components. Figure 7. Interconnection Diagram for Half-Bridge LVDT Figure 7 shows the connection method for half-bridge LVDTs. amples use dual ± 15 volt power supplies. manufacturer; in this case skip to Step 4.
- Determine the mechanical bandwidth required for LVDT
ample, assume fSUBSYSTEM = 250 Hz.
- Select minimum LVDT excitation frequency approximately
10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.
- Select a suitable LVDT that will operate with an excitation
- Select excitation frequency determining component C1.
Figure 8. AD698 Interconnection Diagram for Series
3.5 V rms range when the LVDT is at its mechanical full-scale
tion is relatively unimportant.
- Determine optimum LVDT excitation voltage, V
LVDT sensitivity × Maximum Stroke Length from null.
REV. B–10– AD698 Determining LVDT Sensitivity LVDT sensitivity can be determined by measuring the LVDT secondary voltages as a function of primary drive and core posi- tion, and performing a simple computation. Energize the LVDT at its recommended primary drive level, VPRI (3 V rms for the E100). Set the core displacement to its mechanical full-scale position and measure secondary voltages VA and VB. Sensitivity = VSECONDARY VPRI × d From Figure 19, Sensitivity = 0.72 3V × 100 mils = 2.4 mV /V mil d = –100 mils d = 0 1.71V rms 0.99V rms d = +100 mils VSEC WHEN V PRI 3V rms VA VB Figure 19. LVDT Secondary Voltage vs. Core the AD698 continues to meet its output specifications.
APPLICATIONS
Most of the applications for the AD598 can also be imple- mented with the AD698. Please refer to the applications written for the AD598 for a detailed explanation. See AD598 data sheet for: – Proving Ring-Weigh Scale – Synchronous Operation of Multiple LVDTs – High Resolution Position-to-Frequency Circuit – Low Cost Setpoint Controller – Mechanical Follower Servo Loop – Differential Gaging and Precision Differential Gaging AC BRIDGE SIGNAL CONDITIONER Bridge circuits which use dc excitation are often plagued by er- rors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pickup. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously de- modulate the resulting signal. The ac phase and amplitude in- formation from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low- pass filter. The AD698 with the addition of a simple ac gain stage can be used to implement an ac bridge. Figure 20 shows the connec- tions for such a system. The AD698 oscillator provides ac excitation for the bridge. The low level bridge signal is amplified by the gain stage created by A1, A2 to provide a differential in- put to the A Channel of the AD698. The signal is then synchro- nously detected by A Channel. The B Channel is used to detect the level of the bridge excitation. The ratio of A/B is then calcu- lated and converted to an output voltage by R2. An optional phase lag/lead network can be added in front of the A compara- tor to adjust for phase delays through the bridge and the ampli- fier, or if the phase delay is small, it can be ignored or compensated for by a gain adjustment. This circuit can be used for resistive bridges such as strain gages, or for inductive or capacitive bridges that are commonly used for pressure or flow sensors. The low level signal outputs of these sensors are susceptible to noise and interference and are good candidates for ac signal processing techniques. Component Selection Amplifiers A1, A2 will be chosen depending on the type of bridge that is conditioned. Capacitive bridges should use an amplifier with low bias current; a large bleeder resistor will be required from the amplifier inputs to ground to provide a path for the dc bias current. Resistive and inductive bridges can use a more general purpose amplifier. The dc performance of A1, A2 are not as important as their ac performance. DC errors such as voltage offset will be chopped out by the AD698 since they are not synchronous to the carrier frequency. The oscillator amplitude and span resistor for the AD698 may be chosen by first computing the transfer function or sensitivity of the bridge and the ac amplifier. This ratio will correspond to the A/B term in the AD698 transfer function. For example, sup- pose that a resistive strain gage with a sensitivity, S, of 2 mV/V at full scale is used. Select an arbitrary target value for A/B that is close to its maximum value such as A/B = 0.8. Then choose a gain for the ac amplifier so that the strain gage transfer function from excitation to output also equals 0.8. Thus the required am- plifier gain will be [A/B]/ S; or 0.8/ 0.002 V/V = 400. Then select values for R S and RG. For the gain stage:
2.4 V rms, which is in the acceptable range. For a 10 V output at FS, with an A/B of 0.8; solve for R2. network on the OFFSET 1 and OFFSET 2 pins of the AD698. Figure 20. AD698 Interconnection Diagram for AC Bridge Applications
REV. B–12– AD698 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Cerdip (Wide) 0.620 (15.75) 0.590 (15.00) 0.015 (0.38) 0.008 (0.20)15° 1.280 (32.51) MAX 0.200 (5.08) MAX 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.005 (0.13) MIN PIN 1 0.098 (2.49) MAX 0.610 (15.5) 0.520 (13.2) 28-Pin PLCC 0.048 (1.21) 0.042 (1.07) 0.456 (11.58) 0.450 (11.43)SQ 0.495 (12.57) 0.485 (12.32)SQ 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) BSC 26 4 TOP VIEW PIN 1 IDENTIFIER 0.020 (0.50) R 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.430 (10.92) 0.390 (9.91) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) C1827a–5–7/95PRINTED IN U.S.A.