AD693

AD693 Loop-Powered 4-20 mA Sensor Transmitter

Document overview

• PDF pages: 12

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Loop-Powered 4–20 mA Sensor Transmitter Tel: 617/329-4700 Fax: 617/326-8703 AD693

FEATURES

Instrumentation Amplifier Front End Loop-Powered Operation Precalibrated 30 mV or 60 mV Input Spans Independently Adjustable Output Span and Zero Precalibrated Output Spans: 4–20 mA Unipolar 0–20 mA Unipolar 12 6 8 mA Bipolar Precalibrated 100 V RTD Interface 6.2 V Reference with Up to 3.5 mA of Current Available Uncommitted Auxiliary Amp for Extra Flexibility Optional External Pass Transistor to Reduce Self-Heating Errors PRODUCT DESCRIPTION The AD693 is a monolithic signal conditioning circuit which accepts low-level inputs from a variety of transducers to control a standard 4–20 mA, two-wire current loop. An on-chip voltage reference and auxiliary amplifier are provided for transducer excitation; up to 3.5 mA of excitation current is available when the device is operated in the loop-powered mode. Alternatively, the device may be locally powered for three-wire applications when 0–20 mA operation is desired. Precalibrated 30 mV and 60 mV input spans may be set by simple pin strapping. Other spans from 1 mV to 100 mV may be realized with the addition of external resistors. The auxiliary amplifier may be used in combination with on-chip voltages to provide six precalibrated ranges for 100 Ω RTDs. Output span and zero are also determined by pin strapping to obtain the standard ranges: 4–20mA, 12 ± 8 mA and 0–20 mA. Active laser trimming of the AD693’s thin-film resistors result in high levels of accuracy without the need for additional adjustments and calibration. Total unadjusted error is tested on every device to be less than 0.5% of full scale at +25 °C, and less than 0.75% over the industrial temperature range. Residual nonlinearity is under 0.05%. The AD693 also allows for the use of an external pass transistor to further reduce errors caused by self-heating. For transmission of low-level signals from RTDs, bridges and pressure transducers, the AD693 offers a cost-effective signal conditioning solution. It is recommended as a replacement for discrete designs in a variety of applications in process control, factory automation and system monitoring. The AD693 is packaged in a 20-pin ceramic side-brazed DIP, 20-pin Cerdip, and 20-pin LCCC and is specified over the –40°C to +85°C industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD693 is a complete monolithic low-level voltage-to- current loop signal conditioner. 2. Precalibrated output zero and span options include 4–20 mA, 0–20 mA, and 12 ± 8 mA in two- and three-wire configurations. 3. Simple resistor programming adds a continuum of ranges to the basic 30 mV and 60 mV input spans. 4. The common-mode range of the signal amplifier input extends from ground to near the device’s operating voltage. 5. Provision for transducer excitation includes a 6.2 V reference output and an auxiliary amplifier which may be configured for voltage or current output and signal amplification. 6. The circuit configuration permits simple linearization of bridge, RTD, and other transducer signals. 7. A monitored output is provided to drive an external pass transistor. This feature off-loads power dissipation to extend the temperature range of operation, enhance reliability, and minimize self-heating errors. 8. Laser-wafer trimming results in low unadjusted errors and affords precalibrated input and output spans. 9. Zero and span are independently adjustable and noninteractive to accommodate transducers or user defined ranges. 10. Six precalibrated temperature ranges are available with a 100 Ω RTD via pin strapping.

AD693–SPECIFICATIONS REV. A–2– (@ +258C and VS = +24 V. Input Span = 30 mV or 60 mV. Output Span = 4–20 mA, RL = 250 V, VCM = 3.1 V, with external pass transistor unless otherwise noted.) Model AD693AD/AQ/AE Conditions Min Typ Max Units LOOP-POWERED OPERATION TOTAL UNADJUSTED ERROR1, 2 ± 0.25 60.5 % Full Scale TMIN to TMAX ± 0.4 60.75 % Full Scale 100 Ω RTD CALIBRATION ERROR 3 (See Figure 17) ± 0.5 ± 2.0 °C LOOP POWERED OPERATION 2 Zero Current Error4 Zero = 4 mA ± 25 680 µA Zero = 12 mA ± 40 6120 µA Zero = 0 mA5 +7 +35 +100 µA vs. Temp. Zero = 4 mA ± 0.5 ± 1.5 µA/°C Power Supply Rejection (RTI) 12 V ≤ VOP ≤ 36V6 ± 3.0 65.6 µV/V 0 V ≤ VCM ≤ 6.2 V Common-Mode Input Range (See Figure 3) 0 +V OP – 4 V6 V Common-Mode Rejection (RTI) 0 V ≤ VCM ≤ 6.2 V ± 10 630 µV/V Input Bias Current7 +5 +20 nA TMIN to TMAX +7 +25 nA Input Offset Current7 VSIG = 0 ± 0.5 63.0 nA Transconductance Nominal 30 mV Input Span 0.5333 A/V 60 mV Input Span 0.2666 A/V Unadjusted Error ± 0.05 60.2 % vs. Common-Mode 0 V ≤ VCM ≤ 6.2 V 30 mV Input Span ± 0.03 ± 0.04 %/V 60 mV Input Span ± 0.05 ± 0.06 %/V Error vs. Temp. ± 20 ± 50 ppm/ °C Nonlinearity8 30 mV Input Span ± 0.01 60.05 % of Span 60 mV Input Span ± 0.02 60.07 % of Span OPERATIONAL VOLTAGE RANGE Operational Voltage, V OP 6 +12 +36 V Quiescent Current Into Pin 9 +500 +700 µA OUTPUT CURRENT LIMIT +21 +25 +32 mA COMPONENTS OF ERROR SIGNAL AMPLIFIER9 Input Voltage Offset ± 40 6200 µV vs. Temp ± 1.0 ± 2.5 µV/°C Power Supply Rejection 12 V ≤ VOP ≤ 36 V6 ± 3.0 65.6 µV/V 0 V ≤ VCM ≤ 6.2 V V/I CONVERTER9, 10 Zero Current Error Output Span = 4–20 mA ± 30 ± 80 µA Power Supply Rejection 12 V ≤ VOP ≤ 36 V6 ± 1.0 ± 3.0 µA/V Transconductance Nominal 0.2666 A/V Unadjusted Error ± 0.05 ± 0.2 %

6.200 V REFERENCE9, 12

Output Voltage Tolerance ± 3 612 mV vs. Temp. ± 20 ± 50 ppm/ °C Line Regulation 12 V ≤ VOP ≤ 36 V6 ± 200 6300 µV/V Load Regulation11 0 mA ≤ IREF ≤ 3 mA ± 0.3 60.75 mV/mA Output Current13 Loop Powered, (Figure 10) +3.0 +3.5 mA 3-Wire Mode, (Figure 15) +5.0 mA

Conditions Min Typ Max Units AUXILIARY AMPLIFIER Common-Mode Range 0 +V OP – 4 V6 V Input Offset Voltage ± 50 ± 200 µV Input Bias Current +5 +20 nA Input Offset Current +0.5 ± 3.0 nA Common-Mode Rejection 90 dB Power Supply Rejection 105 dB Output Current Range Pin I X OUT +0.01 +5 mA Output Current Error Pin V X – Pin IX ± 0.005 % TEMPERATURE RANGE Case Operating14 TMIN to TMAX –40 +85 °C Storage –65 +150 °C NOTES 1 Total error can be significantly reduced (typically less than 0.1%) by trimming the zero current. The remaining unadjusted error sources are transconductance and nonlinearity. 2 The AD693 is tested as a loop powered device with the signal amp, V/I converter, voltage reference, and application voltages operating together. Specifications are valid for preset spans and spans between 30 mV and 60 mV. 3 Error from ideal output assuming a perfect 100 Ω RTD at 0 and +100 °C. 4 Refer to the Error Analysis to calculate zero current error for input spans less than 30 mV. 5 By forcing the differential signal amplifier input sufficiently negative the 7 µA zero current can always be achieved. 6 The operational voltage (V OP) is the voltage directly across the AD693 (Pin 10 to 6 in two-wire mode, Pin 9 to 6 in local power mode). For example, V OP = VS – (ILOOP × RL) in two-wire mode (refer to Figure 10). 7Bias currents are not symmetrical with input signal level and flow out of the input pins. The input bias current of the inverting input increases with input signal volt- age, see Figure 2. 8 Nonlinearity is defined as the deviation of the output from a straight line connecting the endpoints as the input is swept over a 30 mV and 60 mV input span. 9 Specifications for the individual functional blocks are components of error that contribute to, and that are included in, the Loop Powered Operation specifications. 10 Includes error contributions of V/I converter and Application Voltages. 11 Changes in the reference output voltage due to load will affect the Zero Current. A 1% change in the voltage reference output will result in an error of 1% in the value of the Zero Current. 12 If not used for external excitation, the reference should be loaded by approximately 1 mA (6.2 k Ω to common). 13 In the loop powered mode up to 5 mA can be drawn from the reference, however, the lower limit of the output span will be increased accordingly. 3.5 mA is the maximum current the reference can source while still maintaining a 4 mA zero. 14 The AD693 is tested with a pass transistor so T A ≅ TC. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Package Package Model Description Option AD693AD Ceramic Side-Brazed DIP D-20 AD693AQ Cerdip Q-20 AD693AE Leadless Ceramic Chip E-20A Carrier (LCCC) AD693 PIN CONFIGURATION (AD, AQ, AE Packages) Functional Diagram –3–REV. A AD693

noninverting input of the V/I is at 6.2 V. differential input applied to the Signal Amplifier at the left. signal applied to the V/I results in a 20 mA loop current. as common-mode noise on “grounded” signal sources. with a user supplied resistor. application voltages for setting the various “live zero” currents. auxiliary amplifier which can be used for transducer excitation. full-scale output current of 20 mA. consequences of voltage overdrive at the V/I input. mately 1 mA (6.2 kΩ to common). Figure 9. Functional Flock Diagram

3.5 V of headroom with respect to V IN at its input and about 2 V

converter when configured as a follower and resistively loaded. source can be set up for transducer excitation. required in high-current loops.

6.2 V reference should be loaded by approximately 1 mA

base of a user supplied NPN transistor as shown in Figure 11. continuous operation with 25 mA current at the supply voltage. sinking the external pass transistor is suggested. divider network to the inverting terminal of the V/I converter. Figure 10. Minimal Connection for 0–30 mV Unipolar Input, 4–20 mA Output

Pins 14 and 3 will decrease the temperature span. the AD693 to a variety of load cells and strain gages. bridge can be directly powered from the 6.2 V Reference. higher resistance sensors can use proportionally higher voltage. the full-scale span of the Signal Amplifier must be reduced. excitation, therefore, dictates that the span be adjusted to 4 mV. potentiometer for full-scale adjustment. found by multiplying that sensitivity by the excitation voltage. AD590 and a few external resistors as shown in Figure 19. set to 0) and adjust the potentiometer for a 4 mA loop current. Figure 18. Utilizing the Auxiliary Amplifier to Drive a Load Cell, 12 mA ± 8 mA Output

REV. A–12– C1050a–9–10/87PRINTED IN U.S.A. Error it is necessary to add an error of only (5 – 2) × VOS to the error budget. Note that span error may by reduced to zero with the span trim, leaving only the offset and nonlinearity of the AD693. EXAMPLE I The AD693 is configured as a 4-20mA loop powered transmitter with a 60 mV FS input. The inputs are driven by a differential voltage at 2 V common mode with a 300 Ω balanced source resistance. A 24 V loop supply is used with a 500 Ω metering resistance. (See Table IV below.) Trimming the offset and span for your application will remove all span and offset errors except the nonlinearity of the AD693. Table IV. Example 1 OFFSET ERRORS IZ Already included in the TUE spec . 0.0 µV PSRR PSRR = 5.6 µV/V; (|24 V – 24 V| + [ | 500 Ω – 250 Ω × 4 mA]) × 5.6 µV/V =5.6 µV VLOOP = 24 V RL = 500 Ω IZ = 4 mA CMRR CMRR = 30 µV/V; |2 V –3.1 V| × 30 µV/V = 33.0 µV VCM = 2 V IOS IOS = 3 nA, R S = 300 Ω ; 300 Ω × 3 nA = 0.9 µV Total Additional Error at 4 mA 39.5 µV As % of full scale; (39.5 µV × 0.2666 A/V)/20 mA × 100% = 0.053 % of FS SPAN ERRORS X SE Already included in the TUE spec 0.0 µV XPSRR PSRR = 5.6 µV/V; (|500 Ω – 250 Ω | × 16 mA) × 5.6 µV/V = 22.4 µV RL = 500 Ω , IS = 16 mA XCMRR XCMRR = 0.06%/V; |2 V – 3. 1 V| × 60 mV × 0.06%/V = 39.6 µV VCM = 2 V, VSPAN = 60 mV IDIFF VSPAN = +60 mV; 300 Ω × 2 × 20 nA 12.0 µV IDIFF/ + In = 2 from Figure 2) XNL Already included in the TUE 0.0 µV Total Additional Span Error at Full Scale 74.0 µV Total Additional Error at Full Scale; eOFFSET + eSPAN = 39.5 µV + 74.0 µV = 113.5 µV As % of Full Scale; (113.5 µV × 0.2666A V)/20 mA × 100% = 0.151% of FS New Total Unadjusted Error @ FS; eTUE + eADDITIONAL = 0.5% +0.151% = 0.651% of FS and an input common-mode voltage of 3.1 V. The expressions below calculate errors due to deviations from these nominal conditions. The total error at zero consists only of offset errors. The total error at full scale consists of the offset errors plus the span errors. Adding the above errors in this manner may result in an error as large as 0.8% of full scale, however, as a rule, the AD693 performs better as the span and offset errors do not tend to add worst case. The specification “Total Unadjusted Error,” (TUE), reflects this and gives the maximum error as a % of full scale for any point in the transfer function when the device is operated in one of its preset spans, with no external trims. The TUE is less than the error you would get by adding the span and offset errors worst case. Thus, an alternative way of calculating the total error is to start with the TUE and add to it those errors that result from operation of the AD693 with a load resistance, loop supply voltage, or common-mode input voltage different than specified. (See Example 1 below.) ERROR BUDGET FOR SPANS LESS THAN 30 mV An accommodation must be made to include the input voltage offset of the signal amplifier when the span is adjusted to less than 30 mV. The TUE and the Zero Current Error include the input offset voltage contribution of the signal amplifier in a gain of 2. As the input offset voltage is multiplied by the gain of the signal amplifier, one must include the additional error when the signal amplifier is set to gains greater than 2. For example, the 300K span thermocouple application discussed previously requires a 12.207 mV input span; the signal amplifier must be adjusted to a gain of approximately 5. The loop trans- conductance is now 1.333 A/V, (5 × 0.2666 A/V). Calculate the total error by substituting the new values for the transconductance and span into the equations in Table III as was done in Example I. The error contribution due to V OS is 5 × VOS, however, since 2 × VOS is already included in the TUE and the Zero Current E-20A 20-Terminal Leadless Chip Carrier D-20 20-Lead Side Brazed Ceramic DIP Q-20 20-Lead Cerdip OUTLINE DIMENSIONS Dimensions shown in inches and (mm).