AD679SD

AD679 AD | Alldatasheet

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 14-Bit 128 kSPS Complete Sampling ADC AD679*

FEATURES

AC and DC Characterized and Specified (K, B, T Grades) 128k Conversions per Second

1 MHz Full Power Bandwidth

500 kHz Full Linear Bandwidth 80 dB S/N+D (K, B, T Grades) Twos Complement Data Format (Bipolar Mode) Straight Binary Data Format (Unipolar Mode)

10 MV Input Impedance

8-Bit Bus Interface (See AD779 for 16-Bit Interface) On-Board Reference and Clock

10 V Unipolar or Bipolar Input Range

Pin Compatible with AD678 12-Bit, 200 kSPS ADC MIL-STD-883 Compliant Versions Available Tel: 617/329-4700 Fax: 617/326-8703 PRODUCT HIGHLIGHTS 1. COMPLETE INTEGRATION: The AD679 minimizes external component requirements by combining a high speed sample-hold amplifier (SHA), ADC, 5 V reference, clock and digital interface on a single chip. This provides a fully specified sampling A/D function unattainable with discrete designs. 2. SPECIFICATIONS: The AD679K, B and T grades provide fully specified and tested ac and dc parameters. The AD679J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifica- tions (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal process- ing applications. 3. EASE OF USE: The pinout is designed for easy board lay- out, and the two read output provides compatibility with 8- bit buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated performance. 4. RELIABILITY: The AD679 utilizes Analog Devices’ mono- lithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs. 5. UPGRADE PATH: The AD679 provides the same pinout as the 12-bit, 200 kSPS AD678 ADC. 6. The AD679 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD679/883B data sheet for detailed specifications. GENERAL DESCRIPTION The AD679 is a complete, multipurpose 14-bit monolithic analog-to-digital converter, consisting of a sample-hold ampli- fier (SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry. The AD679 is specified for ac (or “dynamic”) parameters such as S/N+D ratio, THD and IMD which are important in signal processing applications. In addition, the AD679K, B and T grades are fully specified for dc parameters which are important in measurement applications. The 14 data bits are accessed in two read operations (8+6), with left justification. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a full-scale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input im- pedance (10 MΩ ) allows direct connection to unbuffered sources without signal degradation. Conversions can be initiated either under microprocessor control or by an external clock asynchronous to the system clock. This product is fabricated on Analog Devices’ BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging al- gorithm which includes error correction and flash converter cir- cuitry to achieve high speed and resolution. The AD679 operates from +5 V and ± 12 V supplies and dissi- pates 560 mW (typ). 28-pin plastic DIP, ceramic DIP and 44 J-leaded ceramic surface mount packages are available. *Protected by U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445; 4,808,908; RE 30,586

AD679–SPECIFICATIONS AC SPECIFICATIONS AD679J/A/S AD679K/B/T Parameter Min Typ Max Min Typ Max Units SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO 2 –0.5 dB Input (Referred to –0 dB Input) 78 79 80 81 dB –20 dB Input (Referred to –20 dB Input) 58 59 60 61 dB –60 dB Input (Referred to –60 dB Input) 18 19 20 21 dB TOTAL HARMONIC DISTORTION (THD) 3 0.003 0.006 0.003 0.006 % TMIN to TMAX –88 –82 –88 –82 dB 0.004 0.008 0.004 0.008 % PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –90 –84 –90 –84 dB FULL POWER BANDWIDTH 1 1 MHz FULL LINEAR BANDWIDTH 500 500 kHz INTERMODULATION DISTORTION (IMD) 4 2nd Order Products –90 –84 –90 –84 dB 3rd Order Products –90 –84 –90 –84 dB DIGITAL SPECIFICATIONS Parameter Test Conditions Min Max Units LOGIC INPUTS V IH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage 0 0.8 V IIH High Level Input Current V IN = 5 V –10 +10 µA IIL Low Level Input Current V IN = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage I OH = 0.1 mA 4.0 V IOH = 0.5 mA 2.4 V VOL Low Level Output Voltage I OL = 1.6 mA 0.4 V IOZ High Z Leakage Current V IN = 0 or 5 V –10 +10 µA COZ High Z Output Capacitance 10 pF NOTES 1flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless otherwise noted. 2See Figure 15 for higher frequencies and other input amplitudes. 3See Figures 13 and 14 for higher frequencies and other input amplitudes. 4fA = 9.08 kHz, f B = 9.58 kHz, with f SAMPLE 100 kSPS. See Definition of Specifications section. Specifications subject to change without notice. REV. C–2– (All device types TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%) (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, fSAMPLE = 128 kSPS, fIN = 10.009 kHz unless otherwise noted)1

Parameter Min Typ Max Min Typ Max Units TEMPERATURE RANGE J, K Grades 0 +70 0 +70 °C A, B Grades –40 +85 –40 +85 °C S, T Grades –55 +125 –55 +125 °C ACCURACY Resolution 14 14 Bits Integral Nonlinearity (INL) ± 2 ± 1 62 LSB Differential Nonlinearity (DNL) 14 14 Bits Unipolar Zero Error 1 (@ +25°C) 0.08 0.05 0.07 % FSR* Bipolar Zero Error 1 (@ +25°C) 0.08 0.05 0.07 % FSR Gain Error1, 2 (@ +25°C) 0.12 0.09 0.11 % FSR Temperature Drift Unipolar Zero3 J, K Grades 0.04 0.04 0.05 % FSR A, B Grades 0.05 0.05 0.07 % FSR S, T Grades 0.09 0.09 0.10 % FSR Bipolar Zero3 J, K Grades 0.02 0.02 0.04 % FSR A, B Grades 0.04 0.04 0.05 % FSR S, T Grades 0.08 0.08 0.09 % FSR Gain3 J, K Grades 0.09 0.09 0.11 % FSR A, B Grades 0.10 0.10 0.16 % FSR S, T Grades 0.20 0.20 0.25 % FSR Gain4 J, K Grades 0.04 0.04 0.05 % FSR A, B Grades 0.05 0.05 0.07 % FSR S, T Grades 0.09 0.09 0.10 % FSR ANALOG INPUT Input Ranges Unipolar Mode 0 +10 0 +10 V Bipolar Mode –5 +5 –5 +5 V Input Resistance 10 10 M Ω Input Capacitance 10 10 pF Input Settling Time 1.5 1.5 µs Aperture Delay 10 10 ns Aperture Jitter 150 150 ps INTERNAL VOLTAGE REFERENCE Output Voltage5 4.98 5.02 4.98 5.02 V External Load Unipolar Mode +1.5 +1.5 mA Bipolar Mode +0.5 +0.5 mA POWER SUPPLIES Power Supply Rejection VCC = +12 V ± 5% ± 6 66 LSB VEE = –12 V ± 5% ± 6 66 LSB VDD = +5 V ± 10% ± 6 66 LSB Operating Current ICC 18 20 18 20 mA IEE 25 34 25 34 mA IDD 8 12 8 12 mA Power Consumption 560 745 560 745 m W NOTES 1Adjustable to zero. See Figures 5 and 6. 2Includes internal voltage reference error. 3Includes internal voltage reference drift. 4Excludes internal voltage reference drift. 5With maximum external load applied. *% FSR = percent of full-scale range. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at T MIN, 25°C and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10% unless otherwise noted) AD679 REV. C –3–

REV. C –5– ABSOLUTE MAXIMUM RATINGS* With Respect Specification To Min Max Units VCC AGND –0.3 +18 V VEE AGND –18 +0.3 V VCC (Note 1) V EE –0.3 +26.4 V VDD DGND 0 +7 V AGND DGND –1 +1 V AIN, REF IN AGND V EE VCC V Digital Inputs DGND –0.5 +7 V Digital Outputs DGND –0.5 V DD + 0.3 V Max Junction Temperature 175 °C CAUTION The AD679 features input protection circuitry consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD679 has been classified as a Category 1 device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equip- ment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. WARNING! ESD SENSITIVE DEVICE With Respect Specification To Min Max Units Operating Temperature J and K Grades 0 +70 °C A and B Grades –40 +85 °C S and T Grades –55 +125 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec max) +300 °C NOTES *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1The AD679 is not designed to operate from ± 15 V supplies. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead J-Leaded Chip Carrier (J-44)28-Pin Ceramic DIP Package (D-28) 28-Lead Plastic DIP Package (N-28)

REV. C–6– PIN DESCRIPTION 28-Pin 44-Lead DIP JLCC Symbol Pin No. Pin No. Type Name and Function AGND 7 11 P Analog Ground. This is the ground return for AIN only. AIN 6 10 AI Analog Signal Input. BIPOFF 10 15 AI Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary output coding. Connect to REF OUT for ± 5 V input bipolar mode and twos complement binary output coding. CS 4 6 DI Chip Select. Active LOW. DGND 12, 14 23 P Digital Ground. DB7–DB0 26–19 40, 39, 37, 36, DO Data Bits. These pins provide all 14 bits in two bytes (8+6 bits). Active HIGH. 35, 34, 33, 31 EOC 27 42 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion finishes. In asynchronous mode, EOC is an open drain output and requires an external 3 k Ω pull-up resistor. See EOCEN and SYNC pins for information on EOC gating. EOCEN 1 1 DI End-of-Convert Enable. Enables EOC pin. Active LOW. HBE 15 25 DI High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte (corresponding to the most recently read high byte). OE 2 3 DI Output Enable. A down-going transition on OE enables DB7–DB0. Gated with CS. Active LOW. REFIN 9 14 AI Reference Input. +5 V input gives 10 V full-scale range. REFOUT 8 12 AO +5 V Reference Output. Tied to REF IN for normal operation. SC 3 5 DI Start Convert. Active LOW. See SYNC pin for gating. SYNC 13 21 DI SYNC Control. If tied to V DD (synchronous mode), SC and EOCEN are gated by CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen- dent of CS, and EOC is an open drain output. EOC requires an external 3 k Ω pull-up resistor in asynchronous mode. VCC 11 17 P +12 V Analog Power. VEE 5 8 P –12 V Analog Power. VDD 28 43 P +5 V Digital Power. — 16 U Tie to DGND. — 17–18 2, 4, 7, 9, 13, U These pins are unused and should be connected to DGND or V DD. 16, 18, 19, 20, 22, 24, 26, 27, 28, 29, 30, 32, 38, 41, 44 Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are three-state drivers. P = Power. U = Unused.

REV. C –7– NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist Frequency” of a converter is that input frequency which is one- half the sampling frequency of the converter. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of a full-scale input signal and is ex- pressed as a percentage or in decibels. For input signals or harmonics that are above the Nyquist frequency, the aliased component is used. PEAK SPURIOUS OR PEAK HARMONIC COMPONENT The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a full- scale input signal. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb) and the third or- der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. The two signals applied to the converter are of equal amplitude and the peak value of their sum is –0.5 dB from full- scale (9.44 V p-p). The IMD products are normalized to a 0-dB input signal. BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. The full-linear bandwidth is the input frequency at which the slew rate limit of the sample-hold-amplifier (SHA) is reached. At this point, the amplitude of the reconstructed fundamental has degraded by less than –0.1 dB. Beyond this frequency, dis- tortion of the sampled input signal increases significantly. The AD679 has been designed to optimize input bandwidth, al- lowing it to undersample input signals with frequencies signifi- cantly above the converter’s Nyquist frequency. APERTURE DELAY Aperture delay is a measure of the SHA’s performance and is measured from the falling edge of Start Convert ( SC) to when the input signal is held for conversion. In synchronous mode, Chip Select ( CS) should be LOW before SC to minimize aper- ture delay. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. INPUT SETTLING TIME Settling time is a function of the SHA’s ability to track fast slew- ing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated con- version accuracy. DIFFERENTIAL NONLINEARITY (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential linearity is the deviation from this ideal value. It is often speci- fied in terms of resolution for which no missing codes (NMC) are guaranteed. INTEGRAL NONLINEARITY (INL) The ideal transfer function for a linear ADC is a straight line drawn between “zero” and “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last code tran- sition. Integral linearity error is the worst case deviation of a code from the straight line. The deviation of each code is mea- sured from the middle of that code. Note that the linearity error is not user adjustable. POWER SUPPLY REJECTION Variations in power supply will affect the full-scale transition, but not the converter’s linearity. Power Supply Rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. TEMPERATURE DRIFT This is the maximum change in the parameter from the initial value (@ +25°C) to the value at T MIN or TMAX. UNIPOLAR ZERO ERROR In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. Unipolar zero error is the devia- tion of the actual transition from that point. This error can be adjusted as discussed in the Input Connections and Calibration section. BIPOLAR ZERO ERROR In the bipolar mode, the major carry transition (11 1111 1111 1111 to 00 0000 0000 0000 ) should occur at an analog value 1/2 LSB below analog ground. Bipolar zero error is the devia- tion of the actual transition from that point. This error can be adjusted as discussed in the Input Connections and Calibration section. GAIN ERROR The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale (9.9991 volts for a 0 V–10 V range, 4.9991 volts for a ± 5 V range). The gain error is the deviation of the actual level at the last transition from the ideal level with the zero error trimmed out. This error can be adjusted as shown in the Input Connections and Calibration section.

REV. C–8– CONVERSION CONTROL In synchronous mode (SYNC = HIGH), both Chip Select ( CS) and Start Convert ( SC) must be brought LOW to start a con- version. CS should be LOW tSC before SC is brought LOW. In asynchronous mode (SYNC = LOW), a conversion is started by bringing SC low, regardless of the state of CS. Before a conversion is started, End-of-Convert (EOC) is HIGH and the sample-hold is in track mode. After a conversion is started, the sample-hold goes into hold mode and EOC goes LOW, signifying that a conversion is in progress. During the conversion, the sample-hold will go back into track mode and start acquiring the next sample. In track mode, the sample-hold will settle to ± 0.003% (14 bits) in 1.5 µs maximum. The acquisition time does not affect the throughput rate as the AD679 goes back into track mode more than 2 µs before the next conversion. In multichannel systems, the input channel can be switched as soon as EOC goes LOW. Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the output data bits (DB7–DB0). A period of time tCD is required after OE is brought HIGH be- fore the next SC instruction is issued. If SC is held LOW, conversion accuracy may deteriorate. For this reason, SC should not be held low in an attempt to operate in a continuously converting mode. START CONVERSION TRUTH TABLE INPUTS SYNC CS SC STATUS 1 1 X No Conversion Synchronous 1 0 f Start Conversion Mode 1 f 0 Start Conversion (Not Recommended) 1 0 0 Continuous Conversion (Not Recommended)

0 X 1 No Conversion

Asynchronous 0 X f Start Conversion Mode 0 X 0 Continuous Conversion (Not Recommended) NOTES 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. = HIGH to LOW transition. Must stay low for t = t CP. 14-BIT MODE CODING FORMAT (1 LSB = 0.61 mV) Unipolar Coding Bipolar Coding (Straight Binary) (Twos Complement) VIN* Output Code V IN* Output Code +2.50000 V 010 . . . 0 +4.99939 V 011 . . . 1 *Code center. END-OF-CONVERT In asynchronous mode, End-of-Convert (EOC) is an open drain output (requiring a minimum 3 k Ω pull-up resistor) enabled by End-of-Convert Enable ( EOCEN). In synchronous mode, EOC is a three-state output which is enabled by EOCEN and CS. See Conversion Status Truth Table. Access (t BA) and float (tFD) timing specifications do not apply in asynchronous mode where they are a function of the time constant formed by the external load capacitance and the pull-up resistor. OUTPUT ENABLE OPERATION The data bits (DB7–DB0) are three-state outputs that are en- abled by Chip Select ( CS) and Output Enable ( OE). CS should be LOW tOE before OE is brought LOW. When EOC goes HIGH, the conversion is completed and the output data may be read. The output is read in two steps as a 16-bit word, with the high byte read first, followed by the low byte. High Byte Enable ( HBE) controls the output sequence. The 14-bit result is left justified within the 16-bit field. In unipolar mode (BIPOFF tied to AGND), the output coding is straight binary. In bipolar mode (BIPOFF tied to REF OUT), output coding is twos-complement binary. POWER-UP The AD679 typically requires 10 µs after power-up to reset in- ternal logic. CONVERSION STATUS TRUTH TABLE INPUTS OUTPUT SYNC CS EOCEN EOC STATUS 1 0 0 0 Converting 1 0 0 1 Not Converting Synchronous 1 1 X High Z Either Mode 1 X 1 High Z Either

0 X 0 0 Converting

Asynchronous 0 X 0 High Z Not Converting Mode* 0 X 1 High Z Either NOTES 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. *EOC requires a pull-up resistor in asynchronous mode. OUTPUT ENABLE TRUTH TABLE INPUTS OUTPUTS HBE (CS U OE) DB7 . . . DB0 X1 ← High Z → Unipolar or 0 0 a b c d e f g h Bipolar 1 0 i j k l m n 0 0 NOTES 1 = HIGH voltage level. a = MSB. 0 = LOW voltage level. n = LSB. X = Don’t care. U = Logical OR. Data coding is binary for Unipolar Mode and 2s Complement Binary for Bipolar Mode.