AD678TD

AD678 AD | Alldatasheet

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CS SC OE EOCEN SYNC 12/8 EOC DB11 DB2 DB1 (R/L) DB0 (HBE) VCC VEE VDD DGND OUTPUT REGISTER 4-BIT FLASH A/D CONVERTER CONTROL LOGIC CONVERSION LOGIC SAMPLE/ HOLD GAIN STAGE 12-BIT D/A CONVERTER VOLTAGE REF. REFOUT REFIN BIPOFF AIN AGND a 12-Bit 200 kSPS Complete Sampling ADC AD678*

FEATURES

AC and DC Characterized and Specified (K, B and T Grades) 200k Conversions per Second

1 MHz Full Power Bandwidth

500 kHz Full Linear Bandwidth 72 dB S/N+D (K, B, T Grades) Twos Complement Data Format (Bipolar Mode) Straight Binary Data Format (Unipolar Mode)

10 M/H9024 Input Impedance

8-Bit or 16-Bit Bus Interface On-Board Reference and Clock

10 V Unipolar or Bipolar Input Range

Commercial, Industrial and Military Temperature Range Grades MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD678 is a complete, multipurpose 12-bit monolithic analog-to-digital converter, consisting of a sample-hold ampli- fier (SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry. The AD678 is specified for ac (or “dynamic”) parameters such as S/N+D ratio, THD and IMD which are important in signal processing applications. In addition, the AD678K, B and T grades are fully specified for dc parameters which are important in measurement applications. The AD678 offers a choice of digital interface formats; the 12 data bits can be accessed by a 16-bit bus in a single read opera- tion or by an 8-bit bus in two read operations (8+4), with right or left justification. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a full-scale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input im- pedance (10 MΩ) allows direct connection to unbuffered sources without signal degradation. This product is fabricated on Analog Devices’ BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging algorithm which includes error correction and flash converter circuitry to achieve high speed and resolution. The AD678 operates from +5 V and ±12 V supplies and dissipates 560 mW (typ). The AD678 is available in 28-lead plastic DIP, ceramic DIP, and 44-lead J-leaded ceramic surface mount packages. Screening to MIL-STD-883C Class B is also available. *Protected by U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445; 4,808,908; RE30,586. PRODUCT HIGHLIGHTS 1. COMPLETE INTEGRATION: The AD678 minimizes ex- ternal component requirements by combining a high speed sample-hold amplifier (SHA), ADC, 5 V reference, clock and digital interface on a single chip. This provides a fully speci- fied sampling A/D function unattainable with discrete designs. 2. SPECIFICATIONS: The AD678K, B and T grades provide fully specified and tested ac and dc parameters. The AD678J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifica- tions (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal process- ing applications. 3. EASE OF USE: The pinout is designed for easy board lay- out, and the choice of single or two read cycle output pro- vides compatibility with 16- or 8-bit buses. Factory trimming eliminates the need for calibration modes or external trim- ming to achieve rated performance. 4. RELIABILITY: The AD678 utilizes Analog Devices’ mono- lithic BiMOS technology. This ensures long-term reliability compared to multichip and hybrid designs. 5. UPGRADE PATH: The AD678 provides the same pinout as the 14-bit, 128 kSPS AD679 ADC. 6. The AD678 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD678/883B data sheet for detailed specifications. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD678–SPECIFICATIONS REV. C–2– AC SPECIFICATIONS AD678J/A/S AD678K/B/T Parameter Min Typ Max Min Typ Max Units SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO 2 –0.5 dB Input (Referred to –0 dB Input) 70 71 71 73 dB –20 dB Input (Referred to –20 dB Input) 51 53 dB –60 dB Input (Referred to –60 dB Input) 11 13 dB TOTAL HARMONIC DISTORTION (THD) 3 –88 –80 –88 –80 dB 0.004 0.010 0.004 0.010 % PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –87 –80 –87 –80 dB FULL POWER BANDWIDTH 1 1 MHz FULL LINEAR BANDWIDTH 500 500 kHz INTERMODULATION DISTORTION (IMD) 4 2nd Order Products –85 –80 –85 –80 dB 3rd Order Products –90 –80 –90 –80 dB NOTES 1fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.9 97 V p-p) input signal unless otherwise indicated. 2See Figures 13 and 14 for higher frequencies and other input amplitudes. 3See Figure 12. 4fA = 9.08 kHz, f B = 9.58 kHz, with f SAMPLE = 200 kSPS. See Definition of Specifications section and Figure 16. Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter Test Conditions Min Max Units LOGIC INPUTS VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage 0 0.8 V IIH High Level Input Current V IN = VDD –10 +10 µA IIL Low Level Input Current V IN = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage I OH = 0.1 mA 4.0 V IOH = 0.5 mA 2.4 V VOL Low Level Output Voltage I OL = 1.6 mA 0.4 V IOZ High Z Leakage Current V IN = 0 or VDD –10 +10 µA COZ High Z Output Capacitance 10 pF Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V /H11550 5%, VEE = –12 V /H11550 5%, VDD = +5 V /H11550 10%, fSAMPLE = 200 kSPS, flN = 10.06 kHz unless otherwise noted) 1 (All device types TMIN to TMAX, VCC = +12 V /H11550 5%, VEE = –12 V /H11550 5%, VDD = +5 V /H11550 10%)

Parameter Min Typ Max Min Typ Max Units TEMPERATURE RANGE J, K Grades 0 +70 0 +70 °C A, B Grades –40 +85 –40 +85 °C S, T Grades –55 +125 –55 +125 °C ACCURACY Resolution 12 12 Bits Integral Nonlinearity (INL) ±1 ±0.7 ±1 LSB Differential Nonlinearity (DNL) 12 12 Bits Unipolar Zero Error (@ +25 °C)1 ±4 ±2 ±3 LSB Bipolar Zero Error (@ +25 °C)1 ±4 ±3 ±5 LSB Gain Error (@ +25°C)1, 2 ±4 ±3 ±6 LSB Temperature Drift Unipolar/Bipolar Zero J, K Grades ±2 ±2 ±4 LSB A, B Grades ±4 ±3 ±4 LSB S, T Grades ±5 ±4 ±5 LSB Gain3 J, K Grades ±4 ±4 ±6 LSB A, B Grades ±7 ±5 ±9 LSB S, T Grades ±10 ±8 ±10 LSB Gain4 J, K Grades ±2 ±2 ±4 LSB A, B Grades ±4 ±3 ±4 LSB S, T Grades ±6 ±5 ±6 LSB ANALOG INPUT Input Ranges Unipolar Range 0 +10 0 +10 V Bipolar Range –5 +5 –5 +5 V Input Resistance 10 10 M Ω Input Capacitance 10 10 pF Input Settling Time 1 1 µs Aperture Delay 10 10 ns Aperture Jitter 150 150 ps INTERNAL VOLTAGE REFERENCE Output Voltage5 4.98 5.02 4.98 5.02 V External Load Unipolar Mode +1.5 +1.5 mA Bipolar Mode +0.5 +0.5 mA POWER SUPPLIES Power Supply Rejection VCC = +12 V ± 5% ±2 ±2 LSB VEE = –12 V ± 5% ±2 ±2 LSB VDD = +5 V ± 10% ±2 ±2 LSB Operating Current ICC 18 20 18 20 mA IEE 25 34 25 34 mA IDD 81 2 81 2 m A Power Consumption 560 745 560 745 mW NOTES 1Adjustable to zero. 2Includes internal voltage reference error. 3Includes internal voltage reference drift. 4Excludes internal voltage reference drift. 5With maximum external load applied. Specifications subject to change without notice. AD678 (TMIN to TMAX, VCC = +12 V /H11550 5%, VEE = –12 V /H11550 5%, VDD = +5 V /H11550 10% unless otherwise noted) REV. C –3–

REV. C –5– ORDERING GUIDE Model1 Package Temperature Range Tested and Specified Package Option 2 AD678JN 28-Lead Plastic DIP 0 °C to +70°C AC N-28 AD678KN 28-Lead Plastic DIP 0 °C to +70°C AC + DC N-28 AD678JD 28-Lead Ceramic DIP 0 °C to +70°C AC D-28 AD678KD 28-Lead Ceramic DIP 0 °C to +70°C AC + DC D-28 AD678AD 28-Lead Ceramic DIP –40 °C to +85°C AC D-28 AD678BD 28-Lead Ceramic DIP –40 °C to +85°C AC + DC D-28 AD678AJ 44-Lead Ceramic JLCC –40 °C to +85°C AC J-44 AD678BJ 44-Lead Ceramic JLCC –40 °C to +85°C AC + DC J-44 AD678SD 28-Lead Ceramic DIP –55 °C to +125°C AC D-28 AD678TD 28-Lead Ceramic DIP –55 °C to +125°C AC + DC D-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military Products D atabook or /883 data sheet. 2N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier. ABSOLUTE MAXIMUM RATINGS* With Respect Specification To Min Max Units VCC AGND –0.3 +18 V VEE AGND –18 +0.3 V VCC VEE –0.3 +26.4 V VDD DGND 0 +7 V AGND DGND –1 +1 V AIN, REF IN AGND V EE VCC V Digital Inputs DGND –0.5 +7 V Digital Outputs DGND –0.5 V DD + 0.3 V Max Junction Temperature 175 °C Operating Temperature J and K Grades 0 +70 °C A and B Grades –40 +85 °C S and T Grades –55 +125 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec max) +300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY The AD678 features input protection circuitry consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD678 has been classified as a Category 1 device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. AD678 CS SC OE EOCEN SYNC 12/8 EOC DB11 DB2 DB1 (R/L) DB0 (HBE) VCC VEE VDD DGND OUTPUT REGISTER 4-BIT FLASH A/D CONVERTER CONTROL LOGIC CONVERSION LOGIC SAMPLE/ HOLD GAIN STAGE 12-BIT D/A CONVERTER VOLTAGE REF. REFOUT REFIN BIPOFF AIN AGND Functional Block Diagram WARNING! ESD SENSITIVE DEVICE

REV. C–6– PIN DESCRIPTION 28-Lead DIP 44-Lead Symbol Pin No. JLCC Pin No. Type Name and Function AGND 7 11 P Analog Ground. This is the ground return for AIN only. AIN 6 10 AI Analog Signal Input. BIPOFF 10 15 AI Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary output coding. Connect to REF OUT through 50 Ω resistor for ±5 V input bipolar mode and twos complement binary output coding. See Figures 7 and 8. CS 4 6 DI Chip Select. Active LOW. DGND 14 23 P Digital Ground DB11–DB4 26–19 40, 39, 37, 36, DO Data Bits 11 through 4. In 12-bit format (see 12/ 8 pin), these pins provide the upper 8 bits 35, 34, 33, 31 of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/ L pin). Active HIGH. DB3, DB2 18, 17 30, 27 DO Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2. Active HIGH. In 8-bit format they are undefined and should be tied to V DD. DB1 (R/L) 16 26 DO In 12-bit format, Data Bit 1. Active HIGH. DB0 (HBE) 15 25 DO In 12-bit format, Data Bit 0. Active HIGH. EOC 27 42 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion is finished. In asynchronous mode, EOC is an open drain output and requires an external 3 k Ω pull-up resistor. See EOCEN and SYNC pins for information on EOC gating. EOCEN 1 1 DI End-Of-Convert Enable. Enables EOC pin. Active LOW. HBE (DB0) 15 25 DI In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte. OE 2 3 DI Output Enable. The falling edge of OE enables DB11–DB0 in 12-bit format and DB11–DB4 in 8-bit format. Gated with CS. Active LOW. REF IN 9 14 AI Reference Input. +5 V input gives 10 V full-scale range. REFOUT 8 12 AO +5 V Reference Output. Tied to REF IN through 50 Ω resistor for normal operation. R/L (DB1) 16 26 DI In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field. Tied to VDD for right-justified output and tied to DGND for left-justified output. SC 3 5 DI Start Convert. Active LOW. See SYNC pin for gating. SYNC 13 21 DI SYNC Control. If tied to V DD (synchronous mode), SC, EOC and EOCEN are gated by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS, and EOC is an open drain output. EOC requires an external 3 k Ω pull-up resistor in asynchronous mode. VCC 11 17 P +12 V Analog Power. VEE 5 8 P –12 V Analog Power. VDD 28 43 P +5 V Digital Power. 12/8 12 19 DI Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied LOW, sets output format to 8-bit multiplexed. No Connect 2, 4, 7, 9, 13, These pins are unused and should be connected to DGND or V DD. 16, 18, 20, 22, 24, 28, 29, 32, 38, 41, 44 Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are three-state drivers; P = Power. PIN CONFIGURATIONS DIP PACKAGE JLCC PACKAGE EOCEN OE VEE AIN AGND SC CS REFOUT REFIN BIPOFF VCC SYNC DGND 258 21 92 0 10 19 12 17 14 15 TOP VIEW (Not to Scale) AD678 VDD EOC DB9 DB8 DB7 DB11 DB10 DB6 DB5 DB4 DB3 DB2 DB1 (R/L) DB0 (HBE) 6 5 4 3 2 44 43 42 41 40 18 19 20 21 22 24 25 26 27 2823 PIN 1 IDENTIFIER TOP VIEW NC NC NC NC V EE AIN AGND REFOUT REFIN BIPOFF VCC NC NC NC DB9 DB8 DB7 DB10 DB6 DB5 DB4 DB3 CS SC NC OE NC EOCEN V DD EOC DB11 NC NC NC NC DGND NC NC SYNC DB0 (HBE) DB1 (R/L) DB2 NC AD678 NC = NO CONNECT

Definition of Specifications–AD678 NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist Frequency” of a converter is that input frequency which is one- half the sampling frequency of the converter. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of a full-scale input signal and is ex- pressed as a percentage or in decibels. For input signals or harmonics that are above the Nyquist frequency, the aliased component is used. PEAK SPURIOUS OR PEAK HARMONIC COMPONENT The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a full- scale input signal. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb) and the third order terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input sides to the rms sum of the distortion terms. The two signals applied to the converter are of equal ampli- tude and the peak value of their sum is –0.5 dB from full scale (9.44 V p-p). The IMD products are normalized to a 0 dB input signal. BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. The full-linear bandwidth is the input frequency at which the slew rate limit of the sample-hold-amplifier (SHA) is reached. At this point, the amplitude of the reconstructed fundamental has degraded by less than 0.1 dB. Beyond this frequency, distor- tion of the sampled input signal increases significantly. The AD678 has been designed to optimize input bandwidth, al- lowing the AD678 to undersample input signals with frequen- cies significantly above the converter’s Nyquist frequency. APERTURE DELAY Aperture delay is a measure of the SHA’s performance and is measured from the falling edge of Start Convert ( SC) to when the input signal is held for conversion. In synchronous mode, Chip Select (CS) should be LOW before SC to minimize aper- ture delay. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. INPUT SETTLING TIME Settling time is a function of the SHA’s ability to track fast slew- ing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated con- version accuracy. DIFFERENTIAL NONLINEARITY (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes (NMC) are guaranteed. UNIPOLAR ZERO ERROR In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point. This error can be ad- justed as discussed in the Input Connections and Calibration section. BIPOLAR ZERO ERROR In the bipolar mode, the major carry transition (1111 1111 1111 to 0000 0000 0000) should occur at an analog value 1/2 LSB below analog ground. Bipolar zero error is the deviation of the actual transition from that point. This error can be adjusted as discussed in the Input Connections and Calibration section. GAIN ERROR The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale (9.9963 volts for a 0–10 V range, 4.9963 volts for a ±5 V range). The gain error is the deviation of the actual difference between the first and last code transition from the ideal difference between the first and last code transi- tion. This error can be adjusted as shown in the Input Connec- tions and Calibration section. INTEGRAL NONLINEARITY (INL) The ideal transfer function for a linear ADC is a straight line drawn between “zero” and “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last code tran- sition. Integral nonlinearity is the worst-case deviation of a code from the straight line. The deviation of each code is measured from the middle of that code. POWER SUPPLY REJECTION Variations in power supply will affect the full-scale transition, but not the converter’s linearity. Power Supply Rejection is the maximum change in the full-scale transition point due to a change in power-supply voltage from the nominal value. TEMPERATURE DRIFT This is the maximum change in the parameter from the initial value (@ +25°C) to the value at T MIN or TMAX. REV. C –7–

REV. C –9– CONVERSION CONTROL In synchronous mode (SYNC = HIGH), both Chip Select ( CS) and Start Convert (SC) must be brought LOW to start a con- version. CS should be LOW tSC before SC is brought LOW. In asynchronous mode (SYNC = LOW), a conversion is started by bringing SC low, regardless of the state of CS. Before a conversion is started, End-of-Convert (EOC) is HIGH, and the sample-hold is in track mode. After a conversion is started, the sample-hold goes into hold mode and EOC goes LOW, signifying that a conversion is in progress. During the conversion, the sample-hold will go back into track mode and start acquiring the next sample. EOC goes HIGH when the con- version is finished. In track mode, the sample-hold will settle to ±0.01% (12 bits) in 1 µs maximum. The acquisition time does not affect the throughput rate as the AD678 goes back into track mode more than 1 µs before the next conversion. In multichannel systems, the input channel can be switched as soon as EOC goes LOW if the maximum throughput rate is needed. 12-Bit Mode Coding Format (1 LSB = 2.44 mV) Unipolar Coding Bipolar Coding (Straight Binary) (Twos Complement) VIN* Output Code V IN* Output Code +2.500 V 010 . . . 0 +4.9976 V 011 . . . 1 *Code center. OUTPUT ENABLE TRUTH TABLES 12-BIT MODE (12/8 = HIGH) INPUTS OUTPUT (CS U OE) DB11–DB0

1 High Z

0 Enable 12-Bit Output

8-BIT MODE (12/8 = LOW) INPUTS OUTPUTS R/L HBE (CS U OE) DB11 . . . DB4 X X 1 High Z 1 0 0 0000abcd Unipolar 1 1 0 e f g h i j k l Mode 0 0 0 a b c d e f g h 0 1 0 i j kl 0000 1 0 0 aaaaabcd Bipolar 1 1 0 e f g h i j k 1 Mode 0 0 0 a b c d e f g h 0 1 0 i j kl 0000 NOTES 1 = HIGH voltage level. a = MSB. 0 = LOW voltage level. 1 = LSB. X = Don’t care. U = Logical OR. END-OF-CONVERT In asynchronous mode, End-of-Convert (EOC) is an open drain output (requiring a minimum 3 k Ω pull-up resistor) enabled by End-of-Convert ENable ( EOCEN). In synchronous mode, EOC is a three-state output which is enabled by EOCEN and CS. See the Conversion Status Truth Table for details. Access (tBA) and float (tFD) timing specifications do not apply in asyn- chronous mode where they are a function of the time constant formed by the 10 pF output capacitance and the pull-up resistor. START CONVERSION TRUTH TABLE INPUTS SYNC CS SC STATUS 1 1 X No Conversion Synchronous 1 0 Start Conversion Mode 1 0 Start Conversion (Not Recommended) 1 0 0 Continuous Conversion (Not Recommended)

0 X 1 No Conversion

Asynchronous 0 X S tart Conversion Mode 0 X 0 Continuous Conversion (Not Recommended) NOTES 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. X = HIGH to LOW transition. Must stay low for t = t CP. CONVERSION STATUS TRUTH TABLE INPUTS OUTPUT SYNC CS EOCEN EOC STATUS 1 0 0 0 Converting 1 0 0 1 Not Converting Synchronous 1 1 X High Z Either Mode 1 X 1 High Z Either

0 X 0 0 Converting

Asynchronous 0 X 0 High Z Not Converting Mode* 0 X 1 High Z Either NOTES l = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. *EOC requires a pull-up resistor in asynchronous mode.

REV. C –13– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Ceramic DIP Package (D-28) 28-Lead Plastic DIP Package (N-28A)

REV. C–14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Terminal Lead Ceramic (J-44) C1381b –0–3/00 (rev. C) PRINTED IN U.S.A.