AD677KR

AD677 AD | Alldatasheet

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14 SCLK

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 16-Bit 100 kSPS Sampling ADC AD677

FEATURES

On-Chip Sample-Hold Function Serial Output

16 Bits No Missing Codes

61 LSB INL

–99 dB THD 92 dB S/(N+D)

1 MHz Full Power Bandwidth

Tel: 617/329-4700 Fax: 617/326-8703 PRODUCT HIGHLIGHTS 1. Autocalibration provides excellent dc performance while eliminating the need for user adjustments or additional exter- nal circuitry. 2. ± 5 V to ± 10 V input range (± V REF). 3. Available in 16-pin 0.3" skinny DIP or 28-lead SOIC. 4. Easy serial interface to standard ADI DSPs. 5. TTL compatible inputs/outputs. 6. Excellent ac performance: –99 dB THD, 92 dB S/(N+D) peak spurious –101 dB. 7. Industry leading dc performance: 1.0 LSB INL, ± 1 LSB full scale and offset. PRODUCT DESCRIPTION The AD677 is a multipurpose 16-bit serial output analog-to- digital converter which utilizes a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 µs total conversion time). Overall performance is opti- mized by digitally correcting internal nonlinearities through on-chip autocalibration. The AD677 circuitry is segmented onto two monolithic chips— a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package. The AD677 is specified for ac (or “dynamic”) parameters such as S/(N+D) Ratio, THD and IMD which are important in sig- nal processing applications. In addition, dc parameters are specified which are important in measurement applications. The AD677 operates from +5 V and ± 12 V supplies and typi- cally consumes 450 mW using a 10 V reference (360 mW with 5 V reference) during conversion. The digital supply (V DD) is separated from the analog supplies (V CC, VEE) for reduced digi- tal crosstalk. An analog ground sense is provided to remotely sense the ground potential of the signal source. This can be use- ful if the signal has to be carried some distance to the A/D con- verter. Separate analog and digital grounds are also provided. The AD677 is available in a 16-pin narrow plastic DIP, 16-pin narrow side-brazed ceramic package, or 28-lead SOIC. A paral- lel output version, the AD676, is available in a 28-pin ceramic or plastic DIP. All models operate over a commercial tempera- ture range of 0°C to +70°C or an industrial range of –40 °C to +85°C.

AD677–SPECIFICATIONS AC SPECIFICATIONS AD677J/A AD677K/B Parameter Min Typ Max Min Typ Max Units Total Harmonic Distortion (THD) 2 @ 83 kSPS, TMIN to TMAX –97 –92 –99 –95 dB @ 100 kSPS, +25°C –97 –92 –99 –95 dB @ 100 kSPS, TMIN to TMAX –93 –95 dB Signal-to-Noise and Distortion Ratio (S/(N+D)) 2, 3 @ 83 kSPS, TMIN to TMAX 89 91 90 92 dB @ 100 kSPS, +25°C8 9 9 1 9 0 9 2 d B @ 100 kSPS, TMIN to TMAX 89 90 dB Peak Spurious or Peak Harmonic Component –101 –101 dB Intermodulation Distortion (IMD) 4 2nd Order Products –102 –102 dB 3rd Order Products –98 –98 dB Full Power Bandwidth 1 1 MHz Noise 160 160 µV rms DIGITAL SPECIFICATIONS Parameter Test Conditions Min Typ Max Units LOGIC INPUTS VIH High Level Input Voltage 2.0 V DD + 0.3 V VIL Low Level Input Voltage –0.3 0.8 V IIH High Level Input Current V IH = VDD –10 +10 µA IIL Low Level Input Current V IL = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage I OH = 0.1 mA V DD – 1 V V IOH = 0.5 mA 2.4 V VOL Low Level Output Voltage I OL = 1.6 mA 0.4 V NOTES 1VREF = 10.0 V, Conversion Rate = 100 kSPS, f lN = 1.0 kHz, V IN = –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred to a 0 dB (20 V p-p) input signal. Values are post-calibration. 2For other input amplitudes, refer to Figure 12. 3For dynamic performance with different reference values see Figure 11. 4fa = 1008 Hz, fb = 1055 Hz. See Definition of Specifications section and Figure 16. Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1 (for all grades TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%) REV. A–2–

Parameter Min Typ Max Min Typ Max Units TEMPERATURE RANGE J, K Grades 0 +70 0 +70 °C A, B Grades –40 +85 –40 +85 °C ACCURACY Resolution 16 16 Bits Integral Nonlinearity (INL) @ 83 kSPS, TMIN to TMAX ± 1 ± 1 ± 1.5 LSB @ 100 kSPS, +25°C ± 1+ 1 ± 1.5 LSB @ 100 kSPS, TMIN to TMAX ± 2 ± 2 LSB Differential Nonlinearity (DNL)–No Missing Codes 16 16 Bits Bipolar Zero Error 2 ± 2 ± 4 ± 1 ± 3 LSB Positive, Negative FS Errors 2 @ 83 kSPS ± 2 ± 4 ± 1 ± 3 LSB @ 100 kSPS, +25°C ± 2 ± 4 ± 1 ± 3 LSB @ 100 kSPS ± 4 ± 4 LSB TEMPERATURE DRIFT3 Bipolar Zero ± 0.5 ± 0.5 LSB Postive Full Scale ± 0.5 ± 0.5 LSB Negative Full Scale ± 0.5 ± 0.5 LSB VOLTAGE REFERENCE INPUT RANGE 4 (VREF)5 1 0 5 1 0V ANALOG INPUT5 Input Range (VIN) ± VREF ± VREF V Input Impedance * * Input Settling Time 2 2 µs Input Capacitance During Sample 50* 50* pF Aperture Delay 6 6 ns Aperture Jitter 100 100 ps POWER SUPPLIES Power Supply Rejection 6 VCC = +12 V ± 5% ± 0.5 ± 0.5 LSB VEE = –12 V ± 5% ± 0.5 ± 0.5 LSB VDD = +5 V ± 10% ± 0.5 ± 0.5 LSB Operating Current VREF = +5 V ICC 14.5 18 14.5 18 mA IEE 14.5 18 14.5 18 –mA IDD 35 35 m A Power Consumption 360 480 360 480 mW VREF = +10 V ICC 18 24 18 24 mA IEE 18 24 18 24 –mA IDD 35 35 m A Power Consumption 450 630 450 630 mW NOTES 1VREF = 10.0 V, Conversion Rate = 100 kSPS unless otherwise noted. Values are post-calibration. 2Values shown apply to any temperature from T MIN to TMAX after calibration at that temperature at nominal supplies. 3Values shown are based upon calibration at +25 °C with no additional calibration at temperature. Values shown are the typical variation from the value at +25 °C. 4See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 11 for dynamic performance with other reference voltage values. 5See “APPLICATIONS” section for recommended input buffer circuit. 6Typical deviation of bipolar zero, –full scale or +full scale from min to max rating. *For explanation of input characteristics, see “ANALOG INPUT” section. Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)1 REV. A –3–

REV. A –5– WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD677 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Model Range S/(N+D) Max INL Package Description Option* AD677JN 0 °C to +70°C 89 dB Typ Only Plastic 16-Pin DIP N-16 AD677KN 0 °C to +70°C 90 dB ± 1.5 LSB Plastic 16-Pin DIP N-16 AD677JD 0 °C to +70°C 89 dB Typ Only Ceramic 16-Pin DIP D-16 AD677KD 0 °C to +70°C 90 dB ± 1.5 LSB Ceramic 16-Pin DIP D-16 AD677JR 0 °C to +70°C 89 dB Typ Only Plastic 28-Lead SOIC R-28 AD677KR 0 °C to +70°C 90 dB ± 1.5 LSB Plastic 28-Lead SOIC R-28 AD677AD –40 °C to +85°C 89 dB Typ Only Ceramic 16-Pin DIP D-16 AD677BD –40 °C to +85°C 90 dB ± 1.5 LSB Ceramic 16-Pin DIP D-16 *D = Ceramic DIP; N = Plastic DIP; R = Small Outline IC (SOIC). ABSOLUTE MAXIMUM RATINGS* Analog Inputs, V REF to AGND *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

REV. A–6– PIN DESCRIPTION DIP Pin SOIC Pin Type Name Description 1 1 SAMPLE DI V IN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the suite of the internal sample-hold amplifier and the falling edge initiates conversion. During calibration, SAMPLE should be held LOW. If HIGH during calibration, diagnostic information will appear on SDATA. 2 2 CLK DI Master Clock Input. The AD677 requires 17 clock pulses to execute a conversion. CLK is also used to derive SCLK. 3 3 SDATA DO Serial Output Data Controlled by SCLK. 4 6, 7 DGND P Digital Ground. 58 V CC P +12 V Analog Supply Voltage. 8 12 AGND P Analog Ground. .9 15 AGND SENSE AI Analog Ground Sense. 10 16 V IN AI Analog Input Voltage. 11 17 V REF AI External Voltage Reference Input. 12 21 V EE P –12 V Analog Supply Voltage. 13 22, 23 V DD P +5 V Logic Supply Voltage. 14 26 SCLK DO Clock Output for Data Read, derived from CLK. 15 27 BUSY DO Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress. 16 28 CAL DI Calibration Control Pin. 6, 7 4, 5, 9, 10, 11, NC _ No Connection. No connections should be made to these pins. 13, 14, 18, 19, 20, 24, 25 Type: AI = Analog Input DI = Digital Input DO = Digital Output P = Power 6 23 TOP VIEW (Not to Scale) AD677 NC = NO CONNECT NC AGND CLK SAMPLE DGND2 NC NC VCC NC NC NC SDATA DGND1 NC CAL BUSY VIN VREF NC NC NC VEE NC NC SCLK VDD1 VDD2 AGND SENSE SOIC Pinout SAMPLE CLK DGND NC NC AGND VCC CAL BUSY AGND SENSE VIN VEE VDD VREF TOP VIEW (Not to Scale) AD677 NC = NO CONNECT SCLKSDATA DIP Pinout

INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb), and the third order terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is –0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. APERTURE DELAY Aperture delay is the time required after SAMPLE pin is taken LOW for the internal sample-hold of the AD677 to open, thus holding the value of V IN. APERTURE JITTER Aperture jitter is the variation in the aperture delay from sample to sample. POWER SUPPLY REJECTION DC variations in the power supply voltage will affect the overall transfer function of the ADC, resulting in zero error and full- scale error changes. Power supply rejection is the maximum change in either the bipolar zero error or full-scale error value. Additionally, there is another power supply variation to con- sider. AC ripple on the power supplies can couple noise into the ADC, resulting in degradation of dynamic performance. This is displayed in Figure 15. INPUT SETTLING TIME Settling time is a function of the SHA’s ability to track fast slewing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated conversion accuracy. NOISE/DC CODE UNCERTAINTY Ideally, a fixed dc input should result in the same output code for repetitive conversions. However, as a consequence of un- avoidable circuit noise within the wideband circuits in the ADC, there is a range of output codes which may occur for a given in- put voltage. If you apply a dc signal to the ADC and record a large number of conversions, the result will be a distribution of codes. If you fit a Gaussian probability distribution to the histo- gram, the standard deviation is approximately equivalent to the rms input noise of the ADC. REV. A –7– Definition of Specifications–AD677 NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist frequency’’ of a converter is that input frequency which is one half the sampling frequency of the converter. TOTAL HARMONIC DISTORTION Total harmonic distortion (THD) is the ratio of the rms sum of the harmonic components to the rms value of a full-scale input signal and is expressed in percent (%) or decibels (dB). For in- put signals or harmonics that are above the Nyquist frequency, the aliased components are used. SIGNAL-TO-NOISE PLUS DISTORTION RATIO Signal-to-noise plus distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, includ- ing harmonics but excluding dc. +/– FULL-SCALE ERROR occur for an analog voltage 1.5 LSB below the nominal full scale (4.99977 volts for a ± 5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. BIPOLAR ZERO ERROR Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the mid- scale output code. DIFFERENTIAL NONLINEARITY (DNL) In an ideal ADC, code transitions are one LSB apart. Differen- tial nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. INTEGRAL NONLINEARITY (INL) The ideal transfer function for an ADC is a straight line bisect- ing the center of each code drawn between “zero” and “full scale.” The point used as “zero” occurs 1/2 LSB before the most negative code transition. “Full scale” is defined as a level 1.5 LSB beyond the most positive code transition. Integral non- linearity is the worst-case deviation of a code center average from the straight line. BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.

REV. A–8– FUNCTIONAL DESCRIPTION The AD677 is a multipurpose 16-bit analog-to-digital converter and includes circuitry which performs an input sample/hold function, ground sense, and autocalibration. These functions are segmented onto two monolithic chips—an analog signal pro- cessor and a digital controller. Both chips are contained within the AD677 package. The AD677 employs a successive-approximation technique to determine the value of the analog input voltage. However, in- stead of the traditional laser-trimmed resistor-ladder approach, this device uses a capacitor-array, charge redistribution tech- nique. Binary-weighted capacitors subdivide the input sample to perform the actual analog-to-digital conversion. The capacitor array eliminates variation in the linearity of the device due to temperature-induced mismatches of resistor values. Since a capacitor array is used to perform the data conversions, the sample/hold function is included without the need for additional external circuitry. Initial errors in capacitor matching are eliminated by an autocalibration circuit within the AD677. This circuit employs an on-chip microcontroller and a calibration DAC to measure and compensate capacitor mismatch errors. As each error is determined, its value is stored in on-chip memory (RAM). Subsequent conversions use these RAM values to improve con- version accuracy. The autocalibration routine may be invoked at any time. Autocalibration insures high performance while eliminating the need for any user adjustments and is described in detail below. The microcontroller controls all of the various functions within the AD677. These include the actual successive approximation algorithm, the autocalibration routine, the sample/hold opera- tion, and the internal output data latch. AUTO CALIBRATION The AD677 achieves rated performance without the need for user trims or adjustments. This is accomplished through the use of on-chip autocalibration. In the autocalibration sequence, sample/hold offset is nulled by internally connecting the input circuit to the ground sense cir- cuit. The resulting offset voltage is measured and stored in RAM for later use. Next, the capacitor representing the most significant bit (MSB) is charged to the reference voltage. This charge is then transferred to a capacitor of equal size (composed of the sum of the remaining lower weight bits). The voltage that results represents the amount of capacitor mismatch. A calibra- tion digital-to-analog converter (DAC) adds an appropriate value of error correction voltage to cancel this mismatch. This correction factor is also stored in RAM. This process is repeated for each of the eight remaining capacitors representing the top nine bits. The accumulated values in RAM are then used during subsequent conversions to adjust conversion results accordingly. As shown in Figure 1, when CAL is taken HIGH the AD677 internal circuitry is reset, the BUSY pin is driven HIGH, and the ADC prepares for calibration. This is an asynchronous hard- ware reset and will interrupt any conversion or calibration cur- rently in progress. Actual calibration begins when CAL is taken LOW and completes in 85,532 clock cycles, indicated by BUSY going LOW. During calibration, it is preferable for SAMPLE to be held LOW. If SAMPLE is HIGH, diagnostic data will appear on SDATA. This data is of no value to the user. In most applications, it is sufficient to calibrate the AD677 only upon power-up, in which case care should be taken that the power supplies and voltage reference have stabilized first. If calibration is not performed, the AD677 may come up in an un- known state, or performance could degrade to as low as 10 bits. CONVERSION CONTROL The AD677 is controlled by two signals: SAMPLE and CLK, as shown in Figure 2. It is assumed that the part has been cali- brated and the digital I/O pins have the levels shown at the start of the timing diagram. A conversion consists of an input acquisition followed by 17 clock pulses which execute the 16-bit internal successive ap- proximation routine. The analog input is acquired by taking the SAMPLE line HIGH for a minimum sampling time of t S. The actual sample taken is the voltage present on V IN one aperture delay after the SAMPLE line is brought LOW, assuming the previous conversion has completed (signified by BUSY going LOW). Care should be taken to ensure that this negative edge is well defined and jitter free in ac applications to reduce the un- certainty (noise) in signal acquisition. With SAMPLE going LOW, the AD677 commits itself to the conversion—the input at V IN is disconnected from the internal capacitor array, BUSY goes HIGH, and the SAMPLE input will be ignored until the conversion is completed (when BUSY goes LOW). SAMPLE must be held LOW for a minimum period of time t SL. A period of time tFCD after bringing SAMPLE LOW, the 17 CLK cycles are applied; CLK pulses that start before this period of time are ignored. BUSY goes HIGH t SB after SAMPLE goes LOW, sig- nifying that a conversion is in process, and remains HIGH until the conversion is completed. As indicated in Figure 2, the twos complement output data is presented MSB first. This data may be captured with the rising edge of SCLK or the falling edge of CLK, beginning with pulse #2. The AD677 will ignore CLK after BUSY has gone LOW and SDATA or SCLK will not change until a new sample is acquired. CONTINUOUS CONVERSION For maximum throughput rate, the AD677 can be operated in a continuous convert mode. This is accomplished by utilizing the fact that SAMPLE will no longer be ignored after BUSY goes LOW, so an acquisition may be initiated even during the HIGH time of the 17th CLK pulse for maximum throughput rate while enabling full settling of the sample/hold circuitry. If SAMPLE is already HIGH during the rising edge of the 17th CLK, then an acquisition is immediately initiated approxi- mately 100 ns after the rising edge of the 17th clock pulse. Care must be taken to adhere to the minimum/maximum tim- ing requirements in order to preserve conversion accuracy. GENERAL CONVERSION GUIDELINES During signal acquisition and conversion, care should be taken with the logic inputs to avoid digital feedthrough noise. It is possible to run CLK continuously, even during the sample period. However, CLK edges during the sampling period, and especially when SAMPLE goes LOW, may inject noise into the sampling process. The AD677 is tested with no CLK cycles during the sampling period. The BUSY signal can be used to prevent the clock from running during acquisition, as illustrated

REV. A –11– made for selecting one with low noise. A capacitor connected between REF IN and AGND will reduce the demands on the reference by decreasing the magnitude of high frequency com- ponents required to be sourced by the reference. Figures 6 and 7 represent typical design approaches. VIN 10µF AGND C N 1.0µF +12V AD586 AD677

8 VREF

0.1µF Figure 6. Figure 6 shows a voltage reference circuit featuring the 5 V out- put AD586. The AD586 is a low cost reference which utilizes a buried Zener architecture to provide low noise and drift. Over the 0°C to +70°C range, the AD586M grade exhibits less than 1.0 mV output change from its initial value at +25 °C. A noise reduction capacitor, C N, reduces the broadband noise of the AD586 output, thereby optimizing the overall performance of the AD677. It is recommended that a 10 µF to 47 µF high qual- ity tantalum capacitor and a 0.1 µF capacitor be tied between the VREF input of the AD677 and ground to minimize the im- pedance on the reference. Using the AD677 with ± 10 V input range (VREF = 10 V) typi- cally requires ± 15 V supplies to drive op amps and the voltage reference. If ± 12 V is not available in the system, regulators such as 78L12 and 79L12 can be used to provide power for the AD677. This is also the recommended approach (for any input range) when the ADC system is subjected to harsh environ- ments such as where the power supplies are noisy and where voltage spikes are present. Figure 7 shows an example of such a system based upon the 10 V AD587 reference, which provides a 300 µV LSB. Circuitry for additional protection against power supply disturbances has been shown. A 100 µF capacitor at each +15V +5V –15V 100µF 100µF 100µF AD677 10µF 10µF 0.1µF 0.1µF 0.1µF 78L12 79L12 0.01µF 0.01µF VIN VREF VDD VCC VEE VIN VO NRGND VIN 10µF 0.1µF 1µF AD587 10µF 2 6 0.1µF 10Ω 10Ω 10Ω 10Ω Figure 7. regulator prevents very large voltage spikes from entering the regulators. Any power line noise which the regulators cannot eliminate will be further filtered by an RC filter (10 Ω /10 µF) having a –3 dB point at 1.6 kHz. For best results the regulators should be within a few centimeters of the AD677. ANALOG INPUT As previously discussed, the analog input voltage range for the AD677 is ± V REF. For purposes of ground drop and common mode rejection, the VIN and VREF inputs each have their own ground. VREF is referred to the local analog system ground (AGND), and VIN is referred to the analog ground sense pin (AGND SENSE) which allows a remote ground sense for the input signal. The AD677 analog inputs (V IN, VREF and AGND SENSE) ex- hibit dynamic characteristics. When a conversion cycle begins, each analog input is connected to an internal, discharged 50 pF capacitor which then charges to the voltage present at the corre- sponding pin. The capacitor is disconnected when SAMPLE is taken LOW, and the stored charge is used in the subsequent conversion. In order to limit the demands placed on the external source by this high initial charging current, an internal buffer amplifier is employed between the input and this capacitance for a few hundred nanoseconds. During this time the input pin ex- hibits typically 20 k Ω input resistance, 10 pF input capacitance and ± 40 µA bias current. Next, the input is switched directly to the now precharged capacitor and allowed to fully settle. During this time the input sees only a 50 pF capacitor. Once the sample is taken, the input is internally floated so that the external input source sees a very high input resistance and a parasitic input capacitance of typically only 2 pF. As a result, the only domi- nant input characteristic which must be considered is the high current steps which occur when the internal buffers are switched in and out. In most cases, these characteristics require the use of an external op amp to drive the input of the AD677. Care should be taken with op amp selection; even with modest loading conditions, most available op amps do not meet the low distortion require- ments necessary to match the performance capabilities of the AD677. Figure 8 represents a circuit, based upon the AD845, which will provide excellent overall performance. For applications optimized more for low distortion and low noise, the AD845 of Figure 8 may be replaced by the AD743. +12V –12V AD845 0.1µF 0.1µF AGND AGND SENSE ±5V INPUT AD677

6 VIN

1k Ω 1k Ω 499Ω Figure 8.

REV. A –15– OUTLINE DIMENSIONS Dimensions shown in inchcs and (mm) D-16 16-Lead Side Brazed Ceramic DIP Package 916 PIN 1 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76)PLANE SEATING 0.080 (2.03) MAX0.005 (0.13) MIN 0.310 (7.87) 0.220 (5.59) N-16 16-Lead Plastic DIP PIN 1 0.060 (1.52) 0.015 (0.38) 0.015 (0.381) 0.008 (0.204) 0.150 (3.81) MIN 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) PLANE SEATING 0.840 (21.33) 0.745 (18.93) 916 0.325 (8.25) 0.300 (7.62) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.200 (5.05) 0.125 (3.18) 0.100 (2.54) BSC R-28 28-Lead Wide Body SOIC (SOIC-28) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0118 (0.30) 0.0040 (0.10) 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.1043 (2.65) 0.0157 (0.40) 0.0125 (0.32) 0.0091 (0.23) 0°- 8° 0.0291 (0.74) 0.0098 (0.25) X 45°

C1786–18–4/93PRINTED IN U.S.A. –16–