AD676

AD676 16-Bit 100 kSPS Sampling ADC

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LOGIC & TIMING CAL DAC LEVEL TRANSLATORS BIT 1 – BIT 16 VIN VREF AD676 SAR 28CLK 10 L A T C H REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 16-Bit 100 kSPS Sampling ADC AD676

FEATURES

On-Chip Sample-Hold Function Parallel Output Format

16 Bits No Missing Codes

61 LSB INL

–97 dB THD 90 dB S/(N+D)

1 MHz Full Power Bandwidth

The AD676 is a multipurpose 16-bit parallel output analog-to- digital converter which utilizes a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 µs total conversion time). Overall performance is opti- mized by digitally correcting internal nonlinearities through on-chip autocalibration. The AD676 circuitry is segmented onto two monolithic chips— a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package. The AD676 is specified for ac (or “dynamic”) parameters such as S/(N+D) Ratio, THD and IMD which are important in sig- nal processing applications. In addition, dc parameters are specified which are important in measurement applications. Tel: 617/329-4700 Fax: 617/326-8703 The AD676 operates from +5 V and ± 12 V supplies and typi- cally consumes 360 mW during conversion. The digital supply (VDD) is separated from the analog supplies (V CC, VEE) for re- duced digital crosstalk. An analog ground sense is provided for the analog input. Separate analog and digital grounds are also provided. The AD676 is available in a 28-pin plastic DIP or 28-pin side- brazed ceramic package. A serial-output version, the AD677, is available in a 16-pin 300 mil wide ceramic or plastic package.

AD676–SPECIFICATIONS AC SPECIFICATIONS AD676J/A AD676K/B Parameter Min Typ Max Min Typ Max Units Total Harmonic Distortion (THD) 2 @ 83 kSPS, TMIN to TMAX –96 –88 –97 –90 dB 0.0016 0.004 0.0014 0.003 % @ 100 kSPS, +25°C –96 –97 dB 0.0016 0.0014 % @ 100 kSPS, TMIN to TMAX –92 –92 dB 0.0025 0.0025 % Signal-to-Noise and Distortion Ratio (S/(N+D)) 2, 3 @ 83 kSPS, TMIN to TMAX 85 89 87 90 dB @ 100 kSPS, +25°C8 9 9 0 d B @ 100 kSPS, TMIN to TMAX 86 86 dB Peak Spurious or Peak Harmonic Component –98 –98 dB Intermodulation Distortion (IMD) 2nd Order Products –102 –102 dB 3rd Order Products –98 –98 dB Full Power Bandwidth 1 1 MHz Noise 160 160 µV rms DIGITAL SPECIFICATIONS Parameter Test Conditions Min Typ Max Units LOGIC INPUTS VIH High Level Input Voltage 2.4 V DD + 0.3 V VIL Low Level Input Voltage –0.3 0.8 V IIH High Level Input Current V IH = VDD –10 +10 µA IIL Low Level Input Current V IL = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage I OH = 0.1 mA V DD –1 V V IOH = 0.5 mA 2.4 V VOL Low Level Output Voltage I OL = 1.6 mA 0.4 V NOTES 1VREF = 10.0 V, (Conversion Rate (fs) = 83 kSPS, f IN = 1.0 kHz, V IN = –0.05 dB, Bandwidth = fs/2 unless otherwise indicated. All measurements referred to a 0 dB (20 V p-p) input signal. Values are post-calibration. 2For other input amplitudes, refer to Figure 13. 3For other input ranges/voltages reference values see Figure 12. 4fa = 1008 Hz. fb = 1055 Hz. See Definition of Specifications section and Figure 15. Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1 (for all grades TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%) REV. A–2–

Parameter Min Typ Max Min Typ Max Units TEMPERATURE RANGE J, K Grades 0 +70 0 +70 °C A, B Grades –40 +85 –40 +85 °C ACCURACY Resolution 16 16 Bits Integral Nonlinearity (INL) @ 83 kSPS, T MIN to TMAX ± 1 ± 1 ± 1.5 LSB @ 100 kSPS, +25°C ± 1 ± 1 LSB @ 100 kSPS, TMIN to TMAX ± 2 ± 2 LSB Differential Nonlinearity (DNL)–No Missing Codes 16 16 Bits Bipolar Zero Error2 (at Nominal Supplies) 0.005 0.005 % FSR Gain Error (at Nominal Supplies) @ 83 kSPS2 0.005 0.005 % FSR @ 100 kSPS, +25°C 0.005 0.005 % FSR @ 100 kSPS2 0.01 0.01 % FSR Temperature Drift, Bipolar Zero 3 % FSR J, K Grades 0.0015 0.0015 % FSR A, B Grades 0.003 0.003 % FSR Temperature Drift, Gain J, K Grades 0.0015 0.0015 % FSR A, B Grades 0.003 0.003 % FSR VOLTAGE REFERENCE INPUT RANGE 4 (VREF)5 1 0 5 1 0V ANALOG INPUT5 Input Range (VIN) ± VREF ± VREF V Input Impedance * * Input Settling Time 2 2 µs Input Capacitance During Sample 50* 50* pF Aperture Delay 6 6 ns Aperture Jitter 100 100 ps POWER SUPPLIES Power Supply Rejection VCC = +12 V ± 5% ± 1 ± 1 LSB VEE = –12 V ± 5% ± 1 ± 1 LSB VDD = +5 V ± 10% ± 1 ± 1 LSB Operating Current ICC 14.5 18 14.5 18 mA IEE 14.5 18 14.5 18 mA IDD 25 25 m A Power Consumption 360 480 360 480 mW NOTES 1VREF = 5.0 V, Conversion Rate = 83 kSPS unless otherwise noted. Values are post-calibration. 2Values shown apply to any temperature from T MIN to TMAX after calibration at that temperature. 3Values shown are based upon calibration at +25 °C with no additional calibration at temperature. Values shown are the worst case variation from the value at +25 °C. 4See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 12 for dynamic performance with other reference voltage values. 5See “APPLICATIONS” section for recommended input buffer circuit. *For explanation of input characteristics, see “ANALOG INPUT” section. Specifications subject to change without notice. (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)1 AD676 REV. A –3–

REV. A –5– ORDERING GUIDE Package Model Temperature Range 1 S/(N+D) Max INL Package Description Option 2 AD676JD 0 °C to +70°C 85 dB Ceramic 28-Pin DIP D-28 AD676KD 0 °C to +70°C 87 dB ± 1.5 LSB Ceramic 28-Pin DIP D-28 AD676AD –40 °C to +85°C 85 dB Ceramic 28-Pin DIP D-28 AD676BD –40 °C to +85°C 87 dB ± 1.5 LSB Ceramic 28-Pin DIP D-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the AD676/883 data sheet. 2D = Ceramic DIP. ABSOLUTE MAXIMUM RATINGS* Analog Inputs, VREF to AGND *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION The AD676 features input protection circuitry consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD676 has been classified as a Category 1 Device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment, and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam discharged to the destination socket before devices are removed. For further information on ESD Precaution. Refer to Analog Devices’ ESD Prevention Manual.

REV. A–6– PIN DESCRIPTION Pin Name Type Description 1–6 BIT 11-BIT 16 DO BIT 11–BIT 16 represent the six LSBs of data. 7 BUSY DO Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress. BUSY should be buffered when capacitively loaded. 8 CAL DI Calibration Control Pin (Asynchronous).

9 SAMPLE DI V

IN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the state of the internal sample-hold amplifier and the falling edge initiates conversion (see “Conver- sion Control” paragraph). During calibration, SAMPLE should be held LOW. If HIGH dur- ing calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6). 10 CLK DI Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion. 11 DGND P Digital Ground. 12 V CC P +12 V Analog Supply Voltage. 13 AGND P/AI Analog Ground. 14 AGND SENSE AI Analog Ground Sense. 15 V IN AI Analog Input Voltage. 16 V REF AI External Voltage Reference Input. 17 V EE P –12 V Analog Supply Voltage. Note: the lid of the ceramic package is internally connected to VEE. 18 V DD P +5 V Logic Supply Voltage. 19–28 BIT 1–BIT 10 DO BIT 1–BIT 10 represent the ten MSB of data. Type: AI = Analog Input DI = Digital Input DO = Digital Output P = Power TOP VIEW (Not to Scale) AD676 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) VDD VEE VREF VIN BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB) BUSY CAL SAMPLE CLK DGND VCC AGND AGND SENSE Package Pinout DIGITAL CHIP PAT GEN ALU RAM MICRO-CODED CONTROLLER AGND AGND SENSE CAL SAMPLE BUSY COMP ANALOG CHIP 16-BIT DAC INPUT BUFFERS LOGIC & TIMING CAL DAC LEVEL TRANSLATORS BIT 1 – BIT 16 VIN VREF AD676 SAR 28CLK 10 L A T C H Functional Block Diagram

REV. A –7– NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist frequency” of a converter is that input frequency which is one half the sampling frequency of the converter. TOTAL HARMONIC DISTORTION Total harmonic distortion (THD) is the ratio of the rms sum of the harmonic components to the rms value of a full-scale input signal and is expressed in percent (%) or decibels (dB). For in- put signals or harmonics that are above the Nyquist frequency, the aliased components are used. SIGNAL-TO-NOISE PLUS DISTORTION RATIO Signal-to-noise plus distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, includ- ing harmonics but excluding dc. GAIN ERROR The last transition should occur at an analog value 1.5 LSB be- low the nominal full scale (4.99977 volts for a ± 5 V range). The gain error is the deviation of the actual difference between the first and last code transition from the ideal difference between the first and last code transition. BIPOLAR ZERO ERROR Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. DIFFERENTIAL NONLINEARITY (DNL) In an ideal ADC, code transitions are one LSB apart. Differen- tial nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. INTEGRAL NONLINEARITY (INL) The ideal transfer function for an ADC is a straight line bisect- ing the center of each code drawn between “zero” and “full scale.” The point used as “zero” occurs 1/2 LSB before the most negative code transition. “Full scale” is defined as a level 1.5 LSB beyond the most positive code transition. Integral nonlinearity is the worst-case deviation of a code center average from the straight line. BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second or- der terms are (fa + fb) and (fa – fb), and the third order terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is –0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. APERTURE DELAY Aperture delay is the time required after SAMPLE pin is taken LOW for the internal sample-hold of the AD676 to open, thus holding the value of V lN. APERTURE JITTER Aperture jitter is the variation in the aperture delay from sample to sample. POWER SUPPLY REJECTION DC variations in the power supply voltage will affect the overall transfer function of the ADC, resulting in zero error and gain er- ror changes. Power supply rejection is the maximum change in either the bipolar zero error or gain error value. Additionally, there is another power supply variation to consider. AC ripple on the power supplies can couple noise into the ADC, resulting in degradation of dynamic performance. This is displayed in Figure 16. INPUT SETTLING TIME Settling time is a function of the SHA’s ability to track fast slewing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated conversion accuracy. Definition of Specifications–

REV. A–8– FUNCTIONAL DESCRIPTION The AD676 is a multipurpose 16-bit analog-to-digital converter and includes circuitry which performs an input sample/hold function, ground sense, and autocalibration. These functions are segmented onto two monolithic chips—an analog signal pro- cessor and a digital controller. Both chips are contained within the AD676 package. The AD676 employs a successive-approximation technique to determine the value of the analog input voltage. However, in- stead of the traditional laser-trimmed resistor-ladder approach, this device uses a capacitor-array, charge redistribution tech- nique. Binary-weighted capacitors subdivide the input sample to perform the actual analog-to-digital conversion. The capacitor array eliminates variation in the linearity of the device due to temperature-induced mismatches of resistor values. Since a ca- pacitor array is used to perform the data conversions, the sample/hold function is included without the need for additional external circuitry. Initial errors in capacitor matching are eliminated by an auto- calibration circuit within the AD676. This circuit employs an on-chip microcontroller and a calibration DAC to measure and compensate capacitor mismatch errors. As each error is deter- mined, its value is stored in on-chip memory (RAM). Subse- quent conversions use these RAM values to improve conversion accuracy. The autocalibration routine may be invoked at any time. Autocalibration insures high performance while eliminat- ing the need for any user adjustments and is described in detail below. The microcontroller controls all of the various functions within the AD676. These include the actual successive approximation algorithm, the autocalibration routine, the sample/hold opera- tion, and the internal output data latch. AUTOCALIBRATION The AD676 achieves rated performance without the need for user trims or adjustments. This is accomplished through the use of on-chip autocalibration. In the autocalibration sequence, sample/hold offset is nulled by internally connecting the input circuit to the ground sense cir- cuit. The resulting offset voltage is measured and stored in RAM for later use. Next, the capacitor representing the most significant bit (MSB) is charged to the reference voltage. This charge is then transferred to a capacitor of equal size (composed of the sum of the remaining lower weight bits). The difference in the voltage that results and the reference voltage represents the amount of capacitor mismatch. A calibration digital-to-ana- log converter (DAC) adds an appropriate value of error correc- tion voltage to cancel this mismatch. This correction factor is also stored in RAM. This process is repeated for each of the capacitors representing the remaining top eight bits. The accu- mulated values in RAM are then used during subsequent con- versions to adjust conversion results accordingly. As shown in Figure 1, when CAL is taken HIGH the AD676 in- ternal circuitry is reset, the BUSY pin is driven HIGH, and the ADC prepares for calibration. This is an asynchronous hard- ware reset and will interrupt any conversion or calibration cur- rently in progress. Actual calibration begins when CAL is taken LOW and completes in 85,530 clock cycles, indicated by BUSY going LOW. During calibration, it is preferable for SAMPLE to be held LOW. If SAMPLE is HIGH, diagnostic data will appear on Pins 5 and 6. This data is of no value to the user. The AD676 requires one clock cycle after BUSY goes LOW to complete the calibration cycle. If this clock cycle is not pro- vided, it will be taken from the first conversion, likely resulting in first conversion error. In most applications, it is sufficient to calibrate the AD676 only upon power-up, in which case care should be taken that the power supplies and voltage reference have stabilized first. If not calibrated, the AD676 accuracy may be as low as 10 bits. CONVERSION CONTROL The AD676 is controlled by two signals: SAMPLE and CLK, as shown in Figures 2a and 2b. It is assumed that the part has been calibrated and the digital I/O pins have the levels shown at the start of the timing diagram. A conversion consists of an input acquisition followed by 17 clock pulses which execute the 16-bit internal successive ap- proximation routine. The analog input is acquired by taking the SAMPLE line HIGH for a minimum sampling time of t S. The actual sample taken is the voltage present on V IN one aperture delay after the SAMPLE line is brought LOW, assuming the previous conversion has completed (signified by BUSY going LOW). Care should he taken to ensure that this negative edge is well defined and jitter free in ac applications to reduce the un- certainty (noise) in signal acquisition. With SAMPLE going LOW, the AD676 commits itself to the conversion—the input at V IN is disconnected from the internal capacitor array, BUSY goes HIGH, and the SAMPLE input will be ignored until the conversion is completed (when BUSY goes LOW). SAMPLE must be held LOW for a minimum period of time t SL. A period of time tSC after bringing SAMPLE LOW, the 17 CLK cycles are applied; CLK pulses that start before this period of time are ignored. BUSY goes HIGH t SB after SAMPLE goes LOW, sig- nifying that a conversion is in process, and remains HIGH until the conversion is completed. BUSY goes LOW during the 17th CLK cycle at the point where the data outputs have changed and are valid. The AD676 will ignore CLK after BUSY has gone LOW and the output data will remain constant until a new conversion is completed. The data can, therefore, be read any time after BUSY goes LOW and before the 17th CLK of the next conversion (see Figures 2a and 2b). The section on Micro- processor Interfacing discusses how the AD676 can be inter- faced to a 16-bit databus. Typically BUSY would be used to latch the AD676 output data into buffers or to interrupt microprocessors or DSPs. It is rec- ommended that the capacitive load on BUSY be minimized by driving no more than a single logic input. Higher capacitive loads such as cables or multiple gates may degrade conversion quality unless BUSY is buffered.

AD676 including the ADC and sample-hold amplifier (SHA). Figure 4. Grounding and Decoupling the AD676 power supply ripple effects (this is further detailed in Figure 7). attention to board layout. Trace impedance is a significant issue. close a small area, minimizing the inductive coupling of noise. circuit board construction is preferred.

REV. A –11– Using AGND SENSE to remotely sense the ground potential of the signal source can be useful if the signal has to be carried some distance to the A/D converter. Since all IC ground cur- rents have to return to the power supply and no ground leads are free from resistance and inductance, there are always some voltage differences from one ground point in a system to another. Over distance this voltage difference can easily amount to sev- eral LSBs (in a 10 V input span, 16-bit system each LSB is about 0.15 mV). This would directly corrupt the A/D input sig- nal if the A/D measures its input with respect to power ground (AGND) as shown in Figure 5a. To solve this problem the AD676 offers an AGND SENSE pin. Figure 5b shows how the AGND SENSE can be used to eliminate the problem in Figure 5a. Figure 5b also shows how the signal wires should be shielded in a noisy environment to avoid capacitive coupling. If inductive (magnetic) coupling is expected to be dominant such as where motors are present, twisted-pair wires should be used instead. The digital ground pin is the reference point for all of the digital signals that operate the AD676. This pin should be connected to the digital common point in the system. As Figure 4 illus- trated, the analog and digital grounds should be connected to- gether at one point in the system, preferably at the AD676. VIN AGND SOURCE VS GROUND LEAD IGROUND > 0 TO POWER SUPPLY GND AD676 DV Figure 5a. Input to the A/D Is Corrupted by IR Drop in Ground Leads: VIN = VS + ΔV VIN AGND SENSE AGND SOURCE VS SHIELDED CABLE GROUND LEAD IGROUND > 0 TO POWER SUPPLY GND AD676 Figure 5b. AGND SENSE Eliminates the Problem in Figure 5a. VOLTAGE REFERENCE The AD676 requires the use of an external voltage reference. The input voltage range is determined by the value of the refer- ence voltage; in general, a reference voltage of n volts allows an input range of ± n volts. The AD676 is specified for both 10 V and 5.0 V references. A 10 V reference will typically require support circuitry operated from ± 15 V supplies; a 5.0 V refer- ence may be used with ± 12 V supplies. Signal-to-noise perfor- mance is increased proportionately with input signal range. In the presence of a fixed amount of system noise, increasing the LSB size (which results from increasing the reference voltage) will increase the effective S/(N+D) performance. Figure 12 illustrates S/(N+D) as a function of reference voltage. In contrast, INL will be optimal at lower reference voltage values (such as 5 V) due to capacitor nonlinearity at higher voltage values. During a conversion, the switched capacitor array of the AD676 presents a dynamically changing current load at the voltage ref- erence as the successive-approximation algorithm cycles through various choices of capacitor weighting. (See the following sec- tion “Analog Input” for a detailed discussion of the V REF input characteristics.) The output impedance of the reference circuitry must be low so that the output voltage will remain sufficiently constant as the current drive changes. In some applications, this may require that the output of the voltage reference be buffered by an amplifier with low impedance at relatively high frequen- cies. In choosing a voltage reference, consideration should be made for selecting one with low noise. A capacitor connected between REF IN and AGND will reduce the demands on the reference by decreasing the magnitude of high frequency com- ponents required to be sourced by the reference. Figures 6 and 7 represent typical design approaches. VIN 10mF AGND C N 1.0mF +12V AD586 AD676 166

8 VREF

Figure 6. Figure 6 shows a voltage reference circuit featuring the 5 V out- put AD586. The AD586 is a low cost reference which utilizes a buried Zener architecture to provide low noise and drift. Over the 0°C to +70°C range, the AD586L grade exhibits less than 2.25 mV output change from its initial value at +25 °C. A noise- reduction capacitor, C N, reduces the broadband noise of the

REV. A–12– AD586 output, thereby optimizing the overall performance of the AD676. It is recommended that a 10 µF to 47 µF high qual- ity tantalum capacitor be tied between the V REF input of the AD676 and ground to minimize the impedance on the reference. +15V +5V –15V 100µF 100µF 100µF AD676 10µF 10µF 0.1µF 0.1µF 0.1µF 78L12 79L12 0.01µF 0.01µF VREF VDD VCC VEE VIN VO NRGND 10µF 0.1µF 1µF AD587 10µF 1517 VIN VIN 10Ω 10Ω 10Ω 10Ω Figure 7. Using the AD676 with ± 10 V input range (VREF = 10 V) typi- cally requires ± 15 V supplies to drive op amps and the voltage reference. If ± 12 V is not available in the system, regulators such as 78L12 and 79L12 can be used to provide power for the AD676. This is also the recommended approach (for any input range) when the ADC system is subjected to harsh environ- ments such as where the power supplies are noisy and where voltage spikes are present. Figure 7 shows an example of such a system based upon the 10 V AD587 reference, which provides a 300 µV LSB. Circuitry for additional protection against power supply disturbances has been shown. A 100 µF capacitor at each regulator prevents very large voltage spikes from entering the regulators. Any power line noise which the regulators cannot eliminate will be further filtered by an RC filter (10 Ω /10 µF) having a –3 dB point at 1.6 kHz. For best results the regulators should be within a few centimeters of the AD676. ANALOG INPUT As previously discussed, the analog input voltage range for the AD676 is ± VREF. For purposes of ground drop and common mode rejection, the VIN and VREF inputs each have their own ground. VREF is referred to the local analog system ground (AGND), and VIN is referred to the analog ground sense pin (AGND SENSE) which allows a remote ground sense for the input signal. The AD676 analog inputs (V IN, VREF and AGND SENSE) ex- hibit dynamic characteristics. When a conversion cycle begins, each analog input is connected to an internal, discharged 50 pF capacitor which then charges to the voltage present at the corre- sponding pin. The capacitor is disconnected when SAMPLE is taken LOW, and the stored charge is used in the subsequent conversion. In order to limit the demands placed on the external source by this high initial charging current, an internal buffer amplifier is employed between the input and this capacitance for a few hundred nanoseconds. During this time the input pin ex- hibits typically 20 k Ω input resistance, 10 pF input capacitance and ± 40 µA bias current. Next, the input is switched directly to the now precharged capacitor and allowed to fully settle. During this time the input sees only a 50 pF capacitor. Once the sample is taken, the input is internally floated so that the external input source sees a very high input resistance and a parasitic input ca- pacitance of typically only 2 pF. As a result, the only dominant input characteristic which must be considered is the high cur- rent steps which occur when the internal buffers are switched in and out. In most cases, these characteristics require the use of an external op amp to drive the input of the AD676. Care should he taken with op amp selection; even with modest loading conditions, most available op amps do not meet the low distortion require- ments necessary to match the performance capabilities of the AD676. Figure 8 represents a circuit, based upon the AD845, recommended for low noise, low distortion ac applications. For applications optimized more for low bias and low offset than speed or bandwidth, the AD845 of Figure 8 may be replaced by the OP27. 499W 1kW +12V –12V AD845 0.1mF 0.1mF AGND AGND SENSE –5V INPUT 1kW AD676 3 4

6 VIN

Figure 8.

ac performance under a variety of conditions. minimize its overall affect. the bandwidth of interest may be eliminated. self as a limit to the theoretical signal-to-noise ratio achievable. trum to eliminate undesired frequencies. by the AD676 used with a 10 V reference. Figure 9. Distribution of Codes from 1000 Conversions, would have a standard deviation of 0.25 LSBs.

Figure 12. S/(N+D) and THD vs. V REF Figure 14. 4096 Point FFT at 96 kSPS, f IN = 1.06 kHz Figure 13. S/(N+D) and THD vs. Input Amplitude Figure 15. IMD Plot for f IN = 1008 Hz (fa),

1055 Hz (fb) at 96 kSPS

Figure 16. AC Power Supply Rejection (f IN = 1.06 kHz)

REV. A–16– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Ceramic DIP Package (D-28) 0.225 (5.72) MAX 0.150 (3.81) MIN 0.100 (2.54) BSC 1.490 (37.85) MAX 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.610 (15.49) 0.500 (12.70) 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) 0.005 (0.13) MIN 0.100 (2.54) MAX 0.026 (0.66) 0.014 (0.36) C1679–24–7/92PRINTED IN U.S.A.