AD674BKN

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–12V/–15V SUPPL Y VEE BIPOLAR OFFSET BIPOFF 10V SP AN INPUT 10VIN 20V SP AN INPUT 20VIN ST A TUS STS DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DIGIT AL COMMON DC CONTROL VOLTAGE DIVIDER N Y B B L E A MSB S T A T E O U T P U T B U F F E R S LSB N Y B B L E B N Y B B L E C CLOCK SAR 12 10V REF COMP I DAC +199.95 k/H9024 DAC N VEE I REF DIGIT AL DATA OUTPUTS REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Complete 12-Bit A/D Converters AD674B /AD774B

FEATURES

Complete Monolithic 12-Bit A/D Converters with Reference, Clock, and Three-State Output Buffers Industry Standard Pinout High Speed Upgrades for AD574A 8- and 16-Bit Microprocessor Interface 8 /H9262s (Max) Conversion Time (AD774B) 15 /H9262s (Max) Conversion Time (AD674B) /H115505 V, /H1155010 V, 0 V–10 V, 0 V–20 V Input Ranges Commercial, Industrial, and Military Temperature Range Grades MIL-STD-883-Compliant Versions Available PRODUCT DESCRIPTION The AD674B and AD774B are complete 12-bit successive- approximation analog-to-digital converters with three-state output buffer circuitry for direct interface to 8- and 16-bit microprocessor busses. A high-precision voltage reference and clock are included on chip, and the circuit requires only power supplies and control signals for operation. The AD674B and AD774B are pin-compatible with the indus- try standard AD574A, but offer faster conversion time and bus- access speed than the AD574A and lower power consumption. The AD674B converts in 15 µs (maximum) and the AD774B converts in 8 µs (maximum). The monolithic design is implemented using Analog Devices’ BiMOS II process allowing high-performance bipolar analog circuitry to be combined on the same die with digital CMOS logic. Offset, linearity, and scaling errors are minimized by active laser trimming of thin-film resistors. Five different grades are available. The J and K grades are specified for operation over the 0 °C to 70°C temperature range. The A and B grades are specified from –40°C to +85°C, the T grade is specified from –55 °C to +125 °C. The J and K grades are available in a 28-lead plastic DIP or 28-lead SOIC. All other grades are available in a 28-lead hermetically sealed ceramic DIP. PRODUCT HIGHLIGHTS 1. Industry Standard Pinout: The AD674B and AD774B use the pinout established by the industry standard AD574A. 2. Analog Operation: The precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges: 0 V to

10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to

+10 V bipolar. The AD674B and AD774B operate on +5 V and ±12 V or ±15 V power supplies. 3. Flexible Digital Interface: On-chip multiple-mode three-state output buffers and interface logic allow direct connection to most microprocessors. The 12 bits of output data can be read either as one 12-bit word or as two 8-bit bytes (one with 8 data bits, the other with 4 data bits and 4 trailing zeros). 4. The internal reference is trimmed to 10.00 V with 1% maxi- mum error and 10 ppm/ °C typical temperature coefficient. The reference is available externally and can drive up to 2.0 mA beyond the requirements of the converter and bipo- lar offset resistors. 5. The AD674B and AD774B are available in versions compli- ant with MIL-STD-883. Refer to the Analog Devices Mili- tary Products Databook or current AD674B/AD774B/883B data sheet for detailed specifications. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

J Grade K Grade A Grade B Grade T Grade Model (AD674B or AD774B) Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 12 12 Bits LINEARITY ERROR @ 25 °C /H115501 /H115501/2 /H115501 /H115501/2 /H115501/2 LSB TMIN to TMAX /H115501 /H115501/2 /H115501 /H115501/2 /H115501 LSB DIFFERENTIAL LINEARITY ERROR (Minimum Resolution for Which No Missing Codes are Guaranteed) 12 12 12 12 12 Bits UNIPOLAR OFFSET 1 @ 25°C /H115502 /H115502 /H115502 /H115502 /H115502 LSB BIPOLAR OFFSET 1 @ 25°C /H115506 /H115503 /H115506 /H115503 /H115503 LSB FULL-SCALE CALIBRATION ERROR 1, 2 @ 25°C (with Fixed 50 Ω Resistor TEMPERATURE RANGE 0 70 0 70 –40 +85 –40 +85 –55 +125 °C TEMPERATURE DRIFT 3 (Using Internal Reference) Unipolar /H115502 /H115501 /H115502 /H115501 /H115501 LSB Bipolar Offset /H115502 /H115501 /H115502 /H115501 /H115502 LSB Full-Scale Calibration /H115506 /H115502 /H115508 /H115505 /H115507 LSB POWER SUPPLY REJECTION Max Change in Full-Scale Calibration VCC = +15 V ± 1.5 V or +12 V ± 0.6 V /H115502 /H115501 /H115502 /H115501 /H115501 LSB VLOGIC = +5 V ± 0.5 V /H115501/2 /H115501/2 /H115501/2 /H115501/2 /H115501/2 LSB VEE = –15 V ± 1.5 V or –12 V ± 0.6 V /H115502 /H115501 /H115502 /H115501 /H115501 LSB ANALOG INPUT Input Ranges –10 +10 –10 +10 –10 +10 –10 +10 –10 +10 V Unipolar 0 10 0 10 0 10 0 10 0 10 V 0 20 0 20 0 20 0 20 0 20 V Input Impedance

10 V Span 3 5 73 5 73 5 73 5 73 5 7 kΩ

20 V Span 6 10 14 6 10 14 6 10 14 6 10 14 6 10 14 kΩ

IEE 10 14 10 14 10 14 10 14 10 14 mA POWER CONSUMPTION 220 375 220 375 220 375 220 375 220 375 mW4 175 175 175 175 175 mW 5 Output Current (External Load Should Not Change During the Conversion) NOTES 1Adjustable to zero. 2Includes internal voltage reference error. 3Maximum change from 25 °C value to the value at T MIN or TMAX. 4Tested with REF OUT tied to REF IN through 50 Ω resistor, V CC = +16.5 V, V EE = –16.5 V, V LOGIC = +5.5 V, and outputs in high-Z mode. 5Tested with REF OUT tied to REF IN through 50 Ω resistor, V CC = +12 V, V EE = –12 V, V LOGIC = +5 V, and outputs in high-Z mode. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test at T MIN, 25°C, and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. AD674B/AD774B–SPECIFICATIONS (T MIN to TMAX with VCC = +15 V /H11550 10% or +12 V /H11550 5%, VLOGIC = +5 V /H11550 10%, VEE = –15 V /H11550 10% or –12 V /H11550 5%, unless otherwise noted.) REV. C–2–

REV. C–4– AD674B/AD774B TIMING—STAND ALONE MODE (Figures 4a and 4b) J, K, A, B Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Unit Data Access Time t DDR 150 150 ns Low R/C Pulsewidth t HRL 50 50 ns STS Delay from R/ C tDS 200 225 ns Data Valid After R/ C Low t HDR 25 25 ns STS Delay After Data Valid t HS 30 200 600 30 200 600 ns High R/C Pulsewidth t HRH 150 150 ns Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. R/C STS DB11–DB0 DATA VALID DATA VALID tHRL tDS HIGH–Z tHStHDR tC Flgure 4a. Standalone Mode Timing Low Pulse R/ C R/C STS DB11–DB0 HIGH–Z HIGH –ZDATA VALID tHRH tDS tDDR tHDR tC tHL Figure 4b. Standalone Mode Timing High Pulse for R/ C WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Conversion INL Package Package Modell Temperature Time (max) (T MIN to TMAX) Description Option 2 AD674BJN 0 °C to 70°C 15 µs ±1 LSB Plastic DIP N-28 AD674BKN 0 °C to 70°C 15 µs ±1/2 LSB Plastic DIP N-28 AD674BAR –40°C to +85°C 15 µs ±1 LSB Plastic SOIC R-28 AD674BBR –40°C to +85°C 15 µs ±1/2 LSB Plastic SOIC R-28 AD674BAD –40°C to +85°C 15 µs ±1 LSB Ceramic DIP D-28 AD674BBD –40°C to +85°C 15 µs ±1/2 LSB Ceramic DIP D-28 AD674BTD –55°C to +125°C 15 µs ±1 LSB Ceramic DIP D-28 AD774BJN 0 °C to 70°C8 µs ±1 LSB Plastic DIP N-28 AD774BKN 0 °C to 70°C8 µs ±1/2 LSB Plastic DIP N-28 AD774BAR –40°C to +85°C8 µs ±1 LSB Plastic SOIC R-28 AD774BBR –40°C to +85°C8 µs ±1/2 LSB Plastic SOIC R-28 AD774BAD –40°C to +85°C8 µs ±1 LSB Ceramic DIP D-28 AD774BBD –40°C to +85°C8 µs ±1/2 LSB Ceramic DIP D-28 AD774BTD –55°C to +125°C8 µs ±1 LSB Ceramic DIP D-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or the current AD674B/ AD774B/883B data sheet. 2N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.

REV. C –5– DEFINITION OF SPECIFICATIONS Linearity Error Linearity error refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for 10 V span) before the first code transition (all zeroes to only the LSB “on”). “Full scale” is defined as a level 1 1/2 LSB beyond the last code tran- sition (to all ones). The deviation of a code from the true straight line is measured from the middle of each particular code. The K, B, and T grades are guaranteed for maximum nonlinear- ity of ± 1/2 LSB. For these grades, this means that an analog value that falls exactly in the center of a given code width will result in the correct digital output code. Values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. The J and A grades are guaranteed to ± 1 LSB max error. For these grades, an analog value that falls within a given code width will result in either the correct code for that region or either adjacent one. Note that the linearity error is not user adjustable. Differential Linearity Error (No Missing Codes) A specification that guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus every code must have a finite width. The AD674B and AD774B guarantee no missing codes to 12-bit resolution, requiring that all 4096 codes must be present over the entire operating temperature ranges. Unipolar Offset The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual transition from that point. This offset can be adjusted as discussed later. The unipolar offset temperature coefficient specifies the maximum change of the transition point over tem perature, with or without external adjustment. Bipolar Offset In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. Quantization Uncertainty Analog-to-digital converters exhibit an inherent quantization uncertainty of ±1/2 LSB. This uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of given resolution. Left-Justified Data The output data format is left-justified. This means that the data represents the analog input as a fraction of full scale, rang- ing from 0 to 4095/4096. This implies a binary point 4095 to the left of the MSB. Full-Scale Calibration Error The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 LSB below the nominal full scale (9.9963 V for 10.000 V full scale). The full-scale cali- bration error is the deviation of the actual level at the last transi- tion from the ideal level. This error, which is typically 0.05% to 0.1% of full scale, can be trimmed out as shown in Figures 7 and 8. The full-scale calibration error over temperature is given with and without the initial error trimmed out. The temperature coefficients for each grade indicate the maximum change in the full-scale gain from the initial value using the internal 10 V reference. Temperature Drift The temperature drift for full-scale calibration, unipolar offset, and bipolar offset specifies the maximum change from the initial (25°C) value to the value at T MIN or TMAX. Power Supply Rejection The standard specifications assume use of +5.00 V and ±15.00 V or ±12.00 V supplies. The only effect of power supply error on the performance of the device will be a small change in the full-scale calibration. This will result in a linear change in all low-order codes. The specifications show the maximum full- scale change from the initial value with the supplies at the various limits. Code Width A fundamental quantity for A/D converter specifications is the code width. This is defined as the range of analog input values for which a given digital output code will occur. The nominal value of a code width is equivalent to 1 least significant bit (LSB) of the full-scale range or 2.44 mV out of 10 V for a 12-bit ADC. AD674B/AD774B

REV. C–6– AD674B/AD774B PIN FUNCTION DESCRIPTIONS Symbol Pin No. Type * Name and Function AGND 9 P Analog Ground (Common) A0 4 DI Byte Address/Short Cycle. If a conversion is started with A 0 Active LOW, a full 12-bit conversion cycle is initiated. If A 0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle results. During Read (R/ C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits, and A0 = HIGH enables DB3 –DB0 and sets DB7–DB4 = 0. BIP OFF 12 AI Bipolar Offset. Connect through a 50 Ω resistor to REF OUT for bipolar operation or to Analog Common for unipolar operation. CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation. CS 3 DI Chip Select. Chip Select is Active LOW. DB11–DB8 27 –24 DO Data Bits 11 through 8. In the 12-bit format (see 12/ 8 and A0 pins) these pins provide the upper 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A 0 is LOW and are disabled when A0 is HIGH. DB7–DB4 23 –20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the 8-bit format they provide the middle 4 bits when A 0 is LOW and all zeroes when A 0 is HIGH. DB3–DB0 19 –16 DO Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of data when A0 is HIGH; they are disabled when A 0 is LOW. DGND 15 P Digital Ground (Common) REF OUT 8 AO 10 V Reference Output R/C 5 DI Read/Convert. In the full control mode R/ C is Active HIGH for a read operation and Active LOW for a convert operation. In the standalone mode, the falling edge of R/ C initiates a conversion. REF IN 10 AI Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation. STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is completed. V CC 7 P +12 V/+15 V Analog Supply VEE 11 P –12 V/–15 V Analog Supply VLOGIC 1 P 5 V Logic Supply 10 VIN 13 AI 10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the 20 V Span, 10 VIN should not be connected. 20 VIN 14 AI 20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using the 10 V Span, 20 VIN should not be connected. 12/8 2 DI The 12/ 8 pin determines whether the digital output data is to be organized as two 8-bit words (12/8 LOW) or a single 12-bit word (12/ 8 HIGH). *Types: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power PIN CONFIGURATION TOP VIEW (Not to Scale) AD674B OR AD774B VLOGIC CS R/C CE VCC REF OUT AGND REF IN VEE BIP OFF

10 VIN

20 VIN

DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DGND

and manufacturing is preferred.

0 TO 10V

0 TO 20V

Figure 7. Unipolar Input Connections in many applications, no calibration trimming will be required. error and ±0.25% (10 LSB) max full-scale error are guaranteed. film resistor should be connected between Pin 8 and Pin 10. gain trim de scribed below is now done with these trimmers. level of +1/2 LSB (1.22 mV for 10 V range). ±15 mV of offset trim range. The connections for bipolar ranges are shown in Figure 8. Figure 8. Bipolar Input Connections erence point; digital power return is preferred.

Figure 9. Equivalent Internal Logic Circuitry logic circuitry is shown in Figure 9. is started with A0 low, a full 12-bit conversion cycle is initiated. 0 = 0) or the 4 LSBs (A 0 = 1) are enabled. 8-bit buses without the need for external three-state buffers. An output signal, STS, indicates the status of the converter. when the conversion cycle is complete. resulting in system bus contention.

mode, resulting in improved accuracy. return to valid logic levels after the conversion cycle is completed. returns low 600 ns after data is valid. the data lines are enabled during the time when R/ C is HIGH. end of the conversion cycle. convert start, a shorter 8-bit conversion cycle results. external three-state buffers. tions. First, a write to the ADC address initiates a conversion. 12 most significant or 12 least significant bits of the data bus. four trailing zeroes, thus eliminating bit masking instructions. Figure 10. Data Format for 8-Bit Bus

REV. C –11– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Ceramic DIP Package (D-28) 1.42 (36.07) 1.40 (35.56) 0.59 0.01 (14.98) 0.050 (12.83) 0.085 (2.16) 0.017 0.003 (0.43) +– 0.1 (2.54) 0.047 0.007 (1.19) 0.095 (2.41) 0.050 0.010 (1.27) 0.6 (15.24) 0.010 0.002 (0.254 0.05)+– 0.145 0.02 (3.68) 0.08 (2.0) 0.125 MIN (3.17)SEATING PLANE o 0.05 (1.27) 0.045 (1.14) 28-Lead Plastic DIP Package (N-28) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24) 11 4 PIN 1 0.580 (14.73) 0.485 (12.32) 1.565 (39.70) 1.380 (35.10) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) MAX 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) MAX 28-Lead Wide Body SOIC Package (R-28) 0.0125 (0.32) 0.0091 (0.23) 8/H11543 0/H11543 0.0291 (0.74) 0.0098 (0.25)/H11547 45/H11543 0.0500 (1.27) 0.0157 (0.40) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 28 15 141 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40)PIN 1 AD674B/AD774B

REV. C–12– AD674B/AD774B C00808-0-4/02(C) PRINTED IN U.S.A.

Revision History

Data Sheet changed from REV. B to REV. C.