AD671 AD | Alldatasheet
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AIN BPO/UPO ENCODE REF IN ACOM DCOM LATCHES CORRECTION LOGIC RANGE SELECT X4 COARSE 4-BIT FLASH 8-BIT LADDER MATRIX FINE 4-BIT FLASH AD671 3 4 DAC OTR MSB BIT1-12 DAV 21 16 19 23 22 24 17 18 3-BIT FLASH DAC3-BIT FLASH 14 13 1512 1 VCC V LOGICEEV REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Monolithic 12-Bit
2 MHz A/D Converter
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
24-Pin “Skinny DIP” Package Conversion Time: 500 ns max—AD671J/K/S-500 Conversion Time: 750 ns max—AD671J/K/S-750 Low Power: 475 mW Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input Ranges ( 65 V) Twos Complement or Offset Binary Output Data Out-of-Range Indicator MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD671 is a high speed monolithic 12-bit A/D converter offering conversion rates of up to 2 MHz (500 ns conversion time). The combination of a merged high speed bipolar/CMOS process and a novel architecture results in a combination of speed and power consumption far superior to previously avail- able hybrid implementations. Additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. The AD671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. An on-chip timing generator pro- vides strobe pulses for each of the four internal flash cycles and assures adequate settling time for the interflash residue ampli- fier. A single ENCODE pulse is used to control the converter. The performance of the AD671 is made possible by using high speed, low noise bipolar circuitry in the linear sections and low power CMOS for the logic sections. Analog Devices’ ABCMOS-1 process provides both high speed bipolar and 2-micron CMOS devices on a single chip. Laser trimmed thin-film resistors are used to provide accuracy and temperature stability. The AD671 is available in two conversion speeds and perfor- mance grades. The AD671J and K grades are specified for op- eration over the 0 °C to +70°C temperature range. The AD671S grades are specified for operation over the –55 °C to +125°C temperature range. All grades are available in a 0.300 inch wide 24-pin ceramic DIP. The J and K grades are also available in a 24-pin plastic DIP. PRODUCT HIGHLIGHTS 1. The AD671 offers a single chip 2 MHz analog-to-digital conversion function in a space saving 24-pin DIP. 2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo- lar, and –5 V to +5 V bipolar, selected by pin strapping. In- put resistance is 1.5 k Ω . Power supplies are +5 V and –5 V, and typical power consumption is less than 500 mW. 3. The external +5 V reference can be chosen to suit the dc ac- curacy and temperature drift requirements of the application. 4. Output data is available in unipolar, bipolar offset or bipolar twos complement binary format. 5. An OUT OF RANGE output bit indicates when the input signal is beyond the AD671’s input range. 6. The AD671 is available in versions compliant with the MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD671/883B data sheet for detailed specifications.
AD671–SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 610%, VEE = –5 V 6 5%, VREF = +5.000 V, unless otherwise noted) AD671J/S-500 AD671K-500 Parameter Min Typ Max Min Typ Max Units RESOLUTION 12 12 Bits ACCURACY (+25°C) Integral Nonlinearity (INL) TMIN to TMAX 64 62 LSB Differential Nonlinearity (DNL) TMIN to TMAX 10 11 Bits No Missing Codes 10 Bits Guaranteed 11 Bits Guaranteed Unipolar Offsetl 64 64 LSB Bipolar Zerol 610 610 LSB Gain Error2 0.1 0.25 0.1 0.25 % FSR TEMPERATURE COEFFICIENTS 3 Unipolar Offset 610 610 ppm/°C Bipolar Zero 615 615 ppm/°C Gain Error 620 620 ppm/°C ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 Volts Unipolar 0+ 5 0+ 5 Volts 0 +10 0 +10 Volts Input Resistance Input Capacitance 10 10 pF POWER SUPPLIES Power Supply Rejection 4 VCC (+5 V ± 0.25 V) 61 61 LSB VLOGIC (+5 V ± 0.5 V) 61 61 LSB VEE (–5 V ± 0.25 V) 61 61 LSB Operating Voltages VCC +4.75 +5.25 +4.75 +5.25 Volts VLOGIC +4.5 +5.5 +4.5 +5.5 Volts VEE –5.25 –4.75 –5.25 –4.75 Volts Operating Current ICC 46 56 46 56 mA ILOGIC 5 3 6 3 6 mA IEE 46 56 46 56 mA POWER CONSUMPTION 475 621 475 621 mW TEMPERATURE RANGE Specified (J/K) 0 +70 0 +70 °C Specified (S) –55 +125 °C NOTES 1Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information. 2Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges. 325°C to TMIN and 25°C to TMAX. 4Change in gain error as a function of the dc supply voltage. 5Tested under static conditions. See Figure 12 for typical curves of I LOGIC vs. Conversion Rate and Output Loading. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. REV. B–2–
Parameter Min Typ Max Min Typ Max Units RESOLUTION 12 12 Bits ACCURACY (+25°C) Integral Nonlinearity (INL) TMIN to TMAX (J) 62 61.5 LSB TMIN to TMAX (S) 62.5 LSB Differential Nonlinearity (DNL) TMIN to TMAX 11 12 Bits No Missing Codes 11 Bits Guaranteed 12 Bits Guaranteed Unipolar Offset l 64 64 LSB Bipolar Zerol 610 610 LSB Gain Error2 0.1 0.25 0.1 0.25 % FSR TEMPERATURE COEFFICIENTS 3 Unipolar Offset 610 610 ppm/°C Bipolar Zero 615 615 ppm/°C Gain Error 620 620 ppm/°C ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 Volts Unipolar 0+ 5 0+ 5 Volts 0 +10 0 +10 Volts Input Resistance Input Capacitance 10 10 pF POWER SUPPLIES Power Supply Rejection 4 VCC (+5 V ± 0.25 V) 61 61 LSB VLOGIC (+5 V ± 0.5 V) 61 61 LSB VEE (–5 V ± 0.25 V) 61 61 LSB Operating Voltages Vcc +4.75 +5.25 +4.75 +5.25 Volts VLOGIC +4.5 +5.5 +4.5 +5.5 Volts VEE –5.25 –4.75 –5.25 –4.75 Volts Operating Current ICC 46 56 46 56 mA ILOGIC 5 3 6 3 6 mA IEE 46 56 46 56 mA POWER CONSUMPTION 475 621 475 621 mW TEMPERATURE RANGE Specified (J/K) 0 +70 0 +70 °C Specified (S) –55 +125 °C NOTES 1Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information. 2Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges. 325°C to TMIN and 25°C to TMAX. 4Change in gain error as a function of the dc supply voltage. 5Tested under static conditions. See Figure 12 for typical curves of I LOGIC vs. Conversion Rate and Output Loading. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. AD671 DC SPECIFICATIONS (TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, VREF = +5.000 V, unless otherwise noted) REV. B –3–
specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. 1tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin. 2tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin. Figure 1. AD671 Timing Diagrams
REV. B –5– ORDERING GUIDE Temperature Package Modell Linearity Range Options 2 AD671JD-500 ± 4 LSB 0 °C to +70°C D-24A AD671KD-500 ± 2 LSB 0 °C to +70°C D-24A AD671JD-750 ± 2 LSB 0 °C to +70°C D-24A AD671KD-750 ± 1.5 LSB 0 °C to +70°C D-24A AD671SD-500 ± 4 LSB –55 °C to +125°C D-24A AD671SD-750 ± 2.5 LSB –55 °C to +125°C D-24A NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD671/883 data sheet. 2D = Ceramic DIP. ABSOLUTE MAXIMUM RATINGS* With Respect Parameter to Min Max Units VCC ACOM –0.5 +6.5 Volts VEE ACOM –6.5 +0.5 Volts VLOGIC DCOM –0.5 +6.5 Volts ACOM DCOM –1.0 +1.0 Volts V CC VLOGIC –6.5 +6.5 Volts ENCODE DCOM –0.5 V LOGIC +0.5 Volts REF IN ACOM –0.5 V CC +0.5 Volts AIN, BPO/UPO ACOM –6.5 11.0 Volts Junction Temperature +175 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C Power Dissipation 1000 mW *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. B–6– AD671 PIN DESCRIPTION Symbol Pin Type Name and Function ACOM 22 P Analog Ground. AIN 20 AI Analog Input Signal. BIT1 (MSB) 12 DO Most Significant Bit. BIT2–BIT11 11–2 DO Data Bits 2–11. BIT12 (LSB) 1 DO Least Significant Bit. BPO/UPO 21 AI Bipolar or Unipolar Configuration Pin. Connect to AIN for 0 V to +5 V Span, to ACOM for 0 V to +10 V Span and to REF IN for –5 V to +5 V Span. DAV 15 DO Data Available Output. The Rising Edge of DAV Indicates an End of Conversion and Can Be Used to Latch Current Data into an External Register. The Falling Edge of DAV Can Be Used to Latch Previous Data into an External Register. DCOM 18 P Digital Ground. ENCODE 16 DI The AD671 Starts a Conversion on the Rising Edge of the ENCODE Pulse. MSB 13 DO Inverted Most Significant Bit. Provides Twos Complement Output Data Format. OTR 14 DO Out of Range Is Active HIGH when the analog input is beyond the input range of the converter. REF IN 19 AI +5 V Reference Input. V CC 23 P +5 V Analog Power. VEE 24 P –5 V Analog Power. VLOGIC 17 P +5 V Digital Power. TYPE: AI = Analog Input DI = Digital Input DO = Digital Output P = Power CONNECTION DIAGRAM PINOUT 12 13 TOP VIEW (Not to Scale) AD671 BIT12 (LSB) BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 (MSB) MSB OTR DAV ENCODE DCOM REF IN AIN BPO/UPO ACOM V CC VEE VLOGIC
before the first code transition (all zeros to only the LSB on). side transition of each particular code to the true straight line. or without external adjustments. supplies at the various limits. 1.8 dB, where N is equal to the effective number of bits. pressed as a percentage or in decibels. generator circuit accurately controls all internal timing.
0 TO 10V+
0 TO 5V+
Figure 2. Input Range Connections
Figure 5. AD586 as Reference Input for AD671 proper layout, grounding and decoupling techniques. should be reviewed before laying out a printed circuit board. Figure 6. AD671 Grounding and Decoupling Capacitor Values 0.1 µF (Ceramic) and 10 µF (Tantalum). mended to Reduce Lead Inductance). Supply Pins to Respective Ground Plane. Connected to the Analog Power Supply. Connected to the Digital Power Supply. Ground Connected Together Once at the AD671. Figure 7. Unipolar (0 V to +10 V) Calibration
proximately ± 50 mV of offset trim range.
0 TO +5V
Figure 8. Unipolar (0 V to +5 V) Calibration
- The AD588 is configured to provide dual +5 V outputs. Pro-
+5 V BPO/UPO input for the bipolar offset trim. Figure 9. Bipolar ( ±5 V) Calibration ures 20, 21 and 22 for PCB layout recommendations. Figure 10. AD671 to Output Latches eliminating gain selection iterations.
Figure 11. Overrange or Underrange Logic
0 V 0000 0000 0000 0
0 V 1000 0000 0000 0
1Voltages listed are with offset and gain errors adjusted to zero. Figure 12. I LOGIC vs. Conversion Rate for Various rate for various capacitive loads on the digital outputs.
REV. B–16– C1426a–10–9/91PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Plastic DIP (Suffix N) 24-Pin Ceramic DIP (Suffix D) PIN 1 0.295 6 0.01 (7.49 6 0.26) 0.175 (4.45) 0.018 6 0.002 (0.46 6 0.05) TYP 1.200 6 0.012 (30.48 6 0.31) 0.05 (1.27) TYP SEATING PLANE 0.100 6 0.005 (2.54 6 0.13) 0.300 6 0.010 (7.49 6 0.25) 0.010 + 0.002 –0.001 (0.025+ 0.05 ) –0.03 0.085 6 0.009 (2.16 6 0.23) 1.100 6 0.005 (27.94 6 0.13) TOLL NON ACCUM NOTES 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MIL-M-385 TO REQUIREMENTS.