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14-Bit, 40 MSPS/65 MSPS Analog-to-Digital Converter AD6644 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

65 MSPS guaranteed sample rate

40 MSPS version available

Sampling jitter < 300 fs 100 dB multitone SFDR

1.3 W power dissipation

Differential analog inputs Pin compatible to AD6645 Twos complement digital output format

3.3 V CMOS compatible

Data-ready for output latching

APPLICATIONS

Multichannel, multimode receivers AMPS, IS-136, CDMA, GSM, WCDMA Single channel digital receivers Antenna array processing Communications instrumentation Radar, infrared imaging Instrumentation GENERAL DESCRIPTION The AD6644 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (TH) and reference, are included on- chip to provide a complete conversion solution. The AD6644 provides CMOS-compatible digital outputs. It is the third generation in a wideband ADC family, preceded by the AD9042 (12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling). Designed for multichannel, multimode receivers, the AD6644 is part of the Analog Devices, Inc. new SoftCell® transceiver chipset. The AD6644 achieves 100 dB multitone, spurious-free dynamic range (SFDR) through the Nyquist band. This break- through performance eases the burden placed on multimode digital receivers (software radios) which are typically limited by the ADC. Noise performance is exceptional; typical signal-to- noise ratio is 74 dB. The AD6644 is also useful in single channel digital receivers designed for use in wide-channel bandwidth systems (CDMA, WCDMA). With oversampling, harmonics can be placed outside the analysis bandwidth. Oversampling also facilitates the use of decimation receivers (such as the AD6620), allowing the noise floor in the analysis bandwidth to be reduced. By replacing traditional analog filters with predictable digital components, modern receivers can be built using fewer RF components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability. The AD6644 is built on the Analog Devices high speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-lead plastic low profile quad flat package (LQFP) specified from – 25°C to +85°C. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate is 65 MSPS. 2. Fully differential analog input stage. 3. Digital outputs can be run on 3.3 V supply for easy interface to digital ASICs. 4. Complete solution: reference and track-and-hold. 5. Packaged in small, surface-mount, plastic, 52-lead LQFP . FUNCTIONAL BLOCK DIAGRAM AD6644 AIN AIN VREF ENCODE ENCODE GND DMID OVR DRY D13 (MSB) D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) ADC3TH5TH4 DAC2ADC2 TH3A2 DAC1 DIGITAL ERROR CORRECTION LOGIC TH2 ADC1 TH1A1 2.4V INTERNAL TIMING DVCCAVCC 00971-001 Figure 1.

AD6644* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes

  • AN-1142: Techniques for High Speed ADC PCB Layout
  • AN-282: Fundamentals of Sampled Data Systems
  • AN-302: Exploit Digital Advantages in an SSB Receiver
  • AN-345: Grounding for Low-and-High-Frequency Circuits
  • AN-501: Aperture Uncertainty and ADC System Performance
  • AN-586: LVDS Outputs for High Speed A/D Converters
  • AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated
  • AN-737: How ADIsimADC Models an ADC
  • AN-741: Little Known Characteristics of Phase Noise
  • AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
  • AN-807: Multicarrier WCDMA Feasibility
  • AN-808: Multicarrier CDMA2000 Feasibility
  • AN-835: Understanding High Speed ADC Testing and Evaluation
  • AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

  • AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
  • AD6644: 14-Bit, 40 MSPS/65 MSPS Analog-to-Digital Converter Data Sheet TOOLS AND SIMULATIONS
  • Visual Analog REFERENCE MATERIALS Technical Articles
  • Buffer Adapts Single-ended Signals for Differential Inputs
  • Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
  • DNL and Some of its Effects on Converter Performance
  • MS-2210: Designing Power Supplies for High Speed ADC
  • Redefining the Role of ADCs in Wireless
  • Soft Radio Runs into Hard Standards DESIGN RESOURCES
  • AD6644 Material Declaration
  • PCN-PDN Information
  • Quality And Reliability
  • Symbols and Footprints DISCUSSIONS View all AD6644 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. D | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

8/07—Rev. C to Rev. D Changes to Noise (for Any Range Within the ADC) Definition .. 13 5/03—Data Sheet changed from Rev. B to Rev. C 3/03—Data Sheet changed from Rev. A to Rev. B 3/03—Data Sheet changed from Rev. 0 to Rev. A

Rev. D | Page 3 of 24 SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; TMIN = –25°C, TMAX = +85°C, unless otherwise noted. Table 1. AD6644AST-40 AD6644AST-65 Parameter Temp Test Level1 Min Typ Max Min Typ Max Unit RESOLUTION 14 14 Bits ACCURACY No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II −10 +3 +10 −10 +3 +10 mV Gain Error Full II −10 −6 +10 −10 –6 +10 % FS Integral Nonlinearity (INL) Full V ±0.50 ±0.50 LSB TEMPERATURE DRIFT Offset Error Full V 10 10 ppm/°C Gain Error Full V 95 95 ppm/°C POWER SUPPLY REJECTION RATIO (PSRR) Full V ±1.0 ±1.0 mV/V REFERENCE OUT (VREF) Full V 2.4 2.4 V ANALOG INPUTS (AIN, AIN) Differential Input Voltage Span Full V 2.2 2.2 V p-p Differential Input Resistance Full V 1 1 kΩ Differential Input Capacitance 25°C V 1.5 1.5 pF POWER SUPPLY Supply Voltage Supply Current IAVCC (AVCC = 5.0 V) Full II 245 276 245 276 mA IDVCC (DVCC = 3.3 V) Full II 30 36 30 36 mA Rise Time3 AVCC Full IV 15 ms POWER CONSUMPTION Full II 1.3 1.5 1.3 1.5 W 1 See the Explanation of Test Levels section. 3 Specified for dc supplies with linear rise time characteristics.

Rev. D | Page 4 of 24 DIGITAL SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; TMIN = −25°C, TMAX = +85°C, unless otherwise noted. Table 2. AD6644AST-40 AD6644AST-65 Parameter Temp Test Level 1 Min Typ Max Min Typ Max Unit ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage2 Full IV 0.4 0.4 V p-p Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25° C V 2.5 2.5 pF LOGIC OUTPUTS (D13 to D0, DRY, OVR) Logic Compatibility CMOS CMOS Logic 1 Voltage3 Full V 2.5 2.5 V Logic 0 Voltage3 Full V 0.4 0.4 V Output Coding Twos co mplement Twos complement DMID Full V DV CC/2 DV CC/2 V 1 See the Explanation of Test Levels section. 2 All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 18 for performance vs. encode power. 3 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrade performance. SWITCHING SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = –25°C, TMAX = +85°C, unless otherwise noted. Table 3. AD6644AST-40 AD6644AST-65 Parameter Temp Test Level 1 Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full II 40 65 MSPS Minimum Conversion Rate Full IV 15 15 MSPS ENCODE Pulse Width High Full IV 10 6.5 ns ENCODE Pulse Width Low Full IV 10 6.5 ns 1 See the Explanation of Test Levels section. AVCC = 5 V , DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, CLOAD = 10 Pf, unless otherwise noted. Table 4. AD6644AST-40/65 Parameter Name Temp Test Level 1 Min Typ Max Unit ENCODE INPUT PARAMETERS2 Encode Period @ 65 MSPS t ENC Full V 15.4 ns Encode Period @ 40 MSPS t ENC Full V 25 ns Encode Pulse Width High3 @ 65 MSPS t ENCH Full IV 6.2 7.7 9.2 ns Encode Pulse Width Low @ 65 MSPS t ENCL Full IV 6.2 7.7 9.2 ns ENCODE/DATA READY Encode Rising to Data Ready Falling t DR Full IV 2.6 3.4 4.6 ns Encode Rising to Data Ready Rising t E_DR t ENCH + tDR @ 65 MSPS (50% Duty Cycle) Full IV 10.3 11.1 12.3 ns @ 40 MSPS (50% Duty Cycle) Full IV 15.1 15.9 17.1 ns ENCODE/DATA (D13:0), OVR ENCODE to DATA Falling Low t E_FL Full IV 3.8 5.5 9.2 ns ENCODE to DATA Rising Low t E_RL Full IV 3.0 4.3 6.4 ns ENCODE to DATA Delay (Hold Time)4 t H_E Full IV 3.0 4.3 6.4 ns ENCODE to DATA Delay (Setup Time)5 t S_E t ENC − tE_FL Encode = 65 MSPS (50% Duty Cycle) Full IV 6.2 9.8 11.6 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 15.9 19.4 21.2 ns

Rev. D | Page 5 of 24 AD6644AST-40/65 Parameter Name Temp Test Level 1 Min Typ Max Unit DATA READY (DRY6)/DATA, OVR Data Ready to DATA Delay (Hold Time)3 t H_DR See note 7 Encode = 65 MSPS (50% Duty Cycle) Full IV 8.0 8.6 9.4 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 12.8 13.4 14.2 ns Data Ready to DATA Delay (Setup Time)3 t S_DR See note 7 @ 65 MSPS (50% Duty Cycle) Full IV 3.2 5.5 6.5 ns @ 40 MSPS (50% Duty Cycle) Full IV 8.0 10.3 11.3 ns APERTURE DELAY t A 25°C V 100 ps APERTURE UNCERTAINTY (JITTER) t J 25°C V 0.2 ps rms 1 See the Explanation of Test Levels section. 2 Several timing parameters are a function of tENC and tENCH.

3 To compensate for a change in duty cycle for tH_DR and tS_DR use the following equations:

NewtH_DR = (tH_DR − % Change(tENCH)) × tENC/2 NewtS_DR = (tS_DR − % Change(tENCH)) × tENC/2 4 ENCODE to data delay (hold time) is the absolute minimum propagation delay through the ADC. 5 ENCODE to data delay (setup time) is calculated relative to 65 MSPS (50% duty cycle). To calculate tS_E for a given encode, use the following equation: NewtS_E = tENC(NEW) − tENC + tS_E (that is, for 40 MSPS, NewtS_E(TYP) = 25 × 10−9 − 15.38 × 10−9 + 9.8 × 10−9 = 19.4 × 10−9). 6 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock correspondingly changes the duty cycle of DRY. 7 Data ready to data delay (tH_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. To calculate tH_DR and tS_DR for a given encode, use the following equations: AC SPECIFICATIONS All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V , DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, unless otherwise noted. Table 5. AD6644AST-40 AD6644AST-65 Parameter Conditions Temp Test Level 1 Min Typ Max Min Typ Max Unit SNR Analog Input 2.2 MHz 25°C V 74.5 74.5 dB @ −1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB 30.5 MHz 25°C II 73.5 72 73.5 dB SINAD2 Analog Input 2.2 MHz 25°C V 74.5 74.5 dB @ −1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB 30.5 MHz 25°C V 73.0 73.0 dB WORST HARMONIC (2ND or 3RD)2 Analog Input 2.2 MHz 25°C V 92 92 dBc @ −1 dBFS 15.5 MHz 25°C II 90 83 90 dBc

30.5 MHz 25°C V 85 85 dBc

WORST HARMONIC (4TH or Higher)2 Analog Input 2.2 MHz 25°C V 93 93 dBc @ −1 dBFS 15.5 MHz 25°C II 92 85 92 dBc

30.5 MHz 25°C V 92 92 dBc

TWO-TONE SFDR2, 3, 4 Full V 100 100 dBFS TWO-TONE IMD REJECTION2, 4 F1, F2 @ −7 dBFS Full V 90 90 dBc ANALOG INPUT BANDWIDTH 25°C V 250 250 MHz 1 See the Explanation of Test Levels section. 2 AVCC = 5 V to 5.25 V for rated ac performance. 3 Analog input signal power swept from −7 dBFS to −100 dBFS. 4 F1 = 15 MHz, F2 = 15.5 MHz.

Figure 2. Timing Diagram

and characterization at temperature extremes. V. Parameter is a typical value only. still air with a solid ground plane. Table 7. Thermal Resistance

27 GND

28 AVCC

29 GND

30 AVCC

31 DNC

32 OVR

33 DVCC

34 GND

35 DMID

36 D0 (LSB)

Figure 3. Pin Configuration Table 8. Pin Function Descriptions 1, 33, 43 DVCC 3.3 V Power Supply (Digital), Output Stage Only. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6 ENCODE Complement of ENCODE. Differential input. 12 AIN Complement of AIN. Differential analog input. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. High indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to DVCC/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit). Twos complement. Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit). Twos complement.

Rev. D | Page 13 of 24 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in the Logic 1 state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in a low state. Optimum performance is achieved using a 50% duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: ⎡ − = 001.0log10 Input ScaleFull Z rmsScaleFullV POWER Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least-square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Noise (for Any Range Within the ADC) ⎛ −−××= 1010001.0 dBFSdBcdBm NOISE SignalSNRFSZV where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. VNOISE includes both thermal and quantization noise. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE, and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Rev. D | Page 14 of 24 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in either dBc (that is, degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Reported in either dBc (that is, degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc.

only one gate should be used for all AD6644 digital outputs. isolated from the digital outputs and the analog inputs. Table 10. AD6644/PCB Bill of Materials Qty. Reference ID1 Description Manufacturer Supplier Part No.

1 PCB Printed circuit board, AD6644/AD6645 engineering

4 C1, C2, C31, C38 Capacitor, tantalum, SMT BCAPTAJC, 10 μF, 16 V, 10% Kemet T491C106K016AS

9 C4, C15, C22 to C26, C29, (C33)3 ,

1 CR13 Diode, dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX)

1 E1 Install jumper (across OPT_LAT and BUFLAT)

5 F1 to F5 EMI suppression ferrite chip, SMT 0805 Steward HZ0805E601R-00

1 J2 Header, 40-pin, male, right angle Samtec TSW-120-08-T-D-RA

1 R152 Resistor, thick film, SMT 0402, 178 Ω, 1/16 W, 1% Panasonic ERJ-2RKF1780X

2 T23, T32 Transformer, ADT4-1WT, CD542, 2 MHz to 775 MHz Mini-Circuits® ADT4-1WT

1 U1 IC, 14-bit, 65 MSPS ADC, LQFP-52 Analog Devices AD6644

2 U2, U7 IC, SOIC-20, OCTAL D-type flip-flop Fairchild 74LCX574

2 U4, U6 IC, SOT-23, tiny logic UHS 2-input or gate Fairchild NC7SZ32

1 Y1 Clock oscillator, 65 MHz CTS Reeves MX045-65

4 Y1-PS Pin sockets, closed end AMP 5-330808-3

4 STDOFF Circuit board support RICHO CBSB-14-01

1 Reference designators in parentheses are not installed on standard units. 2 AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed. 3 AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed.

  1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED.

R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.

  1. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 AND U8 ARE NOT INSTALLED.
  2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.

IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED. IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED. Figure 32. Evaluation Board Schematic

Figure 37. 52-Lead Low Profile Quad Flat Package [LQFP]

Rev. D | Page 22 of 24 NOTES

Rev. D | Page 23 of 24 NOTES

Rev. D | Page 24 of 24 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00971-0-8/07(D)